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146 Commits

Author SHA1 Message Date
Jan Vesely 452b036697 R600: Make FMIN/MAXNUM legal on all asics 
v2: Add tests

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
reviewer: arsenm
llvm-svn: 234716
 2015-04-12 23:45:05 +00:00
Matt Arsenault 8d6300346f R600: Use new fmad node. 
This enables a few useful combines that used to only
use fma.

Also since v_mad_f32 apparently does not support denormals,
disable the existing cases that are custom handled if they are
requested.

llvm-svn: 230071
 2015-02-20 22:10:41 +00:00
Tom Stellard 1ca873bbc5 R600/SI: Don't set isCodeGenOnly = 1 on all instructions 
We only need to set this on pseudo instructions which won't
be used by the assembler.

llvm-svn: 229689
 2015-02-18 16:08:17 +00:00
Matt Arsenault 284d7dfb53 R600: Fix operand encoding error 
llvm-svn: 229609
 2015-02-18 02:10:42 +00:00
Matt Arsenault 0bbcd8ba2f R600/SI: Implement correct f64 fdiv 
This version passes the OpenCL conformance test.

llvm-svn: 229239
 2015-02-14 04:30:08 +00:00
Eric Christopher 7792e32b64 Reuse a bunch of cached subtargets and remove getSubtarget calls 
without a Function argument.

llvm-svn: 227638
 2015-01-30 23:24:40 +00:00
Matt Arsenault b00554886f R600/SI: Custom lower fround 
This fixes it for SI. It also removes the pattern
used previously for Evergreen for f32. I'm not sure
if the the new R600 output is better or not, but it uses
1 fewer instructions if BFI is available.

llvm-svn: 226682
 2015-01-21 18:18:25 +00:00
Matt Arsenault 9cded7a74b R600/SI: Use unordered not equal instructions 
llvm-svn: 224065
 2014-12-11 22:15:35 +00:00
Craig Topper c50d64b07b Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. 
llvm-svn: 222801
 2014-11-26 00:46:26 +00:00
Tom Stellard 9d7ddd516e R600/SI: Start implementing an assembler 
This was done using the Sparc and PowerPC AsmParsers as guides.  So far it
is very simple and only supports sopp instructions.

llvm-svn: 221994
 2014-11-14 14:08:00 +00:00
Matt Arsenault da59f3de45 R600/SI: Fix fmin_legacy / fmax_legacy matching for SI 
select_cc is expanded on SI, so this was never matched.

llvm-svn: 221941
 2014-11-13 23:03:09 +00:00
Matt Arsenault 4cd1d4ecb1 R600: Don't unnecessarily repeat the register class 
llvm-svn: 221119
 2014-11-02 23:46:59 +00:00
Jan Vesely df19696374 R600: FMA is VecALU only instruction 
Reviewed-by: Tom Stellard <tom@stellard.net>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 219704
 2014-10-14 18:52:04 +00:00
Jan Vesely d1d1334064 R600: Fix FROUND 
round halfway cases away from zero

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <tom@stellard.net>
llvm-svn: 217250
 2014-09-05 14:26:54 +00:00
Matt Arsenault 83592a2d32 R600: Add FMA instructions for Evergreen 
llvm-svn: 213882
 2014-07-24 17:41:01 +00:00
Matt Arsenault 9acb978105 R600: Match rcp node on pre-SI 
llvm-svn: 213844
 2014-07-24 06:59:24 +00:00
Marek Olsak ba77c3e4ed R600/SI: fix shadow mapping for 1D and 2D array textures 
It was conflicting with def TEX_SHADOW_ARRAY, which also handles them.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 212829
 2014-07-11 17:11:39 +00:00
Matt Arsenault 257d48d22c R600: Fix inconsistency in rsq instructions. 
R600 was using a clamped version of rsq, but SI was not. Add a
new rsq_clamped intrinsic and use them consistently.

It's unclear to me from the documentation what behavior
the R600 instructions have, so I assume they have the legacy behavior
described by the SI documents. For R600, use RECIPSQRT_IEEE
for both llvm.AMDGPU.rsq.legacy and llvm.AMDGPU.rsq. R600 also
has RECIPSQRT_FF, which I'm not sure how it fits in here.

llvm-svn: 211637
 2014-06-24 22:13:39 +00:00
Tom Stellard 9c603ebca4 R600/SI: Add a pattern for f32 ftrunc 
llvm-svn: 211377
 2014-06-20 17:06:09 +00:00
Matt Arsenault a0050b0961 R600/SI: Add intrinsics for various math instructions. 
These will be used for custom lowering and for library
implementations of various math functions, so it's useful
to expose these as builtins.

llvm-svn: 211247
 2014-06-19 01:19:19 +00:00
Tom Stellard 880a80ad07 R600: Use LDS and vectors for private memory 
llvm-svn: 211110
 2014-06-17 16:53:14 +00:00
Tom Stellard bc5b5370de R600: Remove AMDIL instruction and register definitions 
Most of these are no longer used any more.

llvm-svn: 210915
 2014-06-13 16:38:59 +00:00
Tom Stellard 4a9cea608c R600: Set correct InstrItinClass for instructions using *Helper classes 
We weren't doing this before, so all instruction using the *Helper
classes were considered for any ALU slot.

This fixes a hang in the builtin-char-clz-1.0.generated.cl piglit test.

llvm-svn: 210703
 2014-06-11 20:51:42 +00:00
Matt Arsenault 493c5f1bc4 R600: Expand mul24 for GPUs without it 
llvm-svn: 209458
 2014-05-22 18:00:24 +00:00
Matt Arsenault f15a05623e R600: Expand mad24 for GPUs without it 
llvm-svn: 209457
 2014-05-22 18:00:20 +00:00
Tom Stellard 2c1c9de151 R600: Reorganize tablegen instruction definitions 
Each GPU family now has its own file.

llvm-svn: 204615
 2014-03-24 16:07:25 +00:00
Matt Arsenault fae02989b7 R600: Match sign_extend_inreg to BFE instructions 
llvm-svn: 204072
 2014-03-17 18:58:11 +00:00
Tom Stellard 08ef1233c6 R600: LDS instructions shouldn't implicitly define OQAP 
LDS instructions are pseudo instructions which model
the OQAP defs and uses within a single instruction.

This fixes a hang in the opencv MedianFilter tests.

llvm-svn: 203818
 2014-03-13 17:13:04 +00:00
Matt Arsenault 530dde4386 R600: Remove unnecessary build_vector pattern. 
It is already fully handled in AMDGPUISelDAGToDAG.

llvm-svn: 202312
 2014-02-26 23:00:58 +00:00
Alp Toker cb40291100 Fix known typos 
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.

llvm-svn: 200018
 2014-01-24 17:20:08 +00:00
Tom Stellard a2a4b8ee2f R600: Disable the BFE pattern 
This pattern uses an SDNodeXForm, which isn't being emitted for some
reason.  I can get it to work by attaching the PatLeaf that has the
XForm to the argument in the output pattern, but this results in an
immediate being used in a register operand, which the backend can't
handle yet.

llvm-svn: 199918
 2014-01-23 18:49:33 +00:00
Tom Stellard 59ed4794c4 R600: Add some missing CF instruction definitions to the .td files. 
reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 199841
 2014-01-22 21:55:44 +00:00
Tom Stellard afbb697e0b R600: CF_PUSH is the same on Evergreen and Cayman 
reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 199839
 2014-01-22 21:55:41 +00:00
Tom Stellard 476437cbbc R600: MOVA is vector only 
llvm-svn: 199827
 2014-01-22 19:24:24 +00:00
Tom Stellard eddfa69465 R600: Allow ftrunc 
v2: Add ftrunc->TRUNC pattern instead of replacing int_AMDGPU_trunc
v3: move ftrunc pattern next to TRUNC definition, it's available since R600

Patch By: Jan Vesely

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 197783
 2013-12-20 05:11:55 +00:00
Vincent Lejeune 4b8d9e303c R600: Workaround for cayman loop bug 
llvm-svn: 196121
 2013-12-02 17:29:37 +00:00
Tom Stellard 4d566b2edf R600: Add support for ISD::FROUND 
NOTE: This is a candidate for the 3.4 branch.
llvm-svn: 195878
 2013-11-27 21:23:20 +00:00
Tom Stellard c0845334da R600/SI: Fixing handling of condition codes 
We were ignoring the ordered/onordered bits and also the signed/unsigned
bits of condition codes when lowering the DAG to MachineInstrs.

NOTE: This is a candidate for the 3.4 branch.
llvm-svn: 195514
 2013-11-22 23:07:58 +00:00
Tom Stellard 81d871dee3 R600/SI: Add support for private address space load/store 
Private address space is emulated using the register file with
MOVRELS and MOVRELD instructions.

llvm-svn: 194626
 2013-11-13 23:36:50 +00:00
Vincent Lejeune f143af3fe9 R600: Use function inputs to represent data stored in gpr 
llvm-svn: 194425
 2013-11-11 22:10:24 +00:00
Vincent Lejeune 533352f696 R600: Clear the VPM bit of export instructions. 
It makes apparently no change it to set this bit or not but the
docs recommand to left it cleared.

llvm-svn: 192552
 2013-10-13 17:55:57 +00:00
Vincent Lejeune 6df39438af R600: Add a ldptr intrinsic to support MSAA. 
llvm-svn: 191838
 2013-10-02 16:00:33 +00:00
Vincent Lejeune a4da6fb535 R600: add a pass that merges clauses. 
llvm-svn: 191790
 2013-10-01 19:32:58 +00:00
Vincent Lejeune 269708b98d R600: Enable -verify-machineinstrs in some tests. 
llvm-svn: 191788
 2013-10-01 19:32:38 +00:00
Tom Stellard 0351ea2010 R600: Fix handling of NAN in comparison instructions 
We were completely ignoring the unorder/ordered attributes of condition
codes and also incorrectly lowering seto and setuo.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 191603
 2013-09-28 02:50:50 +00:00
Tom Stellard cd42818d86 SelectionDAG: Try to expand all condition codes using getCCSwappedOperands() 
This is useful for targets like R600, which only support GT, GE, NE, and EQ
condition codes as it removes the need to handle unsupported condition
codes in target specific code.

There are no tests with this commit, but R600 has been updated to take
advantage of this new feature, so its existing selectcc tests are now
testing the swapped operands path.

llvm-svn: 191601
 2013-09-28 02:50:38 +00:00
Aaron Watry 372cecf642 R600: Add support for LDS atomic subtract 
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 190200
 2013-09-06 20:17:42 +00:00
Tom Stellard 13c68ef88b R600: Add support for local memory atomic add 
llvm-svn: 190080
 2013-09-05 18:38:09 +00:00
Vincent Lejeune 4d5c5e53d0 R600: Use SchedModel enum for is{Trans,Vector}Only functions 
llvm-svn: 189979
 2013-09-04 19:53:30 +00:00
Tom Stellard c6f4a29ed5 R600: Add support for i8 and i16 local memory loads 
llvm-svn: 189225
 2013-08-26 15:05:59 +00:00