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4 Commits

Author SHA1 Message Date
Matt Arsenault bc276c6379 GlobalISel: Lower s1 source G_SITOFP/G_UITOFP 2019-11-15 13:37:20 +05:30
Matt Arsenault f9a42ed0a7 AMDGPU: Relax 32-bit SGPR register class 
Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This
will allow the register coalescer to do a better job eliminating
copies to m0.

For GlobalISel, as a terrible hack, use SGPR_32 for things that should
use SCC until booleans are solved.

llvm-svn: 375267
 2019-10-18 18:26:37 +00:00
Matt Arsenault fdea5e02ce AMDGPU/GlobalISel: Select s1 src G_SITOFP/G_UITOFP 
llvm-svn: 373298
 2019-10-01 02:23:20 +00:00
Matt Arsenault 0a6123595f AMDGPU/GlobalISel: Select s32->s16 G_[US]ITOFP 
llvm-svn: 371949
 2019-09-16 00:29:12 +00:00