Commit Graph

361763 Commits

Author SHA1 Message Date
David Sherwood 2078771759 [SVE][CodeGen] Add simple integer add tests for SVE tuple types
I have added tests to:

  CodeGen/AArch64/sve-intrinsics-int-arith.ll

for doing simple integer add operations on tuple types. Since these
tests introduced new warnings due to incorrect use of
getVectorNumElements() I have also fixed up these warnings in the
same patch. These fixes are:

1. In narrowExtractedVectorBinOp I have changed the code to bail out
early for scalable vector types, since we've not yet hit a case that
proves the optimisations are profitable for scalable vectors.
2. In DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS I have replaced
calls to getVectorNumElements with getVectorMinNumElements in cases
that work with scalable vectors. For the other cases I have added
asserts that the vector is not scalable because we should not be
using shuffle vectors and build vectors in such cases.

Differential revision: https://reviews.llvm.org/D84016
2020-07-29 13:32:10 +01:00
Sjoerd Meijer 85342c27a3 [ARM] Optimize immediate selection
Optimize some specific immediates selection by materializing them with sub/mvn
instructions as opposed to loading them from the constant pool.

Patch by Ben Shi, powerman1st@163.com.

Differential Revision: https://reviews.llvm.org/D83745
2020-07-29 13:29:17 +01:00
Matt Arsenault 200bb5191a AMDGPU/GlobalISel: Refactor special argument management 2020-07-29 08:27:31 -04:00
Matt Arsenault c230965ccf AMDGPU: Make saturating add/sub legal for DAG path 2020-07-29 08:27:31 -04:00
Matt Arsenault cdd45d5f9c AMDGPU/GlobalISel: Select llvm.amdgcn.global.atomic.csub
Remove the custom node boilerplate. Not sure why this tried to handle
the LDS atomic stuff.
2020-07-29 08:27:31 -04:00
Chris Gyurgyik 33abb7292e
[libc] [obvious] Fix typo in binary header. 2020-07-29 08:18:07 -04:00
David Sherwood f43b5c7a76 [SVE] Add checks for no warnings in CodeGen/AArch64/sve-sext-zext.ll
Previous patches fixed up all the warnings in this test:

  llvm/test/CodeGen/AArch64/sve-sext-zext.ll

and this change simply checks that no new warnings are added in future.

Differential revision: https://reviews.llvm.org/D83205
2020-07-29 13:06:39 +01:00
David Sherwood 5d84eafc6b [CodeGen] Remove calls to getVectorNumElements in DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR
In DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR I have replaced
calls to getVectorNumElements with getVectorMinNumElements, since
this code path works for both fixed and scalable vector types. For
scalable vectors the index will be multiplied by VSCALE.

Fixes warnings in this test:

  sve-sext-zext.ll

Differential revision: https://reviews.llvm.org/D83198
2020-07-29 13:05:39 +01:00
Alex Zinenko aec38c619d [mlir] LLVMType: make getUnderlyingType private
The current modeling of LLVM IR types in MLIR is based on the LLVMType class
that wraps a raw `llvm::Type *` and delegates uniquing, printing and parsing to
LLVM itself. This is model makes thread-safe type manipulation hard and is
being progressively replaced with a cleaner MLIR model that replicates the type
system. In the new model, LLVMType will no longer have an underlying LLVM IR
type. Restrict access to this type in the current model in preparation for the
change.

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D84389
2020-07-29 13:43:38 +02:00
Florian Hahn 2aa2c40d23 [NewGVN] Require asserts for crashing tests.
Without asserts, it might take a long time for the tests to crash.
Only run them with assert builds.
2020-07-29 12:41:05 +01:00
Yevgeny Rouban 5d6cd61904 [LoopSimplifyCFG] Delete landing pads in dead exit blocks
In addition to removing phi nodes this patch removes any
landing pad that the dead exit block might have. Without
this fix Verifier complains about a new switch instruction
jumps to a block with a landing pad.

Differential Revision: https://reviews.llvm.org/D84320
2020-07-29 18:36:51 +07:00
Pushpinder Singh c970bb5b34 [CMAKE] Fix 'clean' target not working
cmake was still considering the empty value of ${fake_version_inc}
even if it was not defined.

Reviewed By: vsapsai

Differential Revision: https://reviews.llvm.org/D82847
2020-07-29 07:34:24 -04:00
Simon Pilgrim c5ef1f1edd [TTI] Add default cost expansion for abs/smax/smin/umax/umin intrinsics 2020-07-29 12:13:06 +01:00
Georgii Rymar 08a265435b [llvm-readobj] - Move out the common code from printRelocations() methods.
This introduces the printRelocationsHelper() which now contains the common
code used by both GNU and LLVM output styles.

Differential revision: https://reviews.llvm.org/D83935
2020-07-29 13:52:02 +03:00
Hafiz Abid Qadeer 380fee34d2 [libunwind] Provide a way to set '_LIBUNWIND_IS_BAREMETAL' through cmake.
Libunwind uses _LIBUNWIND_IS_BAREMETAL in a lot of places but there is no cmake variable to set it. This patch adds such a variable. It is quite like what LIBCXXABI_BAREMETAL does in libcxxabi.

Reviewed By: compnerd, #libunwind

Differential Revision: https://reviews.llvm.org/D84759
2020-07-29 11:48:28 +01:00
Frederik Gossen b6b9d3ea85 [MLIR][Shape] Remove type conversion from lowering to standard
Operating on indices and extent tensors directly, the type conversion is no
longer needed for the supported cases.

Differential Revision: https://reviews.llvm.org/D84442
2020-07-29 10:48:05 +00:00
Stephan Herhut 5d9f33aaa0 [MLIR][Shape] Add conversion for missing ops to standard
This adds conversions for const_size and to_extent_tensor. Also, cast-like operations are now folded away if the source and target types are the same.

Differential Revision: https://reviews.llvm.org/D84745
2020-07-29 12:46:18 +02:00
Simon Pilgrim 0c005be6eb [X86][SSE] getV4X86ShuffleImm8 - canonicalize broadcast masks
If the mask input to getV4X86ShuffleImm8 only refers to a single source element (+ undefs) then canonicalize to a full broadcast.

getV4X86ShuffleImm8 defaults to inline values for undefs, which can be useful for shuffle widening/narrowing but does leave SimplifyDemanded* calls thinking the shuffle depends on unnecessary elements.

I'm still investigating what we should do more generally to avoid these undemanded elements, but broadcast cases was a simpler win.
2020-07-29 11:32:44 +01:00
Frederik Gossen 2e7baf6197 [MLIR][Shape] Allow `shape.add` to operate on indices
Differential Revision: https://reviews.llvm.org/D84441
2020-07-29 10:23:37 +00:00
Xing GUO 2f98eff345 [DWARFYAML][test] Make the check lines stricter. NFC.
This patch makes the check lines stricter.
2020-07-29 17:31:38 +08:00
Xing GUO 334a7025e0 [DWARFYAML] Replace uint*_t with yaml::Hex* in the 'debug_aranges' entry.
Normally, we use yaml::Hex* to describe the length, offsets,
address/segment size. NFC.
2020-07-29 16:43:21 +08:00
Kirill Bobyrev 1603470e59
[clangd] Fix clangd-indexeer builds after D84697
Some buildbots require explicit clangdSupport dependency:

http://lab.llvm.org:8011/builders/llvm-avr-linux/builds/3996/steps/build%20stage%201/logs/stdio
2020-07-29 10:27:11 +02:00
George Mitenkov 1f4aa30a4f [MLIR][SPIRVToLLVM] Branch weights support for BranchConditional conversion
Conversion of `spv.BranchConditional` now supports branch weights
that are mapped to weights vector in `llvm.cond_br`.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D84657
2020-07-29 10:11:10 +03:00
Nathan Ridge 89247792c5 [clang] Fix ConceptSpecializationExpr::getEndLoc()
Summary:
It returned an invalid location in case of a constrained-parameter
with no explicit arguments.

Reviewers: hokein

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D84613
2020-07-29 02:44:26 -04:00
Juneyoung Lee 1ae766e3e0 [InstCombine] Add tests for select(freeze(undef)); NFC 2020-07-29 15:27:09 +09:00
Stephan Bergmann 2ead4fca79 Test including rpc/xdr.h requires sunrpc
...which is set based on HAVE_RPC_XDR_H.  At least Fedora 32 does not have a
/usr/include/rpc/xdr.h, so failed this test introduced with
<https://reviews.llvm.org/D83358> "[Sanitizers] Add interceptor for
xdrrec_create".

Differential Revision: https://reviews.llvm.org/D84740
2020-07-29 08:20:20 +02:00
George Mitenkov 8a66bb7a75 [MLIR][SPIRV] Added storage class constraint on global variable
Added a check for 'Function' storage class in `spv.globalVariable`
verifier since it only can be used with `spv.Variable`.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D84731
2020-07-29 09:15:00 +03:00
George Mitenkov b1e398920f [MLIR][SPIRVToLLVM] Support of volatile/nontemporal memory access in load/store
This patch adds support of Volatile and Nontemporal
memory accesses to `spv.Load` and `spv.Store`. These attributes are
modelled with a `volatile` and `nontemporal` flags.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D84739
2020-07-29 08:45:40 +03:00
Anh Tuyen Tran 8dbe9b2498 [Clang-tools-extra] Mark override a function which overrides a virtual one
Function void run() on line 286 overrides a virtual function on line 92 of
clang-tools-extra/clangd/index/dex/dexp/Dexp.cpp.  Not marking it override will
cause a build failure when we use -Werror (every warning is treated as an error).

Reviewed By: kbobyrev (Kirill Bobyrev)

Differential Revision: https://reviews.llvm.org/D84794
2020-07-29 05:30:33 +00:00
Azharuddin Mohammed 60c889cf71 [ThinLTO] [test] cache.ll: Prevent Spotlight indexing of the output dir
The test output files whose atime is altered in the test were getting
accessed by Spotlight indexing on macOS, causing them to get an updated
atime and leading to the test not behaving as expected.

Reviewed By: jhenderson, steven_wu

Differential Revision: https://reviews.llvm.org/D84700
2020-07-28 21:21:58 -07:00
Ikhlas Ajbar d50d4c3d44 [Hexagon] Correct the order of operands when lowering funnel shift-left
This patch corrects the order of operands in the pattern that lowers fshl
in Hexagon.
2020-07-28 21:22:41 -05:00
Chuanqi Xu d3527052fc [NFC] Edit the comment for the return type of await_suspend 2020-07-29 10:20:55 +08:00
Chuanqi Xu dd4106d22e [NFC] Edit the comment in User::replaceUsesOfWith 2020-07-29 10:02:04 +08:00
Xing GUO c12394fef3 [llvm-readelf][test] Improve wording in the comments. NFC.
This patch addresses comments in D84640 (https://reviews.llvm.org/D84640#2178475).
2020-07-29 09:59:28 +08:00
Artem Dergachev c26f237cef [analyzer] FuchsiaHandleChecker: Suppress a non-deterministic test failure.
Noticed by Jon Roelofs in https://reviews.llvm.org/D73151#2180499
2020-07-28 18:57:11 -07:00
Stefanos Baziotis db0d636e52 [ADT][BitVector][NFC] Merge find_first_in() / find_first_unset_in()
We can implement find_first_unset_in() in the same function
if every BitWord we use is first flipped.

Differential Revision: https://reviews.llvm.org/D84717
2020-07-29 04:51:22 +03:00
Kang Zhang 00046d789c [PowerPC] Add Def CR1 for MTFSFI_rec and MTFSF_rec 2020-07-29 01:47:23 +00:00
Matt Arsenault 44211f20a8 AMDGPU: Optimize copies to exec with other insts after exec def
It's possible to have terminator instructions after a write to exec,
so skip over them to find it.
2020-07-28 21:34:50 -04:00
Matt Arsenault b6ebc77326 AMDGPU/GlobalISel: Fix selecting llvm.amdgcn.s.getreg
This introduces the same bug llvm.amdgcn.s.setreg has where if the
user specified an immediate outside of the valid 16-bit range, it will
select into a verifier error.
2020-07-28 21:34:50 -04:00
Rahul Joshi 706d992ced [NFC] Add getArgumentTypes() to Region
- Add getArgumentTypes() to Region (missed from before)
- Adopt Region argument API in `hasMultiplyAddBody`
- Fix 2 typos in comments

Differential Revision: https://reviews.llvm.org/D84807
2020-07-28 18:27:42 -07:00
Thomas Lively 11bb7eef41 [WebAssembly] Remove intrinsics for SIMD widening ops
Instead, pattern match extends of extract_subvectors to generate
widening operations. Since extract_subvector is not a legal node, this
is implemented via a custom combine that recognizes extract_subvector
nodes before they are legalized. The combine produces custom ISD nodes
that are later pattern matched directly, just like the intrinsic was.

Also removes the clang builtins for these operations since the
instructions can now be generated from portable code sequences.

Differential Revision: https://reviews.llvm.org/D84556
2020-07-28 18:25:55 -07:00
Craig Topper 06cf6f770d [X86] Add FeatureCMPXCHG8B and FeatureSlowUAMem16 to 'lakemont' in X86.td
We already had CMPXCH8B feature on this CPU for the frontend so
this doesn't have much effect.

The FeatureSlowUAMem16 only matters if someone compiles with
-march=lakemont -msse which doesn't make sense, but is consistent
with all our pre-sse4.2 CPUs. Maybe the feature flag should be
FeatureFastUAMem16 and set on the newer CPUs instead.
2020-07-28 18:24:46 -07:00
Matt Arsenault 6a7b6dd54b AMDGPU: Don't assert in canInsertSelect
Currently GlobalISel doesn't force all VGPR phi operands to VGPRs, so
this hit a case where it was queried with a VGPR and SGPR. This could
arguably be a verifier error, but it's currently not.
2020-07-28 21:01:06 -04:00
Valentin Clement e8d4038efb [openmp][openacc][NFC] Add wrapper for records in DirectiveEmitter
Add wrapper classes to to access record's fields. This makes it easier to
pass record information to the diverse functions for code generation.

Reviewed By: jdenny

Differential Revision: https://reviews.llvm.org/D84612
2020-07-28 20:47:40 -04:00
Thomas Lively ffd8c23ccb [WebAssembly] Implement truncating vector stores
Rather than expanding truncating stores so that vectors are stored one
lane at a time, lower them to a sequence of instructions using
narrowing operations instead, when possible. Since the narrowing
operations have saturating semantics, but truncating stores require
truncation, mask the stored value to manually truncate it before
narrowing. Also, since narrowing is a binary operation, pass in the
original vector as the unused second argument.

Differential Revision: https://reviews.llvm.org/D84377
2020-07-28 17:46:45 -07:00
Matt Arsenault 068808d102 AMDGPU: Don't assume call targets are registers
GlobalISel let through a call to null, which would then fold into the
source operand like any other inline immediate. The SelectionDAG
lowering deletes calls to null and undef as a workaround from before
calls were supported. We should probably drop the special handling
case in the DAG lowering now, since the middle end optimizers delete
null calls anyway.
2020-07-28 20:46:06 -04:00
Shilei Tian 30440924d4 [OpenMP] Replaced mutex lock/unlock in `target` with `std::lock_guard`
Reviewed By: ye-luo

Differential Revision: https://reviews.llvm.org/D84799
2020-07-28 20:31:40 -04:00
Joel E. Denny 69fc33f0cd Revert "[OpenMP] Implement TR8 `present` motion modifier in Clang (1/2)"
This reverts commit 3c3faae497.

It breaks a number of bots.
2020-07-28 20:30:05 -04:00
Joel E. Denny 65564e5eaf Revert "[OpenMP] Implement TR8 `present` motion modifier in runtime (2/2)"
This reverts commit 2cb926a447.

It depends on 3c3faae497, which is being
reverted.
2020-07-28 20:30:05 -04:00
Matt Arsenault 8860daf0ed AMDGPU: Handle a few missing cases in getAddrModeArguments 2020-07-28 20:22:38 -04:00