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5 Commits

Author SHA1 Message Date
Eli Friedman c60a23a6af [LegalizeDAG] Fix ATOMIC_CMP_SWAP_WITH_SUCCESS legalization. 
The code wasn't zero-extending correctly, so the comparison could
spuriously fail.

Adds some AArch64 tests to cover this case.

Inspired by D41791.

Differential Revision: https://reviews.llvm.org/D41798

llvm-svn: 322767
 2018-01-17 22:04:36 +00:00
Chad Rosier 71070856e6 [AArch64] Add basic support for Qualcomm's Saphira CPU. 
llvm-svn: 314105
 2017-09-25 14:05:00 +00:00
Joel Jones 60711ca253 [AArch64] LSE Atomics reorg - part 1 
Add memory synchronization semantics to LSE Atomics.

The memory semantics feature will be added in a subsequent patch.

In this patch, several corrections were added to the existing LSE Atomics
implementation, based on the ARM Errata D11904 from 05/12/2017.

Patch by: steleman

Differential Revision: https://reviews.llvm.org/D35319

llvm-svn: 310167
 2017-08-05 04:30:55 +00:00
Matthew Simpson 06e6a6bdff [AArch64] Add preliminary support for ARMv8.1 SUB/AND atomics 
This patch is a follow-up to r305893 and adds preliminary support for the
fetch_sub and fetch_and operations.

llvm-svn: 307913
 2017-07-13 15:01:23 +00:00
Christof Douma 1ee68828b2 [AARCH64][LSE] Preliminary support for ARMv8.1 LSE Atomics. 
Added test file for ARMv8.1 LSE Atomics that I forgot to include in
commit r305893.

Patch by Ananth Jasty.

Differential Revision: https://reviews.llvm.org/D33586

Change-Id: Ic1ad8ed87c1b584c4c791b459a686c866a3c3087
llvm-svn: 305918
 2017-06-21 15:18:39 +00:00