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289 Commits

Author SHA1 Message Date
Craig Topper b94011fd28 Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. 
llvm-svn: 186274
 2013-07-14 04:42:23 +00:00
Jakob Stoklund Olesen db429d9483 Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes. 
These exception-related opcodes are not used any longer.

llvm-svn: 185625
 2013-07-04 13:54:20 +00:00
Jakob Stoklund Olesen a1f5b901a5 Revert r185595-185596 which broke buildbots. 
Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."

llvm-svn: 185600
 2013-07-04 00:26:30 +00:00
Jakob Stoklund Olesen f33ec531fa Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes. 
These exception-related opcodes are not used any longer.

llvm-svn: 185596
 2013-07-03 23:56:31 +00:00
Benjamin Kramer 755bf4f692 Hexagon: Avoid unused variable warnings in Release builds. 
llvm-svn: 185445
 2013-07-02 17:24:00 +00:00
Richard Trieu fab01e5cea Change if (cond) ... else llvm_unreachable("text") to assert(cond && "text") ... 
llvm-svn: 185392
 2013-07-01 23:06:23 +00:00
Richard Trieu d7fd95a5c1 Change assert(0 && "text") to llvm_unreachable(0 && "text") 
llvm-svn: 185243
 2013-06-28 23:46:19 +00:00
Richard Trieu 4d18c9cc4e Fix broken asserts that never fire. 
Change assert("text") to assert(0 && "text").  The first case is a const char *
to bool conversion, which always evaluates to true, never triggering the
assert.  The second case will always trigger the assert.

llvm-svn: 185227
 2013-06-28 21:54:25 +00:00
Chad Rosier 295bd43adb The getRegForInlineAsmConstraint function should only accept MVT value types. 
llvm-svn: 184642
 2013-06-22 18:37:38 +00:00
Bill Wendling a3cd350249 Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 
llvm-svn: 184360
 2013-06-19 21:36:55 +00:00
David Blaikie b735b4d6db DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs 
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.

llvm-svn: 184067
 2013-06-16 20:34:27 +00:00
Andrew Trick de2109eb4c Machine Model: Add MicroOpBufferSize and resource BufferSize. 
Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize

These can be used to more precisely model instruction execution if desired.

Disabled some misched tests temporarily. They'll be reenabled in a few commits.

llvm-svn: 184032
 2013-06-15 04:49:57 +00:00
Bill Wendling 4a7a408eaa Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

llvm-svn: 183490
 2013-06-07 06:19:56 +00:00
Bill Wendling f77190855d Cache the TargetLowering info object as a pointer. 
Caching it as a pointer allows us to reset it if the TargetMachine object
changes.

llvm-svn: 183361
 2013-06-06 00:43:09 +00:00
Ahmed Bougacha b1a4d9da3b Make SubRegIndex size mandatory, following r183020. 
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.

llvm-svn: 183061
 2013-05-31 23:45:26 +00:00
Andrew Trick ad6d08ac6f Order CALLSEQ_START and CALLSEQ_END nodes. 
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.

Patch by Xiaoyi Guo!

This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.

llvm-svn: 182885
 2013-05-29 22:03:55 +00:00
Jyotsna Verma cceafb2d6d Hexagon: Typo fix. 
llvm-svn: 182790
 2013-05-28 19:01:45 +00:00
Andrew Trick ef9de2a739 Track IR ordering of SelectionDAG nodes 2/4. 
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

llvm-svn: 182703
 2013-05-25 02:42:55 +00:00
Benjamin Kramer e79beacb32 Hexagon: Make helper functions static. 
llvm-svn: 182588
 2013-05-23 15:43:11 +00:00
Jyotsna Verma 1b056e422c Hexagon: SelectionDAG should not use MVT::Other to check the legality of BR_CC. 
llvm-svn: 182390
 2013-05-21 15:54:32 +00:00
Matt Arsenault 75865923c9 Add LLVMContext argument to getSetCCResultType 
llvm-svn: 182180
 2013-05-18 00:21:46 +00:00
Benjamin Kramer 2057a2b86f Don't cast away constness. 
llvm-svn: 182086
 2013-05-17 11:39:41 +00:00
Rafael Espindola 63d2e0ad9a Remove dead calls to addFrameMove. 
Without a PROLOG_LABEL present, the cfi instructions are never printed.

llvm-svn: 182016
 2013-05-16 15:08:37 +00:00
Jyotsna Verma 803e506fec Hexagon: Pass to replace tranfer/copy instructions into combine instruction 
where possible.

llvm-svn: 181817
 2013-05-14 18:54:06 +00:00
Jyotsna Verma 2dca82ad1c Hexagon: Add patterns to generate 'combine' instructions. 
llvm-svn: 181805
 2013-05-14 17:16:38 +00:00
Jyotsna Verma 11bd54afd6 Hexagon: ArePredicatesComplement should not restrict itself to TFRs. 
llvm-svn: 181803
 2013-05-14 16:36:34 +00:00
Jyotsna Verma c61e350a7d Hexagon: Remove dead-code after unconditional return from addPreSched2. 
llvm-svn: 181797
 2013-05-14 15:33:27 +00:00
Duncan Sands 0480b9b54e Suppress GCC compiler warnings in release builds about variables that are only 
read in asserts.

llvm-svn: 181689
 2013-05-13 07:50:47 +00:00
Rafael Espindola 227144c23c Remove the MachineMove class. 
It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.

I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.

llvm-svn: 181680
 2013-05-13 01:16:13 +00:00
Rafael Espindola 1b09836bc3 Change getFrameMoves to return a const reference. 
To add a frame now there is a dedicated addFrameMove which also takes
care of constructing the move itself.

llvm-svn: 181657
 2013-05-11 02:38:11 +00:00
Jyotsna Verma bf0bd1f4ab Fix unused variable error. 
Earlier, this variable was used in an assert and was causing failure on
darwin.

llvm-svn: 181630
 2013-05-10 21:44:02 +00:00
Jyotsna Verma 438cec566b Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore. 
No functionality change.

llvm-svn: 181628
 2013-05-10 20:58:11 +00:00
Jyotsna Verma 300f0b966c Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp. 
llvm-svn: 181624
 2013-05-10 20:27:34 +00:00
Rafael Espindola 140a837acd Remove unused argument. 
llvm-svn: 181618
 2013-05-10 18:16:59 +00:00
Rafael Espindola 7501a81a50 Remove unused function. 
llvm-svn: 181606
 2013-05-10 16:53:12 +00:00
Jyotsna Verma 00681dc1f0 Hexagon: Remove switch cases from GetDotNewPredOp and isPostIncrement functions. 
No functionality change.

llvm-svn: 181535
 2013-05-09 19:16:07 +00:00
Jyotsna Verma 978e972ff9 Hexagon: Use relation map for getMatchingCondBranchOpcode() and 
getInvertedPredicatedOpcode() functions instead of switch cases.

llvm-svn: 181530
 2013-05-09 18:25:44 +00:00
Jyotsna Verma 5eb598001c Hexagon: Fix Small Data support to handle -G 0 correctly. 
llvm-svn: 181344
 2013-05-07 19:53:00 +00:00
Jyotsna Verma 03c6ca905c Reverting r181331. 
Missing file, HexagonSplitConst32AndConst64.cpp, from lib/Target/Hexagon/CMakeLists.txt.

llvm-svn: 181334
 2013-05-07 17:12:35 +00:00
Jyotsna Verma 19f0b40dcf Hexagon: Fix Small Data support to handle -G 0 correctly. 
llvm-svn: 181331
 2013-05-07 16:42:15 +00:00
Jyotsna Verma a03eb9b5d5 Hexagon: Set accessSize and addrMode on all load/store instructions. 
llvm-svn: 181324
 2013-05-07 15:06:29 +00:00
Krzysztof Parzyszek 18ee1193bf Print IR from Hexagon MI passes with -print-before/after-all. 
llvm-svn: 181255
 2013-05-06 21:58:00 +00:00
Krzysztof Parzyszek 59df52c585 Cleanup of the HexagonTargetMachine setup. 
llvm-svn: 181250
 2013-05-06 21:25:45 +00:00
Jyotsna Verma 84c471029b Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. 
llvm-svn: 181235
 2013-05-06 18:49:23 +00:00
Krzysztof Parzyszek d50074712f Make references to HexagonTargetMachine "const". 
llvm-svn: 181233
 2013-05-06 18:38:37 +00:00
Krzysztof Parzyszek cd410d04db Use consistent function names. 
llvm-svn: 181090
 2013-05-04 01:30:49 +00:00
Reid Kleckner 1c76f155b1 Fix missing include in Hexagon code for Release+Asserts 
llvm-svn: 180983
 2013-05-03 00:54:56 +00:00
Jyotsna Verma a841af7556 reverting r180953 
llvm-svn: 180964
 2013-05-02 22:10:59 +00:00
Jyotsna Verma 7e7c730c4f Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. 
llvm-svn: 180953
 2013-05-02 21:21:57 +00:00
Pranav Bhandarkar 7dda912cd7 Hexagon - Add peephole optimizations for zero extends. 
* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a
	sequence of a pair of i32->i64 extensions followed by a "bitwise or"
	into COMBINE_rr.
	* lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the
	instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg.
	* test/CodeGen/Hexagon/union-1.ll: New test.
	* test/CodeGen/Hexagon/combine_ir.ll: Fix test.

llvm-svn: 180946
 2013-05-02 20:22:51 +00:00