llvm-project

Commit Graph

Author	SHA1	Message	Date
Kevin Enderby	6c7279ec2e	Fix the encoding of the armv7m (MClass) for MSR registers other than aspr, iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits. llvm-svn: 158560	2012-06-15 22:14:44 +00:00
Kevin Enderby	f1b225d0e0	Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in the code for better error checking when versions shouldn't be used. rdar://11457025 llvm-svn: 157019	2012-05-17 22:18:01 +00:00
James Molloy	21efa7d6e1	Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a slightly different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. llvm-svn: 140696	2011-09-28 14:21:38 +00:00

Author

SHA1

Message

Date

Kevin Enderby

6c7279ec2e

Fix the encoding of the armv7m (MClass) for MSR registers other than aspr,

iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits.

llvm-svn: 158560

2012-06-15 22:14:44 +00:00

Kevin Enderby

f1b225d0e0

Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing

the 0b10 mask encoding bits.  Make MSR APSR writes without a _<bits> qualifier
an alias for MSR APSR_nzcvq even though ARM as deprecated it use.  Also add
support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions.  Some FIXMEs in
the code for better error checking when versions shouldn't be used.
rdar://11457025

llvm-svn: 157019

2012-05-17 22:18:01 +00:00

James Molloy

21efa7d6e1

Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.

Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.

llvm-svn: 140696

2011-09-28 14:21:38 +00:00

3 Commits