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190 Commits

Author SHA1 Message Date
Jiangning Liu 6a43bf7d74 Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue. 
llvm-svn: 161162
 2012-08-02 08:29:50 +00:00
Jiangning Liu 288e1af8c8 Fix #13138, a bug around ARM instruction DSB encoding and decoding issue. 
llvm-svn: 161161
 2012-08-02 08:21:27 +00:00
Jiangning Liu 10dd40e42d Fix #13241, a bug around shift immediate operand for ARM instruction ADR. 
llvm-svn: 161159
 2012-08-02 08:13:13 +00:00
Jim Grosbach cb540f5cff ARM: Define generic HINT instruction. 
The NOP, WFE, WFI, SEV and YIELD instructions are all hints w/
a different immediate value in bits [7,0]. Define a generic HINT
instruction and refactor NOP, WFI, WFI, SEV and YIELD to be
assembly aliases of that.

rdar://11600518

llvm-svn: 158674
 2012-06-18 19:45:50 +00:00
Jim Grosbach 1d20efb837 ARM: Add a few missing add->sub aliases w/ 'w' suffix. 
Aliases for adding a negative immediate when using an explicit 'w'
suffix. E.g.,
        adds.w r2, #-16
        adds.w r2, r2, #-16
        addw r2, #-16
        addw r2, #-16
        addw r2, r2, #-16

rdar://11330769

llvm-svn: 155946
 2012-05-01 21:17:34 +00:00
Jim Grosbach c6f32b3295 ARM: Thumb add(sp plus register) asm constraints. 
Make sure when parsing the Thumb1 sp+register ADD instruction that
the source and destination operands match. In thumb2, just use the
wide encoding if they don't. In Thumb1, issue a diagnostic.

rdar://11219154

llvm-svn: 155748
 2012-04-27 23:51:36 +00:00
Richard Barton 82f95ea2ad Fix ARM assembly parsing for upper case condition codes on IT instructions. 
llvm-svn: 155720
 2012-04-27 17:34:01 +00:00
Evan Cheng 8a8e9d1b63 Specify cpu to unbreak tests. 
llvm-svn: 155604
 2012-04-26 01:38:10 +00:00
Jim Grosbach df5a244797 ARM fix cc_out operand handling for t2SUBrr instructions. 
We were incorrectly conflating some add variants which don't have a
cc_out operand with the mirroring sub encodings, which do. Part of the
awesome non-orthogonality legacy of thumb1. Similarly, handling of
add/sub of an immediate was sometimes incorrectly removing the cc_out
operand for add/sub register variants.

rdar://11216577

llvm-svn: 154411
 2012-04-10 17:31:55 +00:00
Jim Grosbach 3d00eecc53 ARM assembly parsing for 'msr' plain 'cpsr' operand. 
Plain 'cpsr' is an alias for 'cpsr_fc'.

rdar://11153753

llvm-svn: 154080
 2012-04-05 03:17:53 +00:00
Jim Grosbach fdaab531b7 ARM assembler should prefer non-aliases encoding of cmp. 
When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg,
we want to use the non-negated form to make sure we prefer the normal
encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'.

llvm-svn: 153770
 2012-03-30 19:59:02 +00:00
Jim Grosbach def5e34812 ARM integrated assembler should encoding choice for add/sub imm. 
For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2
can be used for this syntax. Prefer the narrow encoding when possible.

rdar://11156277

llvm-svn: 153759
 2012-03-30 17:20:40 +00:00
Jim Grosbach 199ab90946 ARM assembly parsing needs to be paranoid about negative immediates. 
Make sure to treat immediates as unsigned when doing relative comparisons.

rdar://11153621

llvm-svn: 153753
 2012-03-30 16:31:31 +00:00
Jim Grosbach 7cb9a13b02 ARM optional operand on MRC/MCR assembly instructions. 
rdar://11058464

llvm-svn: 152883
 2012-03-16 00:45:58 +00:00
Jim Grosbach 94298a906a Thumb2 alternate syntax for LDR(literal) and friends. 
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".

rdar://10250964

llvm-svn: 148432
 2012-01-18 22:46:46 +00:00
Jim Grosbach 8c59bbc1ed Thumb2 assembly parsing of 'mov rd, rn, rrx'. 
Maps to the RRX instruction. Missed this case earlier.

rdar://10615373

llvm-svn: 147096
 2011-12-21 21:04:19 +00:00
Jim Grosbach b3ef713e44 Thumb2 assembly parsing of 'mov(register shifted register)' aliases. 
These map to the ASR, LSR, LSL, ROR instruction definitions.

rdar://10615373

llvm-svn: 147094
 2011-12-21 20:54:00 +00:00
Jim Grosbach a342667fd0 ARM/Thumb2 'cmp rn, #imm' alias to cmn. 
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.

rdar://10552389

llvm-svn: 146567
 2011-12-14 17:30:24 +00:00
Jim Grosbach 485e5622f4 Thumb2 assembler aliases for "mov(shifted register)" 
rdar://10549767

llvm-svn: 146520
 2011-12-13 22:45:11 +00:00
Jim Grosbach dce106940e Test for 146516 
llvm-svn: 146517
 2011-12-13 21:06:59 +00:00
Jim Grosbach 1f1a3598c2 ARM thumb2 parsing of "rsb rd, rn, #0". 
rdar://10549741

llvm-svn: 146515
 2011-12-13 20:50:38 +00:00
Jim Grosbach 561e4e18cf ARM pre-UAL NEG mnemonic for convenience when porting old code. 
llvm-svn: 146511
 2011-12-13 20:23:22 +00:00
Jim Grosbach 18b0e5dca0 Thumb2 alias for long-form pop and friends. 
rdar://10542474

llvm-svn: 146046
 2011-12-07 18:32:28 +00:00
Jim Grosbach 5f143be8c5 Thumb2: MUL two-operand form encoding operand order fix. 
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.

rdar://10532439

llvm-svn: 145922
 2011-12-06 05:03:45 +00:00
Jim Grosbach 175c7d0da5 Thumb2 encoding choice correction for PLD. 
Using encoding T1 for offset of #0 and encoding T2 for #-0.

rdar://10532413

llvm-svn: 145919
 2011-12-06 04:49:29 +00:00
Jim Grosbach 8b5e92577b Update tests for r145860. Add a few new ones. 
llvm-svn: 145861
 2011-12-05 22:21:28 +00:00
Jim Grosbach ec9ba98299 Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions. 
rdar://10529348

llvm-svn: 145851
 2011-12-05 21:06:26 +00:00
Jim Grosbach 68c899c211 Testcase for r144684. 
llvm-svn: 144685
 2011-11-15 19:56:17 +00:00
Jim Grosbach 6efa7b9852 Thumb2 assembly parsing for mul.w in IT block fix. 
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.

rdar://10449281

llvm-svn: 144679
 2011-11-15 19:29:45 +00:00
Jim Grosbach 9bded9dc24 Thumb2 parsing for push/pop w/ hi registers in the reglist. 
rdar://10130228.

llvm-svn: 144331
 2011-11-10 23:17:11 +00:00
Jim Grosbach 25bc090170 Thumb2 assembly parsing STMDB w/ optional .w suffix. 
rdar://10422955

llvm-svn: 144242
 2011-11-09 23:44:23 +00:00
Jim Grosbach b009a872d7 Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm". 
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
  mov r2, #-3
becomes
  mvn r2, #2

rdar://10349224

llvm-svn: 143235
 2011-10-28 22:36:30 +00:00
Jim Grosbach 7a49575d7f Thumb2 ADD/SUB instructions encoding selection outside IT block. 
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).

rdar://10348481

llvm-svn: 143201
 2011-10-28 16:57:07 +00:00
Jim Grosbach 6ed3845530 Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix. 
rdar://10348844

llvm-svn: 143110
 2011-10-27 17:33:59 +00:00
Jim Grosbach ba7f90c7df Thumb2 t2MVNi assembly parsing to recognize ".w" suffix. 
rdar://10348584

llvm-svn: 143108
 2011-10-27 17:16:55 +00:00
Jim Grosbach 61fdba048f Thumb2 ldr pc-relative encoding fixes. 
We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.

More of rdar://10348687

llvm-svn: 143068
 2011-10-26 22:22:01 +00:00
Jim Grosbach 54a20ed0f1 Thumb2 assembly parsing and encoding for LDC/STC. 
llvm-svn: 141811
 2011-10-12 20:54:17 +00:00
Jim Grosbach c63af1b7b6 ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w. 
Add inst alias to handle these assembly forms. Add tests, too.

rdar://10178799

llvm-svn: 140647
 2011-09-27 22:18:54 +00:00
Owen Anderson d20cd25c69 Remove incorrect testcases. 
llvm-svn: 140572
 2011-09-26 22:13:55 +00:00
Owen Anderson 4916840eb8 Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0. 
llvm-svn: 140426
 2011-09-23 22:25:02 +00:00
Owen Anderson fbe52c0192 Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused. 
llvm-svn: 140284
 2011-09-21 23:53:44 +00:00
Jim Grosbach c70d9dfaea Thumb2 assembly parsing and encoding for WFE/WFI/YIELD. 
llvm-svn: 140126
 2011-09-20 00:48:56 +00:00
Jim Grosbach b35198021a Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH. 
llvm-svn: 140125
 2011-09-20 00:46:54 +00:00
Jim Grosbach 5aaeb91ca6 Thumb2 assembly parsing and encoding for USUB8/USUB16. 
llvm-svn: 140120
 2011-09-20 00:31:57 +00:00
Jim Grosbach 716f17399e Thumb2 assembly parsing and encoding for USAX. 
llvm-svn: 140119
 2011-09-20 00:30:45 +00:00
Jim Grosbach 42f7b647fa Thumb2 assembly parsing and encoding for USAT16. 
llvm-svn: 140118
 2011-09-20 00:28:25 +00:00
Jim Grosbach e0493ade65 Thumb2 assembly parsing and encoding for USAT. 
llvm-svn: 140117
 2011-09-20 00:27:36 +00:00
Jim Grosbach db6d378f80 Thumb2 assembly parsing and encoding for UQSAD8/USADA8. 
llvm-svn: 140113
 2011-09-20 00:23:51 +00:00
Jim Grosbach 6286f75161 Thumb2 assembly parsing and encoding for UQSUB16/UQSUB8. 
llvm-svn: 140112
 2011-09-20 00:20:44 +00:00
Jim Grosbach 62f8eee0eb Thumb2 assembly parsing and encoding for UQASX/UQSAX. 
llvm-svn: 140111
 2011-09-20 00:18:52 +00:00