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101 Commits

Author SHA1 Message Date
Michael Zuckerman 927fdaee88 [LLVM][AVX512]PSRAWI Change imm8 to int. 
Differential Revision: http://reviews.llvm.org/D17705

llvm-svn: 262480
 2016-03-02 12:05:07 +00:00
Michael Zuckerman 96836fc81c [AVX512][PSLLW ][PSLLV] Change imm8 to int 
Differential Revision: http://reviews.llvm.org/D17684

llvm-svn: 262176
 2016-02-28 07:32:10 +00:00
Michael Zuckerman a1f2d27da2 [LLVM][AVX512][PSHUFHW ][PSHUFLW ] Change imm8 to int 
Differential Revision: http://reviews.llvm.org/D17538

llvm-svn: 261725
 2016-02-24 08:39:05 +00:00
Igor Breger 0aeda37464 AVX512: VPBROADCASTB/W/D/Q from GPR intrinsics implementation. 
Differential Revision: http://reviews.llvm.org/D16813

llvm-svn: 260024
 2016-02-07 08:30:50 +00:00
Michael Zuckerman 1bd7f993fc [AVX512] Adding PTESTNMB/D/W/Q instruction 
Differential Revision: http://reviews.llvm.org/D16520

llvm-svn: 258688
 2016-01-25 14:43:23 +00:00
Michael Zuckerman 19670d479a [AVX512] Adding PTESTMB/W/D/Q instruction 
Differential Revision: http://reviews.llvm.org/D16519

llvm-svn: 258686
 2016-01-25 13:27:32 +00:00
Elena Demikhovsky 29cde35b43 Added Skylake client to X86 targets and features 
Changes in X86.td:

I set features of Intel processors in incremental form: IVB = SNB + X HSW = IVB + X ..
I added Skylake client processor and defined it's features
FeatureADX was missing on KNL
Added some new features to appropriate processors SMAP, IFMA, PREFETCHWT1, VMFUNC and others

Differential Revision: http://reviews.llvm.org/D16357

llvm-svn: 258659
 2016-01-24 10:41:28 +00:00
Igor Breger 1e5bafbc82 AVX512: VMOVDQU8/16/32/64 (load) intrinsic implementation. 
Differential Revision: http://reviews.llvm.org/D16137

llvm-svn: 258657
 2016-01-24 08:04:33 +00:00
Igor Breger 7a000f5bb2 AVX512: Masked move intrinsic implementation. 
Implemented intrinsic for the follow instructions (reg move) : VMOVDQU8/16, VMOVDQA32/64, VMOVAPS/PD.

Differential Revision: http://reviews.llvm.org/D16316

llvm-svn: 258398
 2016-01-21 14:18:11 +00:00
Igor Breger 239fda676c AVX512: Masked store intrinsic implementation. 
Implemented intrinsic for the follow instructions (store) : VMOVDQU8/16/32/64, VMOVDQA32/64, VMOVAPS/PD, VMOVUPS/PD.

Differential Revision: http://reviews.llvm.org/D16271

llvm-svn: 258047
 2016-01-18 13:52:57 +00:00
Michael Zuckerman ac1b238b0a [AVX512] Adding VPERMW/D/Q VPERMPS/D Intrinsics 
Differential Revision: http://reviews.llvm.org/D16189

llvm-svn: 258008
 2016-01-17 11:33:29 +00:00
Michael Zuckerman 0e31b22487 [AVX512] Adding PMOVSXBD/W/Q , PMOVZSDQ and PMOVZSWD/Q Intrinsics . 
Differential Revision: http://reviews.llvm.org/D16111 

llvm-svn: 257604
 2016-01-13 14:59:19 +00:00
Michael Zuckerman 43cea85db9 [AVX512] Adding PMOVZXBD/W/Q , PMOVZXDQ and PMOVZXWD/Q Intrinsics 
Differential Revision:http://reviews.llvm.org/D16071

llvm-svn: 257601
 2016-01-13 14:25:21 +00:00
Michael Zuckerman 5b1cad87aa [avx512] Fix test avx512bw-intrinsics.ll 
Change the CHECK lablel into AVX512BW 
And fix declare lable of llvm.x86.avx512.mask.psrav32_hi 

llvm-svn: 257071
 2016-01-07 16:25:42 +00:00
Michael Zuckerman 3aca221b31 [AVX512] add PSLLW and PSLLV Intrinsic 
Differential Revision: http://reviews.llvm.org/D15889

llvm-svn: 257070
 2016-01-07 16:02:51 +00:00
Michael Zuckerman 354152d590 [AVX512] add PSRAV Intrinsic 
Differential Revision: http://reviews.llvm.org/D15856

llvm-svn: 257063
 2016-01-07 14:42:20 +00:00
Michael Zuckerman a6df006b50 [AVX512] add PSHUFHW and PSHUFLW Intrinsic 
Differential Revision: http://reviews.llvm.org/D15925

llvm-svn: 257056
 2016-01-07 12:35:43 +00:00
Michael Zuckerman 000fca44a8 [AVX512] add PSRAW Intrinsic 
Differential Revision: http://reviews.llvm.org/D15850

llvm-svn: 256751
 2016-01-04 12:50:36 +00:00
Michael Zuckerman 068bc2f219 [AVX512] add PSRLV Intrinsic 
Differential Revision: http://reviews.llvm.org/D15838

llvm-svn: 256747
 2016-01-04 11:39:06 +00:00
Michael Zuckerman 80821ee77c [AVX512] add PSRLW Intrinsic 
Differential Revision: http://reviews.llvm.org/D15751

llvm-svn: 256558
 2015-12-29 13:04:35 +00:00
Igor Breger 756c289dd8 AVX512: Change VPMOVB2M DAG lowering , use CVT2MASK node instead TRUNCATE. 
Fix TRUNCATE lowering vector to vector i1, use LSB and not MSB.
Implement VPMOVB/W/D/Q2M intrinsic.

Differential Revision: http://reviews.llvm.org/D15675

llvm-svn: 256470
 2015-12-27 13:56:16 +00:00
Igor Breger 268f6f53c5 AVX512: VPMOVM2B/W/D/Q intrinsic implementation. 
Differential Revision: http://reviews.llvm.org//D15747

llvm-svn: 256364
 2015-12-24 07:11:53 +00:00
Igor Breger 3ab6f17530 AVX-512: implement kunpck intrinsics. 
Differential Revision: http://reviews.llvm.org/D14821

llvm-svn: 254908
 2015-12-07 13:25:18 +00:00
Igor Breger 076dfe5c12 AVX512: support AVX512BW Intrinsic in 32bit mode. 
Differential Revision: http://reviews.llvm.org/D15076

llvm-svn: 254873
 2015-12-06 11:35:18 +00:00
Igor Breger ea7932cfb7 AVX512: regenerate avx512bw intrincics tests results. 
Differential Revision: http://reviews.llvm.org/D15069

llvm-svn: 254295
 2015-11-30 10:40:52 +00:00
Cong Hou db6220f84d [X86] Fix several issues related to X86's psadbw instruction. 
This patch fixes the following issues:

1. Fix the return type of X86psadbw: it should not be the same type of inputs.
   For vNi8 inputs the output should be vMi64, where M = N/8.
2. Fix the return type of int_x86_avx512_psad_bw_512 accordingly.
3. Fix the definiton of PSADBW, VPSADBW, and VPSADBWY accordingly.
4. Adjust the return type when building a DAG node of X86ISD::PSADBW type.
5. Update related tests.


Differential revision: http://reviews.llvm.org/D14897

llvm-svn: 254010
 2015-11-24 19:51:26 +00:00
Simon Pilgrim 8483df6e24 [X86][AVX512] Added support for AVX512 UNPCK shuffle decode comments. 
llvm-svn: 253391
 2015-11-17 22:35:45 +00:00
Asaf Badouh d2c3599c5f [X86][AVX512VLBW] add support in byte shift and SAD 
add byte shift left/right
add SAD - compute sum of absolute differences

Differential Revision: http://reviews.llvm.org/D12479

llvm-svn: 246654
 2015-09-02 14:21:54 +00:00
Igor Breger f3ded811b2 AVX512: Implemented encoding and intrinsics for vdbpsadbw 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12491

llvm-svn: 246436
 2015-08-31 13:09:30 +00:00
Igor Breger 2ae0fe3ac3 AVX512: Implemented encoding and intrinsics for vpalignr 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12270

llvm-svn: 246428
 2015-08-31 11:14:02 +00:00
Igor Breger f2460112ad Implemented encoding and intrinsics of the following instructions 
vunpckhps/pd, vunpcklps/pd, 
  vpunpcklbw, vpunpckhbw, vpunpcklwd, vpunpckhwd, vpunpckldq, vpunpckhdq, vpunpcklqdq, vpunpckhqdq
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11509

llvm-svn: 243246
 2015-07-26 14:41:44 +00:00
Igor Breger 074a64e72c AVX-512: Implemented encoding , DAG lowering and intrinsics for Integer Truncate with/without saturation 
Added tests for DAG lowering ,encoding and intrinsic

Differential Revision: http://reviews.llvm.org/D11218

llvm-svn: 243122
 2015-07-24 17:24:15 +00:00
Chandler Carruth fe414353db Revert r242990: "AVX-512: Implemented encoding , DAG lowering and ..." 
This commit broke the build. Numerous build bots broken, and it was
blocking my progress so reverting.

It should be trivial to reproduce -- enable the BPF backend and it
should fail when running llvm-tblgen.

llvm-svn: 242992
 2015-07-23 08:03:44 +00:00
Igor Breger da1b2ea955 AVX-512: Implemented encoding , DAG lowering and intrinsics for Integer Truncate with/without saturation 
Added tests for DAG lowering ,encoding and intrinsic

Differential Revision: http://reviews.llvm.org/D11218

llvm-svn: 242990
 2015-07-23 07:39:21 +00:00
Elena Demikhovsky a26f10ce18 AVX-512: Added intrinsics for VCVT* instructions. 
All SKX forms. All VCVT instructions for float/double/int/long types.

Differential Revision: http://reviews.llvm.org/D11343

llvm-svn: 242877
 2015-07-22 08:56:00 +00:00
Igor Breger f7fd547e27 AVX512 : Implemented VPMADDUBSW and VPMADDWD instruction , 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11351

llvm-svn: 242761
 2015-07-21 07:11:28 +00:00
Asaf Badouh c6f3c82ffc [X86][AVX512] Multiply Packed Unsigned Integers with Round and Scale 
pmulhrsw

review:
http://reviews.llvm.org/D10948

llvm-svn: 241443
 2015-07-06 14:03:40 +00:00
Asaf Badouh 73f26f8ffc [x86][AVX512] add Multiply High Op 
include encoding and intrinsics tests.

review
http://reviews.llvm.org/D10896

llvm-svn: 241406
 2015-07-05 12:23:20 +00:00
Elena Demikhovsky 5e2f8c4231 AVX-512: Added all forms of VPABS instruction 
Added all intrinsics, tests for encoding, tests for intrinsics.

llvm-svn: 240386
 2015-06-23 08:19:46 +00:00
Elena Demikhovsky 55a997437c AVX-512: added VPSHUFB instruction - all SKX forms 
Added intrinsics and encoding tests.

llvm-svn: 240277
 2015-06-22 13:00:42 +00:00
Elena Demikhovsky e77566112c AVX-512: Added intrinsics for VPERMT2W/D/Q/PS/PD and 
VPERMI2W/D/Q/PS/PD instructions.
Added tests.

llvm-svn: 240256
 2015-06-22 06:45:48 +00:00
Asaf Badouh 81f03c30a5 [AVX512] 
add instructions: VPAVGB and VPAVGW


review
http://reviews.llvm.org/D10504

llvm-svn: 240012
 2015-06-18 12:30:53 +00:00
Asaf Badouh 02d126cb9d [AVX512] add integer min/max intrinsics support. 
review:
http://reviews.llvm.org/D10439

llvm-svn: 239806
 2015-06-16 08:39:27 +00:00
Elena Demikhovsky 3822af0715 AVX-512: Changed CC parameter in "cmp" intrinsic 
from i8 to i32 according to the Intel Spec

by Igor Breger (igor.breger@intel.com)

llvm-svn: 236979
 2015-05-11 09:03:14 +00:00
Elena Demikhovsky 52266388f8 AVX-512: added integer "add" and "sub" instructions with saturation for SKX 
with intrinsics and tests

by Asaf Badouh (asaf.badouh@intel.com)

llvm-svn: 236418
 2015-05-04 12:35:55 +00:00
Elena Demikhovsky 2557a22be7 AVX-512: Added VPACK* instructions forms for KNL and SKX 
and their intrinsics
by Asaf Badouh (asaf.badouh@intel.com)

llvm-svn: 236414
 2015-05-04 09:14:02 +00:00
Craig Topper 29f2e95185 [X86] Use i8 immediate for comparison type on AVX512 packed integer instructions. This matches floating point equivalents. Includes autoupgrade support to convert old code. 
llvm-svn: 227063
 2015-01-25 23:26:02 +00:00
Elena Demikhovsky 3121449f0b AVX-512: BLENDM - fixed encoding of the broadcast version 
Added more intrinsics and encoding tests.

llvm-svn: 224760
 2014-12-23 09:36:28 +00:00
Robert Khasanov b51bb22611 [AVX512] Added intrinsics for 128-, 256- and 512-bit versions of VPCMP/VPCMPU{BWDQ} 
Added CMP_MASK_CC intrinsic type.
Added tests for intrinsics.

Patch by Sergey Lisitsyn <sergey.lisitsyn@intel.com>

llvm-svn: 219316
 2014-10-08 15:49:26 +00:00
Robert Khasanov 28a7df0b5f [AVX512] Added intrinsics for 128-, 256- and 512-bit versions of VCMPGT{BWDQ}. 
Patch by Sergey Lisitsyn <sergey.lisitsyn@intel.com>

llvm-svn: 218670
 2014-09-30 12:15:52 +00:00
Robert Khasanov b25e562d14 [AVX512] Added intrinsics for VPCMPEQB and VPCMPEQW. 
Added new operand type for intrinsics (IIT_V64)

llvm-svn: 218668
 2014-09-30 11:32:22 +00:00