ed85e12da6
We are not using DBG_STOPPOINT anymore.
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llvm-svn: 89536
2009-11-21 02:46:55 +00:00
bdb43a9d99
Remat VLDRD from constpool. Clean up some instruction property specifications.
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llvm-svn: 89478
2009-11-20 19:57:15 +00:00
6c3b71195a
The verify() call of CPEIsInRange() isn't right for the assertion check of
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constant pool ranges, as CPEIsInRange() makes conservative assumptions about
the potential alignment changes from branch adjustments. The verification,
on the other hand, runs after those branch adjustments are made, so the
effects on alignment are known and already taken into account. The sanity
check in verify should check the range directly instead.
llvm-svn: 89473
2009-11-20 19:37:38 +00:00
fc81352e3f
Remove verifySizes() since it's not adding much value.
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llvm-svn: 89443
2009-11-20 02:32:06 +00:00
bbd50b0f78
Also CSE non-pic load from constant pools.
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llvm-svn: 89440
2009-11-20 02:10:27 +00:00
81a2851bcb
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all.
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llvm-svn: 89423
2009-11-20 00:54:03 +00:00
a6380af658
Update comment to reflect instruction.
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llvm-svn: 89414
2009-11-20 00:21:55 +00:00
b73918c42d
When placing constant islands and adjusting for alignment padding, inline
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assembly can confuse things utterly, as it's assumed that instructions in
inline assembly are 4 bytes wide. For Thumb mode, that's often not true,
so the calculations for when alignment padding will be present get thrown off,
ultimately leading to out of range constant pool entry references. Making
more conservative assumptions that padding may be necessary when inline asm
is present avoids this situation.
llvm-svn: 89403
2009-11-19 23:10:28 +00:00
b6c7704a8d
Refactor cmov selection code out to a separate function. No functionality change.
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llvm-svn: 89396
2009-11-19 21:45:22 +00:00
b3b8209d77
Added NLdStLN which is similar to NLdSt with the exception that op7_4 is not
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fully specified at this level. Subclasses of NLdStLN can specify selective
bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside
ARMInstrNEON.td.
llvm-svn: 89377
2009-11-19 19:20:17 +00:00
36a5bf82bf
fix typo
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llvm-svn: 89369
2009-11-19 18:23:19 +00:00
82adca8373
80 col violation.
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llvm-svn: 89337
2009-11-19 08:16:50 +00:00
b18525937c
More consistent thumb1 asm printing.
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llvm-svn: 89328
2009-11-19 06:57:41 +00:00
2a6c92fcb6
Shrink ldr / str [sp, imm0-1024] to 16-bit instructions.
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llvm-svn: 89326
2009-11-19 06:32:27 +00:00
547abae38d
Eliminate more * 4 in Thumb1 asm printing for consistency sake.
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llvm-svn: 89325
2009-11-19 06:31:26 +00:00
1fd5fdaa7b
Add ARMv6 itineraries.
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llvm-svn: 89218
2009-11-18 18:39:57 +00:00
9dea05d724
Fix a few places that were missed when we converted to unified syntax.
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llvm-svn: 89214
2009-11-18 18:10:35 +00:00
290e9a47a9
Add a target hook to allow changing the tail duplication limit based on the
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contents of the block to be duplicated. Use this for ARM Cortex A8/9 to
be more aggressive tail duplicating indirect branches, since it makes it
much more likely that they will be predicted in the branch target buffer.
Testcase coming soon.
llvm-svn: 89187
2009-11-18 03:34:27 +00:00
cdde77c6a3
Enable arm jumpt table adjustment.
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llvm-svn: 89143
2009-11-17 21:24:11 +00:00
f24804413d
Both Darwin as and GNU as violate ARM docs wrt printing of addrmode6
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alignment imm (in the same way). Fix asmprinting for non-darwin platforms.
llvm-svn: 89137
2009-11-17 20:04:59 +00:00
14b25eb87b
Set Inst{15-12} (Rd/Rt) to 0b1111 (PC) for BR_JTadd, BR_JTr, and BR_JTm to
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distinguish between them and the more generic instructions (add, mov, and ldr).
llvm-svn: 89108
2009-11-17 17:17:50 +00:00
af1ad30a23
When moving a block for table jumps, make sure the prior block terminator
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is analyzable so it can be updated. If it's not, be safe and don't move the
block.
llvm-svn: 89022
2009-11-17 01:21:04 +00:00
18183b6d8e
Set Rm bits of BX_RET to 0b1110 (R14); and set condition code bits of BRIND to
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0b1110 (ALways). This is so that the disassembler decoder can distinguish among
BX_RET, BRIND, and BXr9.
llvm-svn: 89000
2009-11-16 23:57:56 +00:00
56ee15c162
Make the pass class name more explicit.
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llvm-svn: 88964
2009-11-16 21:13:22 +00:00
544b15cbc3
make pass name a bit more clear
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llvm-svn: 88961
2009-11-16 21:03:58 +00:00
9785e5914f
Simplify thumb2 jump table adjustments. Remove unnecessary calculation and
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usage of block sizes and offsets.
llvm-svn: 88935
2009-11-16 18:58:52 +00:00
87b0f0d95c
clarify comment
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llvm-svn: 88933
2009-11-16 18:55:47 +00:00
9c148c2163
back off for a bit. tracking down weirdness
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llvm-svn: 88919
2009-11-16 17:17:48 +00:00
47d5e333ff
Analyze has to be before checking the condition, obviously. Properly construct an iterator for prior.
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llvm-svn: 88917
2009-11-16 17:10:56 +00:00
01c1cae34d
Detect need for autoalignment of the stack earlier to catch spills more
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conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling
llvm-svn: 88874
2009-11-15 21:45:34 +00:00
74ae3e5b0e
set the def of the VLD1q64 properly
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llvm-svn: 88873
2009-11-15 21:05:07 +00:00
e07594df45
cleanup.
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llvm-svn: 88812
2009-11-14 21:33:37 +00:00
43d2108546
Cleanup flow, and only update the jump table we're analyzing when replacing a destination MBB.
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llvm-svn: 88805
2009-11-14 20:10:18 +00:00
6ad7da96fe
- Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.
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- If destination is a physical register and it has a subreg index, use the
sub-register instead.
This fixes PR5423.
llvm-svn: 88745
2009-11-14 02:55:43 +00:00
66401c90da
When expanding t2STRDi8 r, r to two stores, add kill markers correctly.
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llvm-svn: 88734
2009-11-14 01:50:00 +00:00
659c1a9d78
Move DebugInfo checks into EmitComments and remove them from
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target-specific AsmPrinters. Not all comments need DebugInfo.
Re-enable the line numbers comment test.
llvm-svn: 88697
2009-11-13 21:34:57 +00:00
b9fe5d5d02
Allow target to specify regclass for which antideps will only be broken along the critical path.
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llvm-svn: 88682
2009-11-13 19:52:48 +00:00
46a524c3e8
Block renumbering
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llvm-svn: 87056
2009-11-13 01:19:24 +00:00
969910b3e8
use lower case for readability
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llvm-svn: 87054
2009-11-13 01:17:22 +00:00
be851acfb0
Make the MachineFunction argument of getFrameRegister const.
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This also fixes a build error.
llvm-svn: 87027
2009-11-12 21:00:03 +00:00
1fbe054450
Add a bool flag to StackObjects telling whether they reference spill
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slots. The AsmPrinter will use this information to determine whether to
print a spill/reload comment.
Remove default argument values. It's too easy to pass a wrong argument
value when multiple arguments have default values. Make everything
explicit to trap bugs early.
Update all targets to adhere to the new interfaces..
llvm-svn: 87022
2009-11-12 20:49:22 +00:00
5d57714e6c
Update TB[BH] layout optimization. Add support for moving the target block
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to directly follow the jump table. Move the layout changes to prior to any
constant island handling.
llvm-svn: 86999
2009-11-12 17:25:07 +00:00
e129dd311e
Use table to separate opcode from operands.
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llvm-svn: 86965
2009-11-12 07:16:34 +00:00
15b80e4a9f
isLegalICmpImmediate should take a signed integer; code clean up.
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llvm-svn: 86964
2009-11-12 07:13:11 +00:00
6385ea7c4e
Revert 86857. It's causing consumer-typeset to fail, and there's a better way to do it forthcoming anyway.
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llvm-svn: 86945
2009-11-12 03:28:35 +00:00
3d3c24a82c
Add TargetLowering::isLegalICmpImmediate. It tells LSR what immediate can be folded into target icmp instructions.
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llvm-svn: 86858
2009-11-11 19:05:52 +00:00
d576d66d91
Do jump table adjustment before constant island allocation
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llvm-svn: 86857
2009-11-11 19:04:24 +00:00
8d92ec45c7
The TBB and TBH instructions for Thumb2 are really handy for jump tables, but
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can only branch forward. To best take advantage of them, we'd like to adjust
the basic blocks around a bit when reasonable. This patch puts basics in place
to do that, with a super-simple algorithm for backwards jump table targets that
creates a new branch after the jump table which branches backwards. Real
heuristics for reordering blocks or other modifications rather than inserting
branches will follow.
llvm-svn: 86791
2009-11-11 02:47:19 +00:00
e034867587
Change Thumb1 address mode printing, instead of
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[r0, #2 * 4]
Now
[r0, #8 ]
This makes Thumb2 assembly more uniform and frankly the scale doesn't add much.
llvm-svn: 86707
2009-11-10 19:48:13 +00:00
e6548f4106
Add a comment.
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llvm-svn: 86706
2009-11-10 19:44:56 +00:00
Devang Patel