33ad850d93
Add indirect tail call (function pointer) examples.
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llvm-svn: 56127
2008-09-11 22:24:28 +00:00
dd45bc25ac
When tailcallopt is enabled all fastcc calls must have an aligned argument stack size. Add a test case.
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llvm-svn: 56119
2008-09-11 20:28:43 +00:00
5456a37280
Fix PR2748. Avoid coalescing physical register with virtual register which would create illegal extract_subreg. e.g.
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vr1024 = extract_subreg vr1025, 1
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vr1024 = mov8rr AH
If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH.
llvm-svn: 56118
2008-09-11 20:07:10 +00:00
4c9fbbb511
Fix PR2783 - coalescer bug. Missing a TargetRegisterInfo::isVirtualRegister check.
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llvm-svn: 56112
2008-09-11 18:40:32 +00:00
b401449ceb
Propagate subreg index when promoting a load to a copy.
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llvm-svn: 56085
2008-09-11 01:02:12 +00:00
710c3cf36a
Fix a fastcc + sret bug. If fastcc and sret, callee doesn't need to pop the hidden struct ptr; Re-enable fastcc.
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llvm-svn: 56061
2008-09-10 18:25:29 +00:00
f4e5de4583
Legalizer was missing code that expand fpow to a libcall.
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llvm-svn: 56028
2008-09-09 23:02:14 +00:00
53b728c27c
Fix PR2757. Ignore liveinterval register allocation preference if the preference register is not in the right register class. This can happen due to sub-register coalescing.
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llvm-svn: 56006
2008-09-09 20:22:01 +00:00
1e97901388
Fix a constant lowering bug. Now we can do load and store instructions with funky getelementptr embedded in the address operand.
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llvm-svn: 55975
2008-09-09 01:26:59 +00:00
ab4928a6e5
Reapply 55902: Add test for checking proper lowering of eh_return & unwind init intrinsics on 32bit x86 targets
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llvm-svn: 55960
2008-09-08 21:14:36 +00:00
35883b7eec
Reapply 55903: Testcase for 64-bit lowering of eh_return & unwind_init
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llvm-svn: 55959
2008-09-08 21:14:19 +00:00
554e6898ff
Add a target triple; apparently LLVM doesn't use 64-bit
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data directives on darwin.
llvm-svn: 55941
2008-09-08 20:16:18 +00:00
6da384d980
Remove these testcases associated with changes between r 55898 and r 55909.
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llvm-svn: 55931
2008-09-08 18:00:39 +00:00
99b83712f3
Reverting r55898 to r55909. One of these patches was causing an ICE during the full bootstrap on Darwin:
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/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_negdi2 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_negdi2_s.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) &&
TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical
register live information"), function runOnMachineFunction, file
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp,
line 311.
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_lshrdi3 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_lshrdi3_s.o
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter > for instructions.
{standard input}:unknown:Undefined local symbol LBB21_11
{standard input}:unknown:Undefined local symbol LBB21_12
{standard input}:unknown:Undefined local symbol LBB21_13
{standard input}:unknown:Undefined local symbol LBB21_8
llvm-svn: 55928
2008-09-08 17:59:12 +00:00
d172048b59
Handle calls which produce i1 results: promote to i8 but and it with 1 to get the low bit.
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llvm-svn: 55925
2008-09-08 17:15:42 +00:00
f9b2054df1
Add AsmPrinter support for i128 and larger static initializer data.
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llvm-svn: 55919
2008-09-08 16:40:13 +00:00
f5e48008a4
Testcase for 64-bit lowering of eh_return & unwind_init
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llvm-svn: 55903
2008-09-08 14:23:16 +00:00
f0d1a0ccf0
Add test for checking proper lowering of eh_return & unwind init intrinsics on 32bit x86 targets
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llvm-svn: 55902
2008-09-08 14:22:57 +00:00
d3ca8be4a9
Add testcase from bug 2770.
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llvm-svn: 55897
2008-09-08 11:17:54 +00:00
ca14c07175
Correctly handle physical register inputs. They are not explicit input operands in the resulting machine instrs.
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llvm-svn: 55893
2008-09-08 08:39:33 +00:00
b928669409
Handle x86 truncate to i8 with target hook for now.
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llvm-svn: 55877
2008-09-07 08:47:42 +00:00
a9c52c8219
Fix for PR2687: Add patterns to match sint_to_fp and fp_to_sint for <2 x
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i32>. This is a little messy, but it works.
We should really get rid of the intrinsics, though, since they map
perfectly well to standard LLVM instructions.
llvm-svn: 55864
2008-09-05 23:07:03 +00:00
d4e01dce74
Fix test.
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llvm-svn: 55849
2008-09-05 20:04:37 +00:00
4f0d21592a
If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls.
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llvm-svn: 55840
2008-09-05 17:24:07 +00:00
6c94b99c62
For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries.
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llvm-svn: 55807
2008-09-04 22:59:58 +00:00
b8c7ba228f
Fix the ordering of operands to the store (inverted relative to LLVM IR), and fix the testcase.
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llvm-svn: 55777
2008-09-04 16:48:33 +00:00
4f948bd87a
Add a first attempt at implementing stores for X86 fast isel using target hooks.
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Dan or Evan, please review.
llvm-svn: 55764
2008-09-04 07:08:58 +00:00
8d8f47d50b
Load from GV stub should be locally CSE'd.
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llvm-svn: 55763
2008-09-04 06:18:33 +00:00
3152edf474
Remove code that pad number of bytes to pop for X86_FastCall CC. The code doesn't do the "aligning" for Cygwin, Mingw, and Windows. But aligning it on Darwin and Linux breaks gcc compatibility. That ruled out all the platforms we support!
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llvm-svn: 55756
2008-09-04 01:04:15 +00:00
a41ee2974b
Add X86 target hook to implement load (even from GlobalAddress).
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llvm-svn: 55693
2008-09-03 06:44:39 +00:00
fdbe925974
Turn this legalize types test on.
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llvm-svn: 55605
2008-09-01 12:00:55 +00:00
aebd2662d3
Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTR
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instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.
llvm-svn: 55582
2008-08-31 02:59:23 +00:00
91bf1e0dc5
CellSPU doesn't appear to support fully the "ISD::ROTR" operation. The DAG
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combiner can now generate ROTR if the backend says that it can handle it. Cell
SPU says this, but gets an error from code gen saying that it can't select
ROTR. I'm xfailing this test until this can be fixed.
llvm-svn: 55579
2008-08-31 02:32:12 +00:00
a3771d5bd9
Re-apply 55467 with fix. If copy is being replaced by remat'ed def, transfer the implicit defs onto the remat'ed instruction.
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llvm-svn: 55564
2008-08-30 09:09:33 +00:00
cfb7f3abdf
Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).
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llvm-svn: 55558
2008-08-30 02:03:58 +00:00
35c2abf4c2
Testcases for ppc atomics.
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llvm-svn: 55556
2008-08-30 00:54:31 +00:00
3fddc7e906
Swap fp comparison operands and change predicate to allow load folding (safely this time).
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llvm-svn: 55553
2008-08-29 23:22:12 +00:00
0b82607fa1
xfail this.
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llvm-svn: 55550
2008-08-29 22:59:13 +00:00
9fc9d2ec3b
allow this to pass.
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llvm-svn: 55540
2008-08-29 17:18:26 +00:00
960b17a3c2
Swap fp comparison operands and change predicate to allow load folding.
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llvm-svn: 55521
2008-08-28 23:48:31 +00:00
1e137300bd
In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN
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llvm-svn: 55499
2008-08-28 21:04:05 +00:00
f27e33baa7
Optimize DAGCombiner's worklist processing. Previously it started
...
its work by putting all nodes in the worklist, requiring a big
dynamic allocation. Now, DAGCombiner just iterates over the AllNodes
list and maintains a worklist for nodes that are newly created or
need to be revisited. This allows the worklist to stay small in most
cases, so it can be a SmallVector.
This has the side effect of making DAGCombine not miss a folding
opportunity in alloca-align-rounding.ll.
llvm-svn: 55498
2008-08-28 21:01:56 +00:00
04cf2e4540
Revert r55467; it causes regressions in UnitTests/Vector/divides,
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Benchmarks/sim/sim, and others on x86-64.
llvm-svn: 55475
2008-08-28 17:22:54 +00:00
6975602024
If a copy isn't coalesced, but its src is defined by trivial computation. Re-materialize the src to replace the copy.
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llvm-svn: 55467
2008-08-28 07:53:51 +00:00
897b2380d8
This test crashes on non-x86 host; make SSE explicit.
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Feel free to fix a better way!
llvm-svn: 55456
2008-08-28 01:51:09 +00:00
5ca269e684
Basic FastISel support for floating-point constants.
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llvm-svn: 55401
2008-08-27 01:09:54 +00:00
09f8cef571
If an xmm register is referenced explicitly in an inline asm, make sure to
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assign it to a version of the xmm register with the regclass that matches its
type. This fixes PR2715, a bug handling some crazy xpcom case in mozilla.
llvm-svn: 55358
2008-08-26 06:19:02 +00:00
f00f1e50b5
Try approach to moving call address load inside of callseq_start. Now it's done during the preprocess of x86 isel. callseq_start's chain is changed to load's chain node; while load's chain is the last of callseq_start or the loads or copytoreg nodes inserted to move arguments to the right spot.
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llvm-svn: 55338
2008-08-25 21:27:18 +00:00
32635dbfb2
Add support for fast isel of (integer) immediate materialization pattens, and use them to support
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bitcast of constants in fast isel.
llvm-svn: 55325
2008-08-25 20:20:32 +00:00
17d5be2d0a
Adjust grep's for new code sequence.
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llvm-svn: 55320
2008-08-25 18:53:58 +00:00
Arnold Schwaighofer