676c16d088
R600: Add IsExport bit to TableGen instruction definitions
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Tested-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 188516
2013-08-16 01:11:51 +00:00
ac00f9df79
R600: Change the RAT instruction assembly names so they match the docs
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Tested-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 188515
2013-08-16 01:11:46 +00:00
0344cdfe39
R600: Add 64-bit float load/store support
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* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions
Tom Stellard:
- Mark vec2 operations as expand. The addition of a vec2 register
class made them all legal.
Patch by: Dmitry Cherkassov
Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
llvm-svn: 187582
2013-08-01 15:23:42 +00:00
0c5ed2b437
R600: Remove predicated_break inst
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We were using two instructions for similar purpose : break and
predicated break. Only predicated_break was emitted and it was
lowered at R600ControlFlowFinalizer to JUMP;CF_BREAK;POP.
This commit simplify the situation by making AMDILCFGStructurizer
emit IF_PREDICATE;BREAK;ENDIF; instead of predicated_break (which
is now removed).
There is no functionality change.
llvm-svn: 187510
2013-07-31 19:31:14 +00:00
8b8a7b5514
R600: Don't emit empty then clause and use alu_pop_after
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llvm-svn: 186725
2013-07-19 21:45:15 +00:00
0afd0ab749
Make some arrays 'static const'
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llvm-svn: 186307
2013-07-15 06:39:13 +00:00
ce499744b3
R600: Do not predicated basic block with multiple alu clause
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Test is not included as it is several 1000 lines long.
To test this functionnality, a test case must generate at least 2 ALU clauses,
where an ALU clause is ~110 instructions long.
NOTE: This is a candidate for the stable branch.
llvm-svn: 185943
2013-07-09 15:03:33 +00:00
6aa0d5578d
R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on Cayman
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We were using RAT_INST_STORE_RAW, which seemed to work, but the docs
say this instruction doesn't exist for Cayman, so it's probably safer
to use a documented instruction instead.
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184015
2013-06-14 22:12:24 +00:00
4d143328df
R600: Anti dep better handled in tex clause
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llvm-svn: 183592
2013-06-07 23:30:26 +00:00
a6c6e1bfc2
R600: Rework subtarget info and remove AMDILDevice classes
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This should simplify the subtarget definitions and make it easier to
add new ones.
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183566
2013-06-07 20:37:48 +00:00
37e9adb091
Don't cache the instruction and register info from the TargetMachine, because
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the internals of TargetMachine could change.
No functionality change intended.
llvm-svn: 183561
2013-06-07 20:28:55 +00:00
eabf83e0a2
R600: CALL_FS consumes a stack size entry
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llvm-svn: 183108
2013-06-03 15:44:42 +00:00
1b086cbcb8
R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg
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Patch by: Vincent Lejeune
https://bugs.freedesktop.org/show_bug.cgi?id=64877
NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 182600
2013-05-23 18:26:42 +00:00
d78bb468bd
Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
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llvm-svn: 182594
2013-05-23 17:10:37 +00:00
15f193a1a3
Setting the default value (fixes CRT assertions about uninitialized variable use when doing debug MSVC builds), and fixing coding style.
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llvm-svn: 182585
2013-05-23 14:55:00 +00:00
0fca91d52e
R600: Some factorization
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llvm-svn: 182123
2013-05-17 16:50:02 +00:00
f9f4e1e7db
R600: Factorize Fetch size limit inside AMDGPUSubTarget
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llvm-svn: 182122
2013-05-17 16:49:55 +00:00
ddd43383ef
R600: Signed literals are 64bits wide
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llvm-svn: 180960
2013-05-02 21:53:03 +00:00
3abdbf1cad
R600: use native for alu
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llvm-svn: 180761
2013-04-30 00:14:38 +00:00
7c395f77de
R600: Take inner dependency into tex/vtx clauses
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llvm-svn: 180757
2013-04-30 00:14:00 +00:00
3f1d136b02
R600: Turn TEX/VTX into native instructions
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llvm-svn: 180756
2013-04-30 00:13:53 +00:00
c299164284
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions
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v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache
llvm-svn: 180755
2013-04-30 00:13:39 +00:00
119ad03c67
R600: Use correct CF_END instruction on Northern Island GPUs
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llvm-svn: 180735
2013-04-29 22:23:58 +00:00
117f075f6e
R600: Use .AMDGPU.config section to emit stacksize
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llvm-svn: 180124
2013-04-23 17:34:12 +00:00
b6bfe85a07
R600: Add CF_END
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llvm-svn: 180123
2013-04-23 17:34:00 +00:00
3ee2b1e26f
R600ControlFlowFinalizer.cpp: Fix a warning. [-Wunused-variable]
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llvm-svn: 179263
2013-04-11 04:16:27 +00:00
3b0853be56
Whitespace.
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llvm-svn: 179262
2013-04-11 04:16:22 +00:00
04d9aa4822
R600: Add VTX_READ_* and RAT_WRITE_CACHELESS_* when computing cf addr
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llvm-svn: 179174
2013-04-10 13:29:20 +00:00
5f11dd390a
R600: Control Flow support for pre EG gen
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llvm-svn: 179020
2013-04-08 13:05:49 +00:00
8e377fdba6
R600: Fix wrong address when substituting ENDIF
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llvm-svn: 178762
2013-04-04 14:00:03 +00:00
c44fa99719
R600: Take export into account when computing cf address
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llvm-svn: 178761
2013-04-04 13:59:59 +00:00
b6d6c0d458
R600: Simplify data structure and add DEBUG to R600ControlFlowFinalizer
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llvm-svn: 178665
2013-04-03 16:24:09 +00:00
9931298b30
R600: Consider KILLGT as an ALU instruction
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Mesa does not override llvm behavior wrt KILLGT anymore so llvm
has to handle KILLGT on its own.
llvm-svn: 178664
2013-04-03 16:24:04 +00:00
bfaa63a6db
R600: Add support for native control flow
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llvm-svn: 178505
2013-04-01 21:48:05 +00:00
Tom Stellard