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5 Commits

Author SHA1 Message Date
Tom Stellard d3ee8c103a R600: Add support for i16 and i8 global stores 
Tested-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 188519
 2013-08-16 01:12:06 +00:00
Owen Anderson 616852848a Create an FPOW SDNode opcode def in the target independent .td file rather than in a specific backend. 
llvm-svn: 182450
 2013-05-22 06:36:09 +00:00
Tom Stellard 5643c4ac72 R600: Swap the legality of rotl and rotr 
The hardware supports rotr and not rotl.

llvm-svn: 182285
 2013-05-20 15:02:19 +00:00
Tom Stellard f3b2a1e8b3 R600: Support for indirect addressing v4 
Only implemented for R600 so far.  SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.

At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.

v2:
  - Add support for i8 zext load from stack.
  - Coding style fixes

v3:
  - Don't reserve registers for indirect addressing when it isn't
    being used.
  - Fix bug caused by LLVM limiting the number of SubRegIndex
    declarations.

v4:
  - Fix 64-bit defines

llvm-svn: 174525
 2013-02-06 17:32:29 +00:00
Tom Stellard 75aadc2813 Add R600 backend 
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX

llvm-svn: 169915
 2012-12-11 21:25:42 +00:00