Commit Graph

7640 Commits

Author SHA1 Message Date
River Riddle 60c735d409 [mlir-opt] Don't enable `printOpOnDiagnostic` if it was explicitly disabled.
We are currently explicitly setting the flag solely based on the value of `-verify`, which ends up ignoring the situation where the user explicitly disabled this option from the command line.

Differential Revision: https://reviews.llvm.org/D102952
2021-05-24 15:56:48 -07:00
thomasraoux dae9038611 [mlir] Lower sm version for TensorCore intergration tests
Those tests only require sm70, this allows to run those integration
tests on more hardware.

Differential Revision: https://reviews.llvm.org/D103049
2021-05-24 14:45:24 -07:00
Chris Lattner 64716b2c39 [GreedyPatternRewriter] Introduce a config object that allows controlling internal parameters. NFC.
This exposes the iterations and top-down processing as flags, and also
allows controlling whether region simplification is desirable for a client.
This allows deleting some duplicated entrypoints to
applyPatternsAndFoldGreedily.

This also deletes the Constant Preprocessing pass, which isn't worth it
on balance.

All defaults are all kept the same, so no one should see a behavior change.

Differential Revision: https://reviews.llvm.org/D102988
2021-05-24 12:40:40 -07:00
George d3e6c2ddc3 Surface clone APIs in CAPI
Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D102987
2021-05-24 11:53:00 -07:00
Stella Laurenzo 96aa0a4115 Enable MLIR Python bindings for TOSA.
Differential Revision: https://reviews.llvm.org/D103035
2021-05-24 18:04:50 +00:00
Markus Böck d35bd98651 [mlir][doc] Fix links and references in top level docs directory
This is the fourth and final patch in a series of patches fixing markdown links and references inside the mlir documentation. This patch combined with the other three should fix almost every broken link on mlir.llvm.org as far as I can tell.

This patch in particular addresses all Markdown files in the top level docs directory.

Differential Revision: https://reviews.llvm.org/D103032
2021-05-24 18:43:00 +02:00
Suraj Sudhir 1ceff40df0 [mlir][tosa] Align tensor rank specifications with current spec
Deconstrains several TOSA operators to align with the current TOSA spec, including all the elementwise ops.
Note: some more ops are under consideration for further cleanup; they will follow once the spec has been updated.

Reviewed By: stellaraccident

Differential Revision: https://reviews.llvm.org/D102958
2021-05-24 16:03:42 +00:00
Uday Bondhugula 587408c199 [MLIR] Drop old cmake var names
Drop old cmake variable names that were kept around so that zorg
buildbot could be migrated, which has now happened (D102977). D102976
had fixed the inconsistent names.

Differential Revision: https://reviews.llvm.org/D102997
2021-05-24 15:30:01 +05:30
John Demme c65bb760df [MLIR] [Python] Add Operation.parent
Attribute to get the parent operation of an operation.

Reviewed By: stellaraccident

Differential Revision: https://reviews.llvm.org/D102981
2021-05-23 20:52:43 -07:00
Uday Bondhugula 9c21ddb70a [MLIR] Make MLIR cmake variable names consistent
Fix inconsistent MLIR CMake variable names. Consistently name them as
MLIR_ENABLE_<feature>.

Eg: MLIR_CUDA_RUNNER_ENABLED -> MLIR_ENABLE_CUDA_RUNNER

MLIR follows (or has mostly followed) the convention of naming
cmake enabling variables in the from MLIR_ENABLE_... etc. Using a
convention here is easy and also important for convenience. A counter
pattern was started with variables named MLIR_..._ENABLED. This led to a
sequence of related counter patterns: MLIR_CUDA_RUNNER_ENABLED,
MLIR_ROCM_RUNNER_ENABLED, etc.. From a naming standpoint, the imperative
form is more meaningful. Additional discussion at:
https://llvm.discourse.group/t/mlir-cmake-enable-variable-naming-convention/3520

Switch all inconsistent ones to the ENABLE form. Keep the couple of old
mappings needed until buildbot config is migrated.

Differential Revision: https://reviews.llvm.org/D102976
2021-05-24 08:43:10 +05:30
Haruki Imai 000a05fd1a [mlir] Normalize dynamic memrefs with a map of tiled-layout.
Steps for normalizing dynamic memrefs for tiled layout map
1. Check if original map is tiled layout. Only tiled layout is supported.
2. Create normalized memrefType. Dimensions that include dynamic dimensions
   in the map output will be dynamic dimensions.
3. Create new maps to calculate each dimension size of new memref.
   In tiled layout, the dimension size can be calculated by replacing
    "floordiv <tile size>" with "ceildiv <tile size>" and
    "mod <tile size>" with "<tile size>".
4. Create AffineApplyOp to apply the new maps. The output of AffineApplyOp is
   dynamicSizes for new AllocOp.
5. Add the new dynamic sizes in new AllocOp.

This patch also set MemRefsNormalizable trant in CastOp and DimOp since
they used with dynamic memrefs.

Reviewed By: bondhugula

Differential Revision: https://reviews.llvm.org/D97655
2021-05-24 08:39:36 +05:30
Philipp Krones c2f819af73 [MC] Refactor MCObjectFileInfo initialization and allow targets to create MCObjectFileInfo
This makes it possible for targets to define their own MCObjectFileInfo.
This MCObjectFileInfo is then used to determine things like section alignment.

This is a follow up to D101462 and prepares for the RISCV backend defining the
text section alignment depending on the enabled extensions.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D101921
2021-05-23 14:15:23 -07:00
Chris Lattner 81467f500f [IR] Add a Location to BlockArgument
This adds the ability to specify a location when creating BlockArguments.
Notably Value::getLoc() will return this correctly, which makes diagnostics
more precise (e.g. the example in test-legalize-type-conversion.mlir).

This is currently optional to avoid breaking any existing code - if
absent, the BlockArgument defaults to using the location of its enclosing
operation (preserving existing behavior).

The bulk of this change is plumbing location tracking through the parser
and printer to make sure it can round trip (in -mlir-print-debuginfo
mode).  This is complete for generic operations, but requires manual
adoption for custom ops.

I added support for function-like ops to round trip their argument
locations - they print correctly, but when parsing the locations are
dropped on the floor.  I intend to fix this, but it will require more
invasive plumbing through "function_like_impl" stuff so I think it
best to split it out to its own patch.

This is a reapply of the patch here: https://reviews.llvm.org/D102567
with an additional change: we now never defer block argument locations,
guaranteeing that we can round trip correctly.

This isn't required in all cases, but allows us to hill climb here and
works around unrelated bugs like https://bugs.llvm.org/show_bug.cgi?id=50451

Differential Revision: https://reviews.llvm.org/D102991
2021-05-23 14:10:00 -07:00
Markus Böck 9a6eb4968e [mlir][doc] Fix links and indentation of mlir::ModuleOp description
All lines after the first are currently indented by one char further to the left than the first line. This leads to the first character of each sentence being cut from the resulting Markdown file after compilation. The text also contains 3 references to sections of other markdown files. One was missing the file, while the other two had outdated files, leading to 404 errors in the documentation.

Differential Revision: https://reviews.llvm.org/D102983
2021-05-23 20:01:54 +02:00
Butygin 0dd36f81b9 [mlir][linalg][nfc] Fix signed/unsigned comparison warning in header
Differential Revision: https://reviews.llvm.org/D102968
2021-05-22 17:18:01 +03:00
Butygin 4184018253 [mlir][SCF] Canonicalize nested ParallelOp's
Differential Revision: https://reviews.llvm.org/D102799
2021-05-22 14:00:00 +03:00
Navdeep Kumar e552fa28da [MLIR][GPU] Add CUDA Tensor core WMMA test
Add a test case to test the complete execution of WMMA ops on a Nvidia
GPU with tensor cores. These tests are enabled under
MLIR_RUN_CUDA_TENSOR_CORE_TESTS.

Reviewed By: bondhugula

Differential Revision: https://reviews.llvm.org/D95334
2021-05-22 16:19:36 +05:30
Uday Bondhugula 3597b2c37d [MLIR] Drop stale reference to mlir-edsc-builder-api-test
Drop stale reference to mlir-edsc-builder-api-test.

Differential Revision: https://reviews.llvm.org/D102967
2021-05-22 16:11:29 +05:30
Butygin 9afbca746b [mlir] ConvertStandardToLLVM: make AllocLikeOpLowering public
It is useful for someone who wants to implement custom AllocOp LLVM lowering

Differential Revision: https://reviews.llvm.org/D102932
2021-05-22 12:57:45 +03:00
Andrew Young ab3cd2601b
[mlir][docs] Add memref and sparse_tensor to Passes.md
These pass documents belong on the main pass page, and not generated as
top level pages.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D102947
2021-05-21 15:23:39 -07:00
Aart Bik c194b49c9c [mlir][sparse] add full dimension ordering support
This revision completes the "dimension ordering" feature
of sparse tensor types that enables the programmer to
define a preferred order on dimension access (other than
the default left-to-right order). This enables e.g. selection
of column-major over row-major storage for sparse matrices,
but generalized to any rank, as in:

dimOrdering = affine_map<(i,j,k,l,m,n,o,p) -> (p,o,j,k,i,l,m,n)>

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D102856
2021-05-21 12:35:13 -07:00
Marius Brehler b3127c94dd [mlir][docs] Fix links to index and integer types
Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D102922
2021-05-21 18:21:29 +02:00
Alexander Belyaev 335fa18028 [mlir] NFC: Expose tiled_loop->scf pattern.
Differential Revision: https://reviews.llvm.org/D102921
2021-05-21 18:19:00 +02:00
Alexander Belyaev 9ecc8178d7 [mlir] Add support for fusion into TiledLoopOp.
Differential Revision: https://reviews.llvm.org/D102722
2021-05-21 18:13:45 +02:00
Navdeep Kumar eaaf7a6a09 [MLIR][GPU][NVVM] Add conversion of warp synchronous matrix-multiply accumulate GPU ops
Add conversion of warp synchronous matrix-multiply
accumulate GPU ops
Add conversion of warp synchronous matrix-multiply accumulate GPU ops to
NVVM ops. The following conversions are added :-
  1.) subgroup_mma_load_matrix -> wmma.m16n16k16.load.[a,b,c]..row.stride
  2.) subgroup_mma_store_matrix -> wmma.m16n16k16.store.d.[f16,f32].row.stride
  3.) subgroup_mma_compute -> wmma.m16n16k16.mma.row.row.[f16,f32].[f16,f32]

Reviewed By: bondhugula, ftynse

Differential Revision: https://reviews.llvm.org/D95331
2021-05-21 21:20:33 +05:30
Stephan Herhut 90e55dfcf4 [mlir][memref] Improve canonicalization of memref.clone
The previous implementation did not handle casting behavior properly and
did not consider aliases.

Differential Revision: https://reviews.llvm.org/D102785
2021-05-21 16:34:50 +02:00
Matthias Springer 8fb4897934 [mlir] Disallow tensor types in VectorToSCF
Support for tensor types can be added if needed.

Differential Revision: https://reviews.llvm.org/D102749
2021-05-21 22:45:14 +09:00
Stephan Herhut 884a6291f0 [mlir][linalg] Add scalar operands inlining pattern
This pattern inlines operands to a linalg.generic operation that use a constant
index and hence are loop-invariant scalars. This reduces the number of
linalg.generic operands and unlocks some canonicalizations that rely on seeing
an explicit tensor.extract.

Differential Revision: https://reviews.llvm.org/D102682
2021-05-21 15:23:28 +02:00
Adrian Kuegel 28844212fe [mlir] Add additional traits to EqualOp and NotEqualOp.
This matches the traits of the other binary ops.

Differential Revision: https://reviews.llvm.org/D102916
2021-05-21 15:04:26 +02:00
Nicolas Vasilache 8eb18a0f3e [mlir][Standard] NFC - Drop remaining EDSC usage
Drop the remaining EDSC subdirectories and update all uses.

Differential Revision: https://reviews.llvm.org/D102911
2021-05-21 10:40:39 +00:00
Adrian Kuegel a1a429dc1d [mlir] NFC - Use builder.getI1Type() 2021-05-21 11:44:57 +02:00
Adrian Kuegel 7eb85cdb10 [mlir] Add convenience builders for EqualOp and NotEqualOp.
The result type is always I1. This additional builder allows to omit the result type.

Differential Revision: https://reviews.llvm.org/D102905
2021-05-21 11:32:25 +02:00
Adrian Kuegel fb8b2b86d3 [mlir] Add conversion from Complex to Standard dialect for NotEqualOp.
Differential Revision: https://reviews.llvm.org/D102902
2021-05-21 10:46:50 +02:00
Konrad Kleine 0297506d20 [mlir] Rename MlirLspServerLib -> MLIRLspServerLib
I noticed while packaging mlir that most mlir library names start
with `libMLIR`. The only different libary was `libMlirLspServerLib.a`.

That's why I changed the library to be similarly named to the others.

Differential Revision: https://reviews.llvm.org/D102881
2021-05-21 10:25:54 +02:00
Nicolas Vasilache e84a9b9bb3 [mlir][Affine] NFC - Drop Affine EDSC usage
Drop the Affine dialect EDSC subdirectory and update all uses.

Differential Revision: https://reviews.llvm.org/D102878
2021-05-20 21:45:45 +00:00
Nicolas Vasilache e3cf7c88c4 [mlir][MemRef] NFC - Drop MemRef EDSC usage
Drop the MemRef dialect EDSC subdirectory and update all uses.

Differential Revision: https://reviews.llvm.org/D102868
2021-05-20 20:13:58 +00:00
Nicolas Vasilache 4519ca3d2e [mlir][Linalg] NFC - Drop Linalg EDSC usage
Drop the Linalg dialect EDSC subdirectory and update all uses.

Differential Revision: https://reviews.llvm.org/D102848
2021-05-20 15:33:56 +00:00
Adrian Kuegel ac00cb0d2a [mlir] Add conversion from complex to standard dialect for EqualOp.
This adds the straightforward conversion for EqualOp
(two complex numbers are equal if both the real and the imaginary part are equal).

Differential Revision: https://reviews.llvm.org/D102840
2021-05-20 14:25:56 +02:00
Adrian Kuegel a28fe17d73 [mlir] Add EqualOp and NotEqualOp to complex dialect. 2021-05-20 13:25:07 +02:00
Nicolas Vasilache ef33c6e3ce [mlir][Linalg] Drop spurious usage of OperationFolder
Instead, use createOrFold builders which result in more static information available.

Differential Revision: https://reviews.llvm.org/D102832
2021-05-20 09:17:58 +00:00
Matthias Springer 4cd1b66dff [mlir] Add Python bindings for vector dialect
Also add a minimal test case for vector.print.

Differential Revision: https://reviews.llvm.org/D102826
2021-05-20 17:53:08 +09:00
Tobias Gysi 99a198641c [mlir][Python][linalg] Fix to limit size of SmallVector.
Stack allocate at most two ScalarAssign elements. Using the default number of inlined elements triggered a static assert in some setups (https://reviews.llvm.org/D102075).

Differential Revision: https://reviews.llvm.org/D102827
2021-05-20 07:24:41 +00:00
River Riddle 92469ca027 [mlir] Refactor the implementation of pass crash reproducers
The current implementation has several key limitations and weirdness, e.g local reproducers don't support dynamic pass pipelines, error messages don't include the passes that failed, etc. This revision refactors the implementation to support more use cases, and also be much cleaner.

The main change in this revision, aside from moving the implementation out of Pass.cpp and into its own file, is the addition of a crash recovery pass instrumentation. For local reproducers, this instrumentation handles setting up the recovery context before executing each pass. For global reproducers, the instrumentation is used to provide a more detailed error message, containing information about which passes are running and on which operations.

Example of new message:

```
error: Failures have been detected while processing an MLIR pass pipeline
note: Pipeline failed while executing [`TestCrashRecoveryPass` on 'module' operation: @foo]: reproducer generated at `crash-recovery.mlir.tmp`
```

Differential Revision: https://reviews.llvm.org/D101854
2021-05-19 16:59:53 -07:00
River Riddle 64ce90e1af [mlir] Add a new `print-ir-after-failure` IR pass printing flag
This flag will print the IR after a pass only in the case where the pass failed. This can be useful to more easily view the invalid IR, without needing to print after every pass in the pipeline.

Differential Revision: https://reviews.llvm.org/D101853
2021-05-19 16:54:20 -07:00
hasheddan 0316f3e649 [mlir][docs] Fix minor typos in vector dialect docs
Updates a minor typo in vector dialect documentation.

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D101203
2021-05-19 14:20:28 -07:00
Aart Bik bf9ef3efaa [mlir][sparse] skip sparsification for unannotated (or unhandled) cases
Skip the sparsification pass for Linalg ops without annotated tensors
(or cases that are not properly handled yet).

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D102787
2021-05-19 13:49:28 -07:00
River Riddle 3b7f8daed4 [mlir] Properly align StorageUniquer::BaseStorage to fix 32 bit build
We allow stealing up to 3 bits of pointers to BaseStorage, so we need to make sure that we align by at least 8.
2021-05-19 13:46:43 -07:00
Marius Brehler f878e1af9f [mlir] Harmonize TOSA include guards
Reviewed By: sjarus

Differential Revision: https://reviews.llvm.org/D102802
2021-05-19 22:45:06 +02:00
Sean Silva 35454268cf [mlir][CAPI] Expose [u]int8 DenseElementsAttr.
Also, fix a small typo where the "unsigned" splat variants were not
being created with an unsigned type.

Differential Revision: https://reviews.llvm.org/D102797
2021-05-19 13:41:44 -07:00
Marius Brehler 745ddd27ea [mlir] Add include guard to TOSA tblgen passes
Reviewed By: sjarus, stellaraccident

Differential Revision: https://reviews.llvm.org/D102800
2021-05-19 22:02:31 +02:00