5e7ee0a002
Also LXCHG64 -> XCHG64rm.
...
llvm-svn: 49948
2008-04-19 02:05:42 +00:00
00bd8d904a
- Fix atomic operation JIT encoding.
...
- Remove unused instructions.
llvm-svn: 49921
2008-04-18 20:55:36 +00:00
29e62a59f3
Allow certain lea instructions to be rematerialized.
...
llvm-svn: 48855
2008-03-27 01:41:09 +00:00
7da2bceb3b
Don't loose incoming argument registers. Fix documentation style.
...
llvm-svn: 48545
2008-03-19 16:39:45 +00:00
d3d0ad3f58
Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.
...
llvm-svn: 48412
2008-03-16 03:12:01 +00:00
0e7b00d79f
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
...
llvm-svn: 48380
2008-03-15 00:03:38 +00:00
96bdbd6c5d
Fix a number of encoding bugs. SSE 4.1 instructions MPSADBWrri, PINSRDrr, etc. have 8-bits immediate field (ImmT == Imm8).
...
llvm-svn: 48360
2008-03-14 07:39:27 +00:00
dd55d3f1b2
Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects.
...
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329
2008-03-13 05:47:01 +00:00
d4e1d9eeb2
Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.
...
llvm-svn: 48167
2008-03-10 19:31:26 +00:00
4ba3f0430b
Allow insert_subreg into implicit, target-specific values.
...
Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.
llvm-svn: 48130
2008-03-10 06:12:08 +00:00
4fee9f35b5
x86-64 atomics
...
llvm-svn: 47903
2008-03-04 21:13:33 +00:00
3c7d3d5700
Compile x86-64-and-mask.ll into:
...
_test:
movl %edi, %eax
ret
instead of:
_test:
movl $4294967295, %ecx
movq %rdi, %rax
andq %rcx, %rax
ret
It would be great to write this as a Pat pattern that used subregs
instead of a 'pseudo' instruction, but I don't know how to do that
in td files.
llvm-svn: 47658
2008-02-27 05:47:54 +00:00
8ef50214f0
SSE4.1 64b integer insert/extract pattern support
...
Move formats into the formats file
llvm-svn: 47035
2008-02-12 22:51:28 +00:00
a20a773654
Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
...
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
llvm-svn: 46850
2008-02-07 08:53:49 +00:00
e14fdfaecd
SSE 4.1 Intrinsics and detection
...
llvm-svn: 46681
2008-02-03 07:18:54 +00:00
084a1cdcdd
Work in progress. This patch *fixes* x86-64 calls which are modelled as StructRet but really should be return in registers, e.g. _Complex long double, some 128-bit aggregates. This is a short term solution that is necessary only because llvm, for now, cannot model i128 nor call's with multiple results.
...
Status: This only works for direct calls, and only the caller side is done. Disabled for now.
llvm-svn: 46527
2008-01-29 19:34:22 +00:00
95d46ef887
The last pieces needed for loading arbitrary
...
precision integers. This won't actually work
(and most of the code is dead) unless the new
legalization machinery is turned on. While
there, I rationalized the handling of i1, and
removed some bogus (and unused) sextload patterns.
For i1, this could result in microscopically
better code for some architectures (not X86).
It might also result in worse code if annotating
with AssertZExt nodes turns out to be more harmful
than helpful.
llvm-svn: 46280
2008-01-23 20:39:46 +00:00
806dd0e2ac
remove xchg and shift-reg-by-1 instructions, which are dead.
...
llvm-svn: 45870
2008-01-11 18:00:50 +00:00
8c51394e01
Rename Int_CVTSI642SSr* to Int_CVTSI2SS64r* for naming consistency and remove unused instructions.
...
llvm-svn: 45861
2008-01-11 07:37:44 +00:00
9283173061
more flags set right
...
llvm-svn: 45860
2008-01-11 07:18:17 +00:00
317332fc2a
Start inferring side effect information more aggressively, and fix many bugs in the
...
x86 backend where instructions were not marked maystore/mayload, and perf issues where
instructions were not marked neverHasSideEffects. It would be really nice if we could
write patterns for copy instructions.
I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on
other targets are probably not right in all cases, but no clients currently use this
info that are enabled by default.
llvm-svn: 45829
2008-01-10 07:59:24 +00:00
2e38f2458c
rename X86InstrX86-64.td -> X86Instr64bit.td
...
llvm-svn: 45826
2008-01-10 05:50:42 +00:00
Evan Cheng