Chris Lattner
120ad01fcb
start handling the 'f' x87 constraint.
...
llvm-svn: 48239
2008-03-11 19:06:29 +00:00
Christopher Lamb
342e4104d3
Missed part of recommit.
...
llvm-svn: 48224
2008-03-11 10:27:36 +00:00
Christopher Lamb
aa7c2105de
Recommitting parts of r48130. These do not appear to cause the observed failures.
...
llvm-svn: 48223
2008-03-11 10:09:17 +00:00
Evan Cheng
d85667b89c
If there are multiple register classes that a register belongs to, return the super-class (e.g. on x86, returns GR32, not GR32_).
...
llvm-svn: 48220
2008-03-11 07:54:14 +00:00
Evan Cheng
e88a625ecd
When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting.
...
llvm-svn: 48218
2008-03-11 07:19:34 +00:00
Evan Cheng
5b59e372dc
In 32-bit mode, mark 64-bit GPR's as unallocatable.
...
llvm-svn: 48217
2008-03-11 07:16:00 +00:00
Nick Lewycky
a3860a2422
Fix the build on gcc 4.2.
...
llvm-svn: 48212
2008-03-11 05:56:09 +00:00
Chris Lattner
1bd44363f2
Change the model for FP Stack return to use fp operands on the
...
RET instruction instead of using FpSET_ST0_32. This also generalizes
the code to handling returning of multiple FP results.
llvm-svn: 48209
2008-03-11 03:23:40 +00:00
Dan Gohman
d6819da453
Generalize ExpandIntToFP to handle the case where the operand is legal
...
and it's the result that requires expansion. This code is a little confusing
because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type
(the integer type) rather than the result type.
llvm-svn: 48206
2008-03-11 01:59:03 +00:00
Chris Lattner
a4fa0ad30d
abort with an assert instead of a cerr to get line#
...
llvm-svn: 48199
2008-03-10 23:56:08 +00:00
Scott Michel
92275427e5
- Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency.
...
- Add test pattern matching in CellSPU's icmp32.ll test harness
- Fix CellSPU fcmp.ll-generated assert.
llvm-svn: 48197
2008-03-10 23:49:09 +00:00
Chris Lattner
7362d38391
Don't emit FP_REG_KILL into a block that just returns. Nothing
...
can be live out of the block anyway, so it isn't needed.
llvm-svn: 48192
2008-03-10 23:34:12 +00:00
Dale Johannesen
0fb187f81b
Disable prolog code that aligns the stack when a
...
local object of >16 byte alignment exists. It does not
work and getting it to work is not trivial, as explained
in the comment. This fixes all the remaining ppc32
failures in the struct-layout-1 part of the gcc testsuite.
(gcc does not support this either, and the only way to
get such an object is with __attribute__((aligned)) or
generic vectors; it can't be done in a standard-conforming
program, or with Altivec. So I think disabling it is OK.)
llvm-svn: 48188
2008-03-10 22:59:46 +00:00
Bill Wendling
c6c48fca74
Change the "enable/disable" mechanism so that we can enable PPC register
...
scavenging for 32-bit and 64-bit separately.
llvm-svn: 48186
2008-03-10 22:49:16 +00:00
Chris Lattner
4b3a7fa823
Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to
...
copyfromreg/copytoreg instead.
llvm-svn: 48174
2008-03-10 21:08:41 +00:00
Evan Cheng
ae2c56d93e
Default ISD::PREFETCH to expand.
...
llvm-svn: 48169
2008-03-10 19:38:10 +00:00
Evan Cheng
d4e1d9eeb2
Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.
...
llvm-svn: 48167
2008-03-10 19:31:26 +00:00
Chris Lattner
514b3ed536
fix 80 col violations.
...
llvm-svn: 48166
2008-03-10 18:55:53 +00:00
Nicolas Geoffray
708784ea4f
Stylistic modifications. No functionality changes.
...
llvm-svn: 48158
2008-03-10 17:46:45 +00:00
Scott Michel
48e3375544
Integer comparison tests for CellSPU.
...
llvm-svn: 48152
2008-03-10 16:58:52 +00:00
Scott Michel
a6729e8666
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
...
return ValueType can depend its operands' ValueType.
This is a cosmetic change, no functionality impacted.
llvm-svn: 48145
2008-03-10 15:42:14 +00:00
Nicolas Geoffray
b1de7a35f9
Add description of individual bits in CR. This fix PR1765.
...
llvm-svn: 48143
2008-03-10 14:12:10 +00:00
Christopher Lamb
4ba3f0430b
Allow insert_subreg into implicit, target-specific values.
...
Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.
llvm-svn: 48130
2008-03-10 06:12:08 +00:00
Dale Johannesen
4e622ec86d
Increase ISD::ParamFlags to 64 bits. Increase the ByValSize
...
field to 32 bits, thus enabling correct handling of ByVal
structs bigger than 0x1ffff. Abstract interface a bit.
Fixes gcc.c-torture/execute/pr23135.c and
gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing
on ppc32, quietly producing wrong code on x86-32.)
llvm-svn: 48122
2008-03-10 02:17:22 +00:00
Chris Lattner
aed9406bb7
Darwin PPC64 indirect call target goes in X12, not R12. This fixes these
...
two regression tests:
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll
llvm-svn: 48120
2008-03-09 20:49:33 +00:00
Chris Lattner
78e817d7fc
cell really does support cross-regclass moves, because R3 is in lots of different regclasses, and the code is not consistent when it comes to value tracking.
...
llvm-svn: 48119
2008-03-09 20:31:11 +00:00
Chris Lattner
3ba79ed9e8
make sure ar.pfs is in a register class, this fixes test/CodeGen/IA64/ret-0.ll
...
llvm-svn: 48118
2008-03-09 20:12:44 +00:00
Chris Lattner
86829f0ff7
teach X86InstrInfo::copyRegToReg how to copy into ST(0) from
...
an RFP register class.
Teach ScheduleDAG how to handle CopyToReg with different src/dst
reg classes.
This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.
llvm-svn: 48107
2008-03-09 09:15:31 +00:00
Chris Lattner
b79bafcec8
add some code to support cross-register class copying from
...
RST -> RFP{32/64/80}. We only handle ST(0) for now.
llvm-svn: 48104
2008-03-09 08:46:19 +00:00
Chris Lattner
c4c9dde04c
rearrange some code, no functionality change.
...
llvm-svn: 48101
2008-03-09 07:58:04 +00:00
Chris Lattner
459f518703
claim ST(x) registers are 80 bits, which is true. This doesn't affect
...
codegen yet because these can't be spilled (they don't exist until after RA).
llvm-svn: 48098
2008-03-09 07:49:01 +00:00
Chris Lattner
4c869594bc
rename FP_SETRESULT -> FP_SET_ST0
...
llvm-svn: 48094
2008-03-09 07:08:44 +00:00
Chris Lattner
d587e580a6
rename FpGETRESULT32 -> FpGET_ST0_32 etc. Add support for
...
isel'ing value preserving FP roundings from one fp stack reg to another
into a noop, instead of stack traffic.
llvm-svn: 48093
2008-03-09 07:05:32 +00:00
Chris Lattner
b6387c8a74
Finish implementing a readme entry: when inserting an i64 variable
...
into a vector of zeros or undef, and when the top part is obviously
zero, we can just use movd + shuffle. This allows us to compile
vec_set-B.ll into:
_test3:
movl $1234567, %eax
andl 4(%esp), %eax
movd %eax, %xmm0
ret
instead of:
_test3:
subl $28, %esp
movl $1234567, %eax
andl 32(%esp), %eax
movl %eax, (%esp)
movl $0, 4(%esp)
movq (%esp), %xmm0
addl $28, %esp
ret
llvm-svn: 48090
2008-03-09 05:42:06 +00:00
Chris Lattner
93930dc28c
add a note
...
llvm-svn: 48064
2008-03-09 01:08:22 +00:00
Chris Lattner
eef374c197
Implement a readme entry, compiling
...
#include <xmmintrin.h>
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}
into:
movl $1, %eax
movd %eax, %xmm0
ret
instead of a constant pool load.
llvm-svn: 48063
2008-03-09 01:05:04 +00:00
Chris Lattner
ad58828354
1) Improve comments.
...
2) Don't try to insert an i64 value into the low part of a
vector with movq on an x86-32 target. This allows us to
compile:
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}
into:
_doload64:
movaps LCPI1_0, %xmm0
ret
instead of:
_doload64:
subl $28, %esp
movl $0, 4(%esp)
movl $1, (%esp)
movq (%esp), %xmm0
addl $28, %esp
ret
llvm-svn: 48057
2008-03-08 22:59:52 +00:00
Chris Lattner
8a6ebd23a8
minor simplifications to this code, don't create a dead
...
SCALAR_TO_VECTOR on paths that end up not using it.
llvm-svn: 48056
2008-03-08 22:48:29 +00:00
Chris Lattner
35adf46967
This one looks easy, add a note.
...
llvm-svn: 48055
2008-03-08 22:32:39 +00:00
Chris Lattner
a76e23a935
move these to the appropriate file
...
llvm-svn: 48054
2008-03-08 22:28:45 +00:00
Dale Johannesen
21a8f144a6
More ppc32 byval handling (bug fixes). Things
...
are looking pretty good now.
llvm-svn: 48043
2008-03-08 01:41:42 +00:00
Evan Cheng
95cf661534
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
...
llvm-svn: 48042
2008-03-08 00:58:38 +00:00
Dan Gohman
d2ab5fd713
Add support for calls with i128 return values on ppc64.
...
llvm-svn: 48041
2008-03-08 00:19:12 +00:00
Bill Wendling
968f32ce3d
PPC64 passes arguments of integral type in i64 registers, not i32. Reflect this
...
by promoting smaller integral values (i32 at this point) to i64, then truncating
to get the wanted size.
llvm-svn: 48030
2008-03-07 20:49:02 +00:00
Dan Gohman
8d2ead2e34
Add support for lowering 128-bit shifts on ppc64.
...
llvm-svn: 48029
2008-03-07 20:36:53 +00:00
Dale Johannesen
bfa252d402
Next bits of PPC byval handling. Basically functional
...
but there are bugs.
llvm-svn: 48028
2008-03-07 20:27:40 +00:00
Chris Lattner
20b5a2b037
Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl).
...
llvm-svn: 48027
2008-03-07 20:18:24 +00:00
Chris Lattner
25ff7e217d
Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work
...
with 32 or 64-bit operands/results.
llvm-svn: 48026
2008-03-07 20:13:51 +00:00
Chris Lattner
d4defb00df
mark frem as expand for all legal fp types on x86, regardless of whether
...
we're using SSE or not. This fixes PR2122.
llvm-svn: 48006
2008-03-07 06:36:32 +00:00
Gabor Greif
636ab19205
some more spelling changes
...
llvm-svn: 47996
2008-03-06 10:51:21 +00:00
Scott Michel
e9b690b7f1
Refine Cell's i64 constant generation code to cover more constants where the
...
upper and lower 32-bits are the same (in addition to 0 and -1 previously.)
llvm-svn: 47985
2008-03-06 04:02:54 +00:00
Andrew Lenharth
dcabdb1b38
gcc likes things spelled correctly
...
llvm-svn: 47981
2008-03-05 23:41:37 +00:00
Dale Johannesen
0d235052d1
Next bit of PPC ByVal handling; call-site code seems
...
correct now.
llvm-svn: 47978
2008-03-05 23:31:27 +00:00
Scott Michel
42f56b4838
- Fix support for "special" i64 immediates that can be loaded
...
using IL, ILA, et. al. v2i64 and i64 are now supported by
the select bits (SELB) instruction.
- Add missing comparison operations (testcase forthcoming)
- More multiclass refactoring.
llvm-svn: 47973
2008-03-05 23:02:02 +00:00
Chris Lattner
7c08a01698
evan implemented this.
...
llvm-svn: 47948
2008-03-05 17:11:51 +00:00
Evan Cheng
3ea44e4ee9
isTwoAddress = 1 -> Constraints.
...
llvm-svn: 47941
2008-03-05 08:19:16 +00:00
Evan Cheng
6ec7dc6bea
PSLLWri etc. are two-address instructions.
...
llvm-svn: 47940
2008-03-05 08:11:27 +00:00
Chris Lattner
2acd0c25f6
add a note
...
llvm-svn: 47939
2008-03-05 07:22:39 +00:00
Evan Cheng
3bd59641ac
Ignore debugging related instructions if they get this far.
...
llvm-svn: 47934
2008-03-05 02:34:36 +00:00
Evan Cheng
801bfb2cf7
Rather than asserting. Dump out the MI that we are not able to encode and abort.
...
llvm-svn: 47933
2008-03-05 02:08:03 +00:00
Evan Cheng
0a62cb44ce
Add a target lowering hook to control whether it's worthwhile to compress fp constant.
...
For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive.
llvm-svn: 47931
2008-03-05 01:30:59 +00:00
Andrew Lenharth
357061a74d
64bit CAS on 32bit x86.
...
llvm-svn: 47929
2008-03-05 01:15:49 +00:00
Evan Cheng
6325446666
Refactor code. Remove duplicated functions that basically do the same thing as
...
findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies.
llvm-svn: 47927
2008-03-05 00:59:57 +00:00
Bill Wendling
3fcd946c26
Removed spurious EnablePPCRS check.
...
llvm-svn: 47918
2008-03-04 23:27:33 +00:00
Dale Johannesen
85d41a1c44
Move PPC lowering functions into PPCTargetLowering
...
class (cosmetic). First piece of byval implementation;
this doesn't work yet. No functional change.
llvm-svn: 47917
2008-03-04 23:17:14 +00:00
Bill Wendling
1af20ad336
Use a command-line option to turn register scavenging on/off for PPC.
...
llvm-svn: 47915
2008-03-04 23:13:51 +00:00
Andrew Lenharth
4fee9f35b5
x86-64 atomics
...
llvm-svn: 47903
2008-03-04 21:13:33 +00:00
Evan Cheng
59d58ab8c4
80 column violations.
...
llvm-svn: 47878
2008-03-04 03:20:06 +00:00
Evan Cheng
33ff36321e
Remove -always-fold-and-in-test.
...
llvm-svn: 47871
2008-03-04 00:40:35 +00:00
Dan Gohman
a986eea82f
Add support for lowering i64 SRA_PARTS and friends on x86-64.
...
llvm-svn: 47865
2008-03-03 22:22:09 +00:00
Bill Wendling
632ea65072
This is the initial check-in for adding register scavenging to PPC. (Currently,
...
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.
llvm-svn: 47863
2008-03-03 22:19:16 +00:00
Devang Patel
9d91785987
s/isReturnStruct()/hasStructRetAttr()/g
...
llvm-svn: 47857
2008-03-03 21:46:28 +00:00
Chris Lattner
d51372aa96
another random note
...
llvm-svn: 47831
2008-03-02 19:29:42 +00:00
Chris Lattner
6b0a189225
add a note
...
llvm-svn: 47830
2008-03-02 19:27:34 +00:00
Chris Lattner
a70df9e2ee
Evan implemented these.
...
llvm-svn: 47828
2008-03-02 18:05:14 +00:00
Chris Lattner
bd0bb3f07f
Evan implemented this.
...
llvm-svn: 47827
2008-03-02 17:56:29 +00:00
Chris Lattner
c93b48caeb
add support for lvsl, fixing PR1481
...
llvm-svn: 47825
2008-03-02 08:54:27 +00:00
Chris Lattner
8fb4c98284
add support for the sse.cmp.* intrinsics, which fixes sse.isamax with the CBE.
...
llvm-svn: 47824
2008-03-02 08:47:13 +00:00
Chris Lattner
9044719798
refactor intrinsic handling code out into its own method.
...
llvm-svn: 47823
2008-03-02 08:29:41 +00:00
Chris Lattner
2541f1dac6
fix printing of undef vectors, this fixes "simple" and "build" in UnitTests/Vector.
...
Now they all pass.
llvm-svn: 47820
2008-03-02 08:14:45 +00:00
Chris Lattner
4c058b39e4
insertelement got the wrong operands.
...
llvm-svn: 47819
2008-03-02 08:10:16 +00:00
Chris Lattner
051709436e
Several changes:
...
* Simplify handling of byval, making it easier to understand and more
consistent. This fixes PR2065.
* Clean up and simplify handling of GEPs. I can actually understand it now!
* Implement support for GEP'ing into vectors, this fixes
SingleSource/UnitTests/Vector/build2 among others.
llvm-svn: 47818
2008-03-02 08:07:24 +00:00
Chris Lattner
9140fba6ad
Fix a bug I introduced in constant array and constant vector handling.
...
llvm-svn: 47816
2008-03-02 05:46:57 +00:00
Chris Lattner
7295bc15a0
implement shufflevector.
...
llvm-svn: 47815
2008-03-02 05:41:07 +00:00
Chris Lattner
689d830b6d
implement extractelement.
...
llvm-svn: 47812
2008-03-02 03:57:08 +00:00
Chris Lattner
d9cc003b0d
implement insertelement.
...
llvm-svn: 47811
2008-03-02 03:52:39 +00:00
Chris Lattner
92d929c21d
respect isSigned for vector types, fixing sdiv of vectors etc.
...
llvm-svn: 47810
2008-03-02 03:41:23 +00:00
Chris Lattner
fe1083be61
print the attribute in the right place, this fixes function returning vectors.
...
llvm-svn: 47809
2008-03-02 03:39:43 +00:00
Chris Lattner
d861066d15
vector types are simple types. This fixes div/rem of vectors.
...
llvm-svn: 47807
2008-03-02 03:33:31 +00:00
Chris Lattner
b104be599a
Print vector types appropriately. This gets basic vector code working
...
(PR1126)
llvm-svn: 47806
2008-03-02 03:29:50 +00:00
Chris Lattner
c8d974a323
rename PT -> VT for VectorTypes.
...
llvm-svn: 47805
2008-03-02 03:18:46 +00:00
Chris Lattner
895aef4720
Print i32/i64 integer constants as 1u instead of ((unsigned int)1).
...
Use dyn_cast better.
llvm-svn: 47804
2008-03-02 03:16:38 +00:00
Chris Lattner
647c6642e7
Move pr717 to here.
...
llvm-svn: 47803
2008-03-02 02:51:40 +00:00
Andrew Lenharth
20bcdba9ca
good catch anton
...
llvm-svn: 47800
2008-03-01 23:18:21 +00:00
Andrew Lenharth
f5c90ec12c
make CAS work
...
llvm-svn: 47799
2008-03-01 22:27:48 +00:00
Andrew Lenharth
d032c33300
all but CAS working on x86
...
llvm-svn: 47798
2008-03-01 21:52:34 +00:00
Andrew Lenharth
0070dd1de3
Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode.
...
llvm-svn: 47795
2008-03-01 13:37:02 +00:00
Anton Korobeynikov
0e8b146152
Use enumeration for preffered EH dwarf encoding reason
...
llvm-svn: 47770
2008-02-29 22:09:08 +00:00
Anders Carlsson
17df4cd397
Use the correct instruction encodings for the 64-bit MMX movd.
...
llvm-svn: 47740
2008-02-29 01:35:12 +00:00
Evan Cheng
95a7be473c
Added option -align-loops=<true/false> to disable loop aligner pass.
...
llvm-svn: 47736
2008-02-28 23:29:57 +00:00
Dale Johannesen
cbde4c2206
Interface of getByValTypeAlignment differed between
...
generic & x86 versions; change generic to follow x86
and improve comments. Add PPC version (not right
for non-Darwin.)
llvm-svn: 47734
2008-02-28 22:31:51 +00:00
Lauro Ramos Venancio
714eeb2d55
Initialize TextAlignFillValue. Fix revision 47703.
...
llvm-svn: 47732
2008-02-28 22:14:09 +00:00
Lauro Ramos Venancio
9781aee03c
Avoid collisions in value names.
...
llvm-svn: 47725
2008-02-28 20:26:04 +00:00
Chris Lattner
643dce1146
add a note
...
llvm-svn: 47720
2008-02-28 17:21:27 +00:00
Evan Cheng
507713de08
Set to default: x86 no longer fold and into test if it has more than one use.
...
llvm-svn: 47711
2008-02-28 07:46:38 +00:00
Chris Lattner
e2f55f9fc5
Sparc backend doesn't support debug info yet, mark the nodes as expand. This fixes a crash on
...
test/DebugInfo/funccall.ll
llvm-svn: 47709
2008-02-28 05:54:25 +00:00
Chris Lattner
f1444c35e8
Fix CodeGen/Generic/storetrunc-fp.ll on sparc, PR2105
...
llvm-svn: 47707
2008-02-28 05:48:04 +00:00
Chris Lattner
beb6a5ba4f
fix CodeGen/Generic/2008-01-25-dag-combine-mul.ll on sparc, PR2105
...
llvm-svn: 47706
2008-02-28 05:44:20 +00:00
Chris Lattner
765be8874d
target-indep codegen memcpy lowering issue.
...
llvm-svn: 47705
2008-02-28 05:34:27 +00:00
Chris Lattner
83e80cd368
Add a random not very important note
...
llvm-svn: 47704
2008-02-28 04:52:59 +00:00
Evan Cheng
c799065cc3
Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries.
...
llvm-svn: 47703
2008-02-28 00:43:03 +00:00
Eli Friedman
93e8b679a3
A few more small things I've run into.
...
llvm-svn: 47702
2008-02-28 00:21:43 +00:00
Anton Korobeynikov
d73396bef9
EHPreferredDataFormat hook for PPC targets. Looks like Darwin
...
uses the same encoding everywhere. Linux FIXME'ed.
llvm-svn: 47701
2008-02-27 23:49:15 +00:00
Anton Korobeynikov
ae24cca0e4
Preparation step for some cleanup/generalization in EH information emission:
...
provide TAI hook for selection of EH data emission format. Currently unused.
llvm-svn: 47699
2008-02-27 23:33:50 +00:00
Dan Gohman
26854f242e
Don't hard-code the mask size to be 32, which is incorrect on ppc64
...
and was causing aborts with the new APInt changes. This may also be
fixing an obscure ppc64 bug.
llvm-svn: 47692
2008-02-27 21:12:32 +00:00
Evan Cheng
3d17e4c427
This is done.
...
llvm-svn: 47688
2008-02-27 20:26:32 +00:00
Bill Wendling
97925ec704
Final de-tabification.
...
llvm-svn: 47663
2008-02-27 06:33:05 +00:00
Chris Lattner
83263b8cfb
Make X86TargetLowering::LowerSINT_TO_FP return without creating a dead
...
stack slot and store if the SINT_TO_FP is actually legal. This allows
us to compile:
double a(double b) {return (unsigned)b;}
to:
_a:
cvttsd2siq %xmm0, %rax
movl %eax, %eax
cvtsi2sdq %rax, %xmm0
ret
instead of:
_a:
subq $8, %rsp
cvttsd2siq %xmm0, %rax
movl %eax, %eax
cvtsi2sdq %rax, %xmm0
addq $8, %rsp
ret
crazy.
llvm-svn: 47660
2008-02-27 05:57:41 +00:00
Chris Lattner
5fe95a04f5
this code is correct but strange looking ;-)
...
llvm-svn: 47659
2008-02-27 05:48:44 +00:00
Chris Lattner
3c7d3d5700
Compile x86-64-and-mask.ll into:
...
_test:
movl %edi, %eax
ret
instead of:
_test:
movl $4294967295, %ecx
movq %rdi, %rax
andq %rcx, %rax
ret
It would be great to write this as a Pat pattern that used subregs
instead of a 'pseudo' instruction, but I don't know how to do that
in td files.
llvm-svn: 47658
2008-02-27 05:47:54 +00:00
Evan Cheng
6d56368caf
Spiller now remove unused spill slots.
...
llvm-svn: 47657
2008-02-27 03:04:06 +00:00
Dan Gohman
f19609abe8
Convert the last remaining users of the non-APInt form of
...
ComputeMaskedBits to use the APInt form, and remove the
non-APInt form.
llvm-svn: 47654
2008-02-27 01:23:58 +00:00
Chris Lattner
3f86109fd1
add a note
...
llvm-svn: 47652
2008-02-27 01:17:20 +00:00
Arnold Schwaighofer
3bfca3e942
Refactor according to Evan's and Anton's suggestions.
...
llvm-svn: 47635
2008-02-26 22:21:54 +00:00
Bill Wendling
d7a258d325
Rename PrintableName to Name.
...
llvm-svn: 47629
2008-02-26 21:47:57 +00:00
Bill Wendling
c24ea4fb41
Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool
...
would have been a Godsend here!
llvm-svn: 47625
2008-02-26 21:11:01 +00:00
Arnold Schwaighofer
1f17bf6171
Correct function comments.
...
llvm-svn: 47606
2008-02-26 17:50:59 +00:00
Bill Wendling
80d6b87934
De-tabify
...
llvm-svn: 47600
2008-02-26 10:57:23 +00:00
Arnold Schwaighofer
69a10f4112
Add support for intermodule tail calls on x86/32bit with
...
GOT-style position independent code. Before only tail calls to
protected/hidden functions within the same module were optimized.
Now all function calls are tail call optimized.
llvm-svn: 47594
2008-02-26 10:21:54 +00:00
Arnold Schwaighofer
b01b99ec78
Change the lowering of arguments for tail call optimized
...
calls. Before arguments that could overwrite each other were
explicitly lowered to a stack slot, not giving the register allocator
a chance to optimize. Now a sequence of copyto/copyfrom virtual
registers ensures that arguments are loaded in (virtual) registers
before they are lowered to the stack slot (and might overwrite each
other). Also parameter stack slots are marked mutable for
(potentially) tail calling functions.
llvm-svn: 47593
2008-02-26 09:19:59 +00:00
Dan Gohman
a790af3a88
Revert the assert for MUL_LOHI with an unused high result; Chris
...
pointed out that this isn't correct at -O0.
llvm-svn: 47575
2008-02-25 22:43:48 +00:00
Dale Johannesen
65b404d61c
Revise previous patch per review.
...
llvm-svn: 47573
2008-02-25 22:29:22 +00:00
Dan Gohman
0be2f3b941
Add an assert to verify that we don't see an
...
{S,U}MUL_LOHI with an unused high value.
llvm-svn: 47569
2008-02-25 22:15:55 +00:00
Dan Gohman
2ff975e749
Remove the hack that turned an {S,U}MUL_LOHI with an unused high
...
result into a MUL late in the X86 codegen process. ISD::MUL is
once again Legal on X86, so this is no longer needed. And, the
hack was suboptimal; see PR1874 for details.
llvm-svn: 47567
2008-02-25 21:57:04 +00:00
Dan Gohman
1f372edd97
Convert MaskedValueIsZero and all its users to use APInt. Also add
...
a SignBitIsZero function to simplify a common use case.
llvm-svn: 47561
2008-02-25 21:11:39 +00:00
Dale Johannesen
32d84b1772
Expand removal of MMX memory copies to allow 1 level
...
of TokenFactor underneath chain (seems to be enough)
llvm-svn: 47554
2008-02-25 19:20:14 +00:00
Bill Wendling
a7d1ed4c98
Some platforms use the same name for 32-bit and 64-bit registers (like
...
%r3 on PPC) in their ASM files. However, it's hard for humans to read
during debugging. Adding a new field to the register data that lets you
specify a different name to be printed than the one that goes into the
ASM file -- %x3 instead of %r3, for instance.
llvm-svn: 47534
2008-02-24 00:56:13 +00:00
Scott Michel
7d5eaec6dd
Merge current work back to tree to minimize diffs and drift. Major highlights
...
for CellSPU modifications:
- SPUInstrInfo.td refactoring: "multiclass" really is _your_ friend.
- Other improvements based on refactoring effort in SPUISelLowering.cpp,
esp. in SPUISelLowering::PerformDAGCombine(), where zero amount shifts and
rotates are now eliminiated, other scalar-to-vector-to-scalar silliness
is also eliminated.
- 64-bit operations are being implemented, _muldi3.c gcc runtime now
compiles and generates the right code. More work still needs to be done.
llvm-svn: 47532
2008-02-23 18:41:37 +00:00
Evan Cheng
42cb72e52c
Turning on remat of pic loads.
...
llvm-svn: 47524
2008-02-23 02:07:42 +00:00
Evan Cheng
4d17671997
No need recognize load from a fixed argument slot as re-materializable. LiveIntervalAnalysis already handles it as a special case.
...
llvm-svn: 47522
2008-02-23 01:47:44 +00:00
Dale Johannesen
09f410b6d7
Split ParameterAttributes.h, putting the complicated
...
stuff into ParamAttrsList.h. Per feedback from
ParamAttrs changes.
llvm-svn: 47504
2008-02-22 22:17:59 +00:00
Dale Johannesen
eac159c1f0
MMX vectors are passed 4-byte aligned.
...
llvm-svn: 47483
2008-02-22 17:47:28 +00:00
Evan Cheng
94ba37f8e3
Allow re-materialization of pic load (controlled by -remat-pic-load for now).
...
llvm-svn: 47476
2008-02-22 09:25:47 +00:00
Chris Lattner
ab8bfc28c8
copy mmx values from/to memory with GPRs on x86-32
...
instead of with mmx registers. This horribleness is apparently
done by gcc to avoid having to insert emms in places that really
should have it. This is the second half of rdar://5741668.
llvm-svn: 47474
2008-02-22 05:18:04 +00:00
Chris Lattner
997b3a65ca
Start using GPR's to copy around mmx value instead of mmx regs.
...
GCC apparently does this, and code depends on not having to do
emms when this happens. This is x86-64 only so far, second half
should handle x86-32.
rdar://5741668
llvm-svn: 47470
2008-02-22 02:09:43 +00:00
Eli Friedman
5d8fa828f1
A few minor updates, removing implemented stuff and adding a couple of
...
new things.
llvm-svn: 47458
2008-02-21 21:16:49 +00:00
Chris Lattner
e86c91f5b2
Dan implemented one multiply issue. Replace it with another. :)
...
llvm-svn: 47431
2008-02-21 06:51:29 +00:00
Andrew Lenharth
95528943e9
Atomic op support. If any gcc test uses __sync builtins, it might start failing on archs that haven't implemented them yet
...
llvm-svn: 47430
2008-02-21 06:45:13 +00:00
Evan Cheng
b6b69208ba
Poorly named option.
...
llvm-svn: 47400
2008-02-20 20:57:32 +00:00
Evan Cheng
e43b6054b1
Temporarily backing out r47337. It breaks a number of CBE tests.
...
llvm-svn: 47385
2008-02-20 18:32:05 +00:00
Anton Korobeynikov
18991d78fa
Fix newly-introduced 4.3 warnings
...
llvm-svn: 47375
2008-02-20 12:07:57 +00:00
Anton Korobeynikov
852e214993
Fix code style
...
llvm-svn: 47370
2008-02-20 11:24:05 +00:00
Anton Korobeynikov
40d67c59d5
Remove bunch of gcc 4.3-related warnings from Target
...
llvm-svn: 47369
2008-02-20 11:22:39 +00:00
Anton Korobeynikov
579f07135a
Unbreak build with gcc 4.3: provide missed includes and silence most annoying warnings.
...
llvm-svn: 47367
2008-02-20 11:08:44 +00:00
Evan Cheng
7626ab33d8
Disable for now. This is pessimizing code.
...
llvm-svn: 47354
2008-02-20 02:29:17 +00:00
Evan Cheng
5ce8dd93ef
Add hidden option -x86-fold-and-in-test to test the effect the test / and folding change.
...
llvm-svn: 47351
2008-02-19 23:36:51 +00:00
Andrew Lenharth
4aa9e208fa
fix some byval problems in the cbe. Closes PR2065
...
llvm-svn: 47337
2008-02-19 19:47:54 +00:00
Chris Lattner
97b9662f78
Don't fold and's into test instructions if they have multiple uses.
...
This compiles test-nofold.ll into:
_test:
movl $15, %ecx
andl 4(%esp), %ecx
testl %ecx, %ecx
movl $42, %eax
cmove %ecx, %eax
ret
instead of:
_test:
movl 4(%esp), %eax
movl %eax, %ecx
andl $15, %ecx
testl $15, %eax
movl $42, %eax
cmove %ecx, %eax
ret
llvm-svn: 47330
2008-02-19 17:37:35 +00:00
Evan Cheng
3b56f506e7
Me not like duplicated comments.
...
llvm-svn: 47300
2008-02-19 02:05:16 +00:00
Evan Cheng
6200c225e0
- When DAG combiner is folding a bit convert into a BUILD_VECTOR, it should check if it's essentially a SCALAR_TO_VECTOR. Avoid turning (v8i16) <10, u, u, u> to <10, 0, u, u, u, u, u, u>. Instead, simply convert it to a SCALAR_TO_VECTOR of the proper type.
...
- X86 now normalize SCALAR_TO_VECTOR to (BIT_CONVERT (v4i32 SCALAR_TO_VECTOR)). Get rid of X86ISD::S2VEC.
llvm-svn: 47290
2008-02-18 23:04:32 +00:00
Dan Gohman
c589243107
Chris pointed out that it's not necessary to set i64 MUL to Expand
...
on x86-32 since i64 itself is not a Legal type. And, update some
comments.
llvm-svn: 47282
2008-02-18 19:34:53 +00:00
Chris Lattner
6bb6a55f01
upgrade some tests.
...
llvm-svn: 47280
2008-02-18 18:46:39 +00:00
Nate Begeman
0fddc34485
Add a note
...
llvm-svn: 47279
2008-02-18 18:39:23 +00:00
Chris Lattner
a827205670
Add a note about sext from i1 plus flags use.
...
llvm-svn: 47278
2008-02-18 18:30:13 +00:00
Dan Gohman
a589ee11bb
Don't mark scalar integer multiplication as Expand on x86, since x86
...
has plain one-result scalar integer multiplication instructions.
This avoids expanding such instructions into MUL_LOHI sequences that
must be special-cased at isel time, and avoids the problem with that
code that provented memory operands from being folded.
This fixes PR1874, addressesing the most common case. The uncommon
cases of optimizing multiply-high operations will require work
in DAGCombiner.
llvm-svn: 47277
2008-02-18 17:55:26 +00:00
Chris Lattner
1f6520842c
move PR2053 to here.
...
llvm-svn: 47237
2008-02-17 19:43:57 +00:00
Andrew Lenharth
fedcf477b5
I cannot find a libgcc function for this builtin. Therefor expanding it to a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support.
...
llvm-svn: 47213
2008-02-16 14:46:26 +00:00
Andrew Lenharth
9b254eed32
llvm.memory.barrier, and impl for x86 and alpha
...
llvm-svn: 47204
2008-02-16 01:24:58 +00:00
Chris Lattner
7b1431785b
Handle \n's in value names for more targets. The asm printers
...
really really really need refactoring :(
llvm-svn: 47171
2008-02-15 19:04:54 +00:00
Chris Lattner
318c41f9e8
If the llvm name contains an unprintable character, don't print it in
...
the global comment. This prevents printing things like:
... # foo
bar
when the name is "foo\nbar".
llvm-svn: 47170
2008-02-15 18:56:05 +00:00
Dale Johannesen
2e01912f1a
Cosmetics.
...
llvm-svn: 47168
2008-02-15 18:40:53 +00:00
Dale Johannesen
67b818f503
Remove warning about 64-bit code on processor
...
that doesn't support it. Per Chris.
llvm-svn: 47162
2008-02-15 18:09:51 +00:00
Dale Johannesen
401a4d72d5
nocona, core2 and penryn support 64 bit.
...
llvm-svn: 47149
2008-02-15 01:22:41 +00:00
Dale Johannesen
6ca3ccf519
Rewrite tblgen handling of subtarget features so
...
it follows the order of the enum, not alphabetical.
The motivation is to make -mattr=+ssse3,+sse41
select SSE41 as it ought to. Added "ignored"
enum values of 0 to PPC and SPU to avoid compiler
warnings.
llvm-svn: 47143
2008-02-14 23:35:16 +00:00
Nate Begeman
4b3210a3ec
Fix single precision FP constants on SPU. They are actually legal,
...
which allows us to kill a target-specific node.
llvm-svn: 47127
2008-02-14 18:43:04 +00:00
Duncan Sands
4c95dbd69f
In TargetLowering::LowerCallTo, don't assert that
...
the return value is zero-extended if it isn't
sign-extended. It may also be any-extended.
Also, if a floating point value was returned
in a larger floating point type, pass 1 as the
second operand to FP_ROUND, which tells it
that all the precision is in the original type.
I think this is right but I could be wrong.
Finally, when doing libcalls, set isZExt on
a parameter if it is "unsigned". Currently
isSExt is set when signed, and nothing is
set otherwise. This should be right for all
calls to standard library routines.
llvm-svn: 47122
2008-02-14 17:28:50 +00:00
Nate Begeman
53e1b3f9d5
Change how FP immediates are handled.
...
1) ConstantFP is now expand by default
2) ConstantFP is not turned into TargetConstantFP during Legalize
if it is legal.
This allows ConstantFP to be handled like Constant, allowing for
targets that can encode FP immediates as MachineOperands.
As a bonus, fix up Itanium FP constants, which now correctly match,
and match more constants! Hooray.
llvm-svn: 47121
2008-02-14 08:57:00 +00:00
Nate Begeman
64db2b9615
Move some useful operands up into the all-targets .td
...
llvm-svn: 47115
2008-02-14 07:25:46 +00:00
Chris Lattner
eb63b09206
upgrade some entries, remove stuff that is done.
...
llvm-svn: 47109
2008-02-14 06:19:02 +00:00
Chris Lattner
5bc0957f5b
the mid-level optimizer removes this stuff.
...
llvm-svn: 47108
2008-02-14 05:43:18 +00:00
Chris Lattner
b43983b274
this one is easy.
...
llvm-svn: 47107
2008-02-14 05:41:38 +00:00
Chris Lattner
3bd37f549a
This readme entry is done, testcase here: CodeGen/X86/zero-remat.ll
...
llvm-svn: 47106
2008-02-14 05:39:46 +00:00
Dan Gohman
9ca025f1dc
Assigning an APInt to 0 with plain assignment gives it a one-bit
...
size. Initialize these APInts to properly-sized zero values.
llvm-svn: 47099
2008-02-13 23:07:24 +00:00
Dan Gohman
e1d9ee66ed
Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits
...
to pass the mask APInt by value, not by reference.
llvm-svn: 47096
2008-02-13 22:28:48 +00:00
Nicolas Geoffray
21ad494f67
Enable exception handling int JIT
...
llvm-svn: 47079
2008-02-13 18:39:37 +00:00
Chris Lattner
d973e836f1
Fix the PPC JIT regressions by encoding zeroreg as 0 for BLR.
...
llvm-svn: 47067
2008-02-13 17:24:14 +00:00
Chris Lattner
f6518cf4ab
don't try to avoid inserting loads when lowering FORMAL_ARGUMENTS.
...
DAGCombine is now quite good at zapifying them.
llvm-svn: 47053
2008-02-13 07:35:30 +00:00
Nate Begeman
eea32990a9
readme updates
...
llvm-svn: 47051
2008-02-13 07:06:12 +00:00
Nate Begeman
87abe955fc
Make register scavenging happy by not using a reg (CR0) that isn't defined
...
llvm-svn: 47045
2008-02-13 02:58:33 +00:00
Evan Cheng
244183ef0d
commuteInstr() can now commute non-ssa machine instrs.
...
llvm-svn: 47043
2008-02-13 02:46:49 +00:00
Dan Gohman
f990faf23b
Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.
...
Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.
llvm-svn: 47039
2008-02-13 00:35:47 +00:00
Dale Johannesen
ffde4ff5b1
__DATA not __DATA__ is the right segment name on darwin.
...
Spotted by Nick Kledzik.
llvm-svn: 47037
2008-02-12 23:35:09 +00:00
Nate Begeman
bcc182f50d
Remove some dead code
...
llvm-svn: 47036
2008-02-12 22:54:40 +00:00
Nate Begeman
8ef50214f0
SSE4.1 64b integer insert/extract pattern support
...
Move formats into the formats file
llvm-svn: 47035
2008-02-12 22:51:28 +00:00
Evan Cheng
83af1197ca
Revert r46916 PPCTargetAsmInfo.cpp.
...
llvm-svn: 47020
2008-02-12 19:25:12 +00:00
Evan Cheng
8a25d6ac53
Only using x86-64 rip relative addressing in non-staic mode?
...
llvm-svn: 47019
2008-02-12 19:20:46 +00:00
Evan Cheng
352acec37e
Update comment.
...
llvm-svn: 47002
2008-02-12 07:59:55 +00:00
Evan Cheng
4d8c98b8f9
Unbreak various insert_vector_elt and extract_vector_elt tests in presence of SSE4.
...
llvm-svn: 47001
2008-02-12 07:59:45 +00:00
Nate Begeman
fd82c308e5
Stuff noticed while grepping code
...
llvm-svn: 46979
2008-02-11 23:47:56 +00:00
Nate Begeman
2d77e8e446
Enable SSE4 codegen and pattern matching.
...
Add some notes to the README.
llvm-svn: 46949
2008-02-11 04:19:36 +00:00