e28372c0d6
Fix (mem) <-> low 64-bits of xmm bugs pointed out by David Greene. Mac OS X Leopard assembler recognizes movq.
...
llvm-svn: 45040
2007-12-14 19:54:07 +00:00
f7cefdd5f0
x86-32 long doubles are 4-byte aligned on the stack
...
for parameter passing (only for that, on Darwin).
llvm-svn: 45038
2007-12-14 19:25:34 +00:00
a56e6ff9a7
Fix bsf / bsr jit encoding.
...
llvm-svn: 45037
2007-12-14 18:49:43 +00:00
f28c810036
Oops. Forgot these.
...
llvm-svn: 45036
2007-12-14 18:25:34 +00:00
9d2e9e376f
Fix Intel asm syntax for the bsr and bsf instructions.
...
llvm-svn: 45030
2007-12-14 15:10:00 +00:00
0e6408124e
Fix ctlz and cttz. llvm definition requires them to return number of bits in of the src type when value is zero.
...
llvm-svn: 45029
2007-12-14 08:30:15 +00:00
e9fbc3f014
Implement ctlz and cttz with bsr and bsf.
...
llvm-svn: 45024
2007-12-14 02:13:44 +00:00
827d30db19
Fold some and + shift in x86 addressing mode.
...
llvm-svn: 44970
2007-12-13 00:43:27 +00:00
6e68381e02
Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.
...
llvm-svn: 44960
2007-12-12 23:12:09 +00:00
7a7742c2fe
Allow vector integer constants to be created with
...
SelectionDAG::getConstant, in the same way as vector floating-point
constants. This allows the legalize expansion code for @llvm.ctpop and
friends to be usable with vector types.
llvm-svn: 44954
2007-12-12 22:21:26 +00:00
0f42730722
Use shuffles to implement insert_vector_elt for i32, i64, f32, and f64.
...
llvm-svn: 44929
2007-12-12 07:55:34 +00:00
2a98956796
Lower a build_vector with all constants into a constpool load unless it can be done with a move to low part.
...
llvm-svn: 44921
2007-12-12 06:45:40 +00:00
4a8bc7e105
Correct typo for Linux: s/esp/%rsp/
...
llvm-svn: 44904
2007-12-12 02:38:28 +00:00
6dc8b4ed13
Allow the JIT to encode MMX instructions
...
llvm-svn: 44869
2007-12-11 18:06:14 +00:00
4fbf459549
- Improved v8i16 shuffle lowering. It now uses pshuflw and pshufhw as much as
...
possible before resorting to pextrw and pinsrw.
- Better codegen for v4i32 shuffles masquerading as v8i16 or v16i8 shuffles.
- Improves (i16 extract_vector_element 0) codegen by recognizing
(i32 extract_vector_element 0) does not require a pextrw.
llvm-svn: 44836
2007-12-11 01:46:18 +00:00
a55a67ae91
x86 doesn't actually want to custom lower v3i32
...
llvm-svn: 44835
2007-12-11 01:41:33 +00:00
21ade5880b
Hey, English is not my native language :)
...
llvm-svn: 44820
2007-12-10 23:10:20 +00:00
77eb5e649d
Clarify the need of CFI() stuff
...
llvm-svn: 44819
2007-12-10 23:08:35 +00:00
a6b0f7e244
Provide convenient way to disable CFI stuff for old/broken assemblers.
...
Use it for Darwin.
llvm-svn: 44818
2007-12-10 23:04:38 +00:00
8a72a7d586
Disable cfi directives for now, darwin does't support them.
...
These should probably be something like:
CFI(".cfi_def_cfa_offset 16\n")
where CFI is defined to a noop on darwin and other platforms
that don't support those directives.
llvm-svn: 44803
2007-12-10 19:10:18 +00:00
657be86229
And finally annotate X86-64 version of callback.
...
All bad stuff from SSE version is implicitely inherited :)
llvm-svn: 44794
2007-12-10 15:27:07 +00:00
88e9d082d8
Provide annotation for SSE version of callback. It's even more
...
broken, because doesn't mark xmm regs properly
llvm-svn: 44793
2007-12-10 15:13:55 +00:00
81e9dc4af7
Annotate JIT callback function with call frame infromation.
...
This will allow us (theoretically) to unwind through JITer.
The code wasn't verified, so I'm pretty sure offsets are wrong :)
llvm-svn: 44792
2007-12-10 14:54:42 +00:00
3f19dfe794
Reverting 44702. It wasn't correct to rename them.
...
llvm-svn: 44727
2007-12-08 23:58:46 +00:00
ff87f05e43
aesthetic changes, no functionality change. Evan, it's not clear
...
what 'Available' is, please add a comment near it and rename it
if appropriate.
llvm-svn: 44703
2007-12-08 07:22:58 +00:00
2b07d8c5a0
Renaming:
...
isTriviallyReMaterializable -> hasNoSideEffects
isReallyTriviallyReMaterializable -> isTriviallyReMaterializable
llvm-svn: 44702
2007-12-08 07:17:56 +00:00
b41d838d28
Add comment.
...
llvm-svn: 44686
2007-12-07 21:30:01 +00:00
bfd373a53e
Much improved v8i16 shuffles. (Step 1).
...
llvm-svn: 44676
2007-12-07 08:07:39 +00:00
c829e5cdf0
Remove a bogus optimization. It's not possible to do a move to low element to a <8 x i16> or <16 x i8> vector.
...
llvm-svn: 44669
2007-12-06 22:14:22 +00:00
ad05e17491
add a note
...
llvm-svn: 44637
2007-12-05 22:58:19 +00:00
bb26301864
Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether
...
the stored register is killed.
llvm-svn: 44600
2007-12-05 03:14:33 +00:00
f45a1d623c
Remove redundant foldMemoryOperand variants and other code clean up.
...
llvm-svn: 44517
2007-12-02 08:30:39 +00:00
69fda0a716
Allow some reloads to be folded in multi-use cases. Specifically testl r, r -> cmpl [mem], 0.
...
llvm-svn: 44479
2007-12-01 02:07:52 +00:00
6f026a654c
Support returning non-power-of-2 vectors to unblock some work
...
llvm-svn: 44371
2007-11-27 19:28:48 +00:00
ad0ea2d430
Fix PR1146: parameter attributes are longer part of
...
the function type, instead they belong to functions
and function calls. This is an updated and slightly
corrected version of Reid Spencer's original patch.
The only known problem is that auto-upgrading of
bitcode files doesn't seem to work properly (see
test/Bitcode/AutoUpgradeIntrinsics.ll). Hopefully
a bitcode guru (who might that be? :) ) will fix it.
llvm-svn: 44359
2007-11-27 13:23:08 +00:00
5728bdd4db
Fix a long standing deficiency in the X86 backend: we would
...
sometimes emit "zero" and "all one" vectors multiple times,
for example:
_test2:
pcmpeqd %mm0, %mm0
movq %mm0, _M1
pcmpeqd %mm0, %mm0
movq %mm0, _M2
ret
instead of:
_test2:
pcmpeqd %mm0, %mm0
movq %mm0, _M1
movq %mm0, _M2
ret
This patch fixes this by always arranging for zero/one vectors
to be defined as v4i32 or v2i32 (SSE/MMX) instead of letting them be
any random type. This ensures they get trivially CSE'd on the dag.
This fix is also important for LegalizeDAGTypes, as it gets unhappy
when the x86 backend wants BUILD_VECTOR(i64 0) to be legal even when
'i64' isn't legal.
This patch makes the following changes:
1) X86TargetLowering::LowerBUILD_VECTOR now lowers 0/1 vectors into
their canonical types.
2) The now-dead patterns are removed from the SSE/MMX .td files.
3) All the patterns in the .td file that referred to immAllOnesV or
immAllZerosV in the wrong form now use *_bc to match them with a
bitcast wrapped around them.
4) X86DAGToDAGISel::SelectScalarSSELoad is generalized to handle
bitcast'd zero vectors, which simplifies the code actually.
5) getShuffleVectorZeroOrUndef is updated to generate a shuffle that
is legal, instead of generating one that is illegal and expecting
a later legalize pass to clean it up.
6) isZeroShuffle is generalized to handle bitcast of zeros.
7) several other minor tweaks.
This patch is definite goodness, but has the potential to cause random
code quality regressions. Please be on the lookout for these and let
me know if they happen.
llvm-svn: 44310
2007-11-25 00:24:49 +00:00
f72ad16263
remove bogus assertion that broke CodeGen/Generic/cast-fp.ll on x86
...
among others.
llvm-svn: 44302
2007-11-24 18:37:20 +00:00
f81d5886c6
Several changes:
...
1) Change the interface to TargetLowering::ExpandOperationResult to
take and return entire NODES that need a result expanded, not just
the value. This allows us to handle things like READCYCLECOUNTER,
which returns two values.
2) Implement (extremely limited) support in LegalizeDAG::ExpandOp for MERGE_VALUES.
3) Reimplement custom lowering in LegalizeDAGTypes in terms of the new
ExpandOperationResult. This makes the result simpler and fully
general.
4) Implement (fully general) expand support for MERGE_VALUES in LegalizeDAGTypes.
5) Implement ExpandOperationResult support for ARM f64->i64 bitconvert and ARM
i64 shifts, allowing them to work with LegalizeDAGTypes.
6) Implement ExpandOperationResult support for X86 READCYCLECOUNTER and FP_TO_SINT,
allowing them to work with LegalizeDAGTypes.
LegalizeDAGTypes now passes several more X86 codegen tests when enabled and when
type legalization in LegalizeDAG is ifdef'd out.
llvm-svn: 44300
2007-11-24 07:07:01 +00:00
ab98c41337
add a note
...
llvm-svn: 44299
2007-11-24 06:13:33 +00:00
763e110a9f
Fix .eh table linkage issues on Darwin. Some EH support
...
for Darwin PPC, but it's not fully working yet.
llvm-svn: 44258
2007-11-20 23:24:42 +00:00
d4d45c268c
Add support for vectors to int <-> float casts.
...
llvm-svn: 44204
2007-11-17 03:58:34 +00:00
91460e43f1
Implement codegen for flt_rounds on x86
...
llvm-svn: 44183
2007-11-16 01:31:51 +00:00
0cbe920d7c
Oops. Debugging code shouldn't have been checked in.
...
llvm-svn: 44128
2007-11-14 19:08:32 +00:00
2c6387803e
Fix PIC jump table codegen on x86-32/linux. In fact, such thing should be applied
...
to all targets uses GOT-relative offsets for PIC (Alpha?)
llvm-svn: 44108
2007-11-14 09:18:41 +00:00
e2287ed552
Eliminate the recently introduced CCAssignToStackABISizeAlign
...
in favour of teaching CCAssignToStack that size 0 and/or align
0 means to use the ABI values. This seems a neater solution.
It is safe since no legal value type has size 0.
llvm-svn: 44107
2007-11-14 08:29:13 +00:00
7f02cfa599
Clean up sub-register implementation by moving subReg information back to
...
MachineOperand auxInfo. Previous clunky implementation uses an external map
to track sub-register uses. That works because register allocator uses
a new virtual register for each spilled use. With interval splitting (coming
soon), we may have multiple uses of the same register some of which are
of using different sub-registers from others. It's too fragile to constantly
update the information.
llvm-svn: 44104
2007-11-14 07:59:08 +00:00
7904708369
Revert previous; these files aren't ready to go in yet.
...
llvm-svn: 44057
2007-11-13 19:16:02 +00:00
7a7085f6d3
Add parameter to getDwarfRegNum to permit targets
...
to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.
llvm-svn: 44056
2007-11-13 19:13:01 +00:00
c891ae92dc
Fix x86-64 jit: remove reliance on Dwarf numbers.
...
llvm-svn: 44048
2007-11-13 17:54:34 +00:00
77b13af9a6
Unifacalize the CALLSEQ{START,END} stuff.
...
llvm-svn: 44045
2007-11-13 09:19:02 +00:00
f359fed9f9
Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
...
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).
This can only result in tears...
llvm-svn: 44037
2007-11-13 00:44:25 +00:00
933b5b7e62
Add a flag for indirect branch instructions.
...
Target maintainers: please check that the instructions for your target are correctly marked.
llvm-svn: 44012
2007-11-12 07:39:39 +00:00
4edfea438a
Use TableGen to emit information for dwarf register numbers.
...
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,
llvm-svn: 43997
2007-11-11 19:50:10 +00:00
b988e7e8cd
Add CCAssignToStackABISizeAlign for convenience in
...
dealing with types whose size & alignment are
different on different subtargets. Use it for x86 f80.
llvm-svn: 43988
2007-11-10 22:07:15 +00:00
d2c16ff905
Update tailcall code to include inline attribute operand for memcpy.
...
llvm-svn: 43978
2007-11-10 10:48:01 +00:00
fb13fd6f93
Unbreak x86-64 jumptable.
...
llvm-svn: 43955
2007-11-09 19:11:23 +00:00
dfb85c7831
Revert previous rewrite per chris's comments.
...
llvm-svn: 43950
2007-11-09 18:07:11 +00:00
797d56ff17
Much improved pic jumptable codegen:
...
Then:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
imull $4, %ecx, %ecx
leal LJTI1_0-"L1$pb"(%eax), %edx
addl LJTI1_0-"L1$pb"(%ecx,%eax), %edx
jmpl *%edx
.align 2
.set L1_0_set_3,LBB1_3-LJTI1_0
.set L1_0_set_2,LBB1_2-LJTI1_0
.set L1_0_set_5,LBB1_5-LJTI1_0
.set L1_0_set_4,LBB1_4-LJTI1_0
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
Now:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
addl LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax
jmpl *%eax
.align 2
.set L1_0_set_3,LBB1_3-"L1$pb"
.set L1_0_set_2,LBB1_2-"L1$pb"
.set L1_0_set_5,LBB1_5-"L1$pb"
.set L1_0_set_4,LBB1_4-"L1$pb"
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
llvm-svn: 43924
2007-11-09 01:32:10 +00:00
04fd82088e
Rewrite Dwarf number handling per review comments.
...
llvm-svn: 43918
2007-11-09 00:47:10 +00:00
1b9de4dd6f
Complete conditionalization of Dwarf reg numbers.
...
Would somebody not on Darwin please make sure this
doesn't break anything. Exception handling failures
would be the most likely symptom.
llvm-svn: 43844
2007-11-07 21:48:35 +00:00
fbe69d2cd6
Interchange Dwarf numbers of ESP and EBP on x86 Darwin.
...
Much improvement in exception handling.
llvm-svn: 43794
2007-11-07 00:25:05 +00:00
fa0df55bdd
Move the LowerMEMCPY and LowerMEMCPYCall to a common place.
...
Thanks for the suggestions Bill :-)
llvm-svn: 43742
2007-11-05 23:12:20 +00:00
9337929aae
Use movups to spill / restore SSE registers on targets where stacks alignment is
...
less than 16. This is a temporary solution until dynamic stack alignment is
implemented.
llvm-svn: 43703
2007-11-05 07:30:01 +00:00
283207a71c
Eliminate the remaining uses of getTypeSize. This
...
should only effect x86 when using long double. Now
12/16 bytes are output for long double globals (the
exact amount depends on the alignment). This brings
globals in line with the rest of LLVM: the space
reserved for an object is now always the ABI size.
One tricky point is that only 10 bytes should be
output for long double if it is a field in a packed
struct, which is the reason for the additional
argument to EmitGlobalConstant.
llvm-svn: 43688
2007-11-05 00:04:43 +00:00
9329e780cd
Fix PR1761 by not printing (rip) suffix when in -static mode.
...
Evan, please review this.
llvm-svn: 43680
2007-11-04 19:23:28 +00:00
296160d443
Fix PR1763 by allowing the 'q' constraint to work with 64-bit
...
regs on x86-64.
llvm-svn: 43669
2007-11-04 06:51:12 +00:00
2b93a20b09
Unbreak tailcall opt.
...
llvm-svn: 43646
2007-11-02 17:45:40 +00:00
389d430c49
add a note
...
llvm-svn: 43642
2007-11-02 17:04:20 +00:00
e453ff4913
Missing a getNumOperands check.
...
llvm-svn: 43630
2007-11-02 01:26:22 +00:00
b7cabbe295
Silence, accersed warning
...
llvm-svn: 43609
2007-11-01 08:51:44 +00:00
419b6d7ce4
Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into getMaxInlineSizeThreshold
...
and by restructuring the X86 version.
New I just have to move this to a common place :-)
llvm-svn: 43554
2007-10-31 14:39:58 +00:00
063f177300
Make ARM an X86 memcpy expansion more similar to each other.
...
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.
This should not change generated code.
llvm-svn: 43552
2007-10-31 11:52:06 +00:00
b066c1f216
Make i64=expand_vector_elt(v2i64) work in 32-bit mode.
...
llvm-svn: 43535
2007-10-31 00:32:36 +00:00
d50c8bcef6
Add missing SSE builtins: CVTPD2PI, CVTPS2PI,
...
CVTTPD2PI, CVTTPS2PI, CVTPI2PD, CVTPI2PS.
llvm-svn: 43523
2007-10-30 22:15:38 +00:00
b508c53c63
Fix for visibility warnings generated by gcc-4.2.
...
llvm-svn: 43500
2007-10-30 13:14:37 +00:00
6aa304e529
Add missing MMX PSUBQ.
...
llvm-svn: 43488
2007-10-30 01:18:38 +00:00
e106e2f142
Enable more fold (sext (load x)) -> (sext (truncate (sextload x)))
...
transformation. Previously, it's restricted by ensuring the number of load uses
is one. Now the restriction is loosened up by allowing setcc uses to be
"extended" (e.g. setcc x, c, eq -> setcc sext(x), sext(c), eq).
llvm-svn: 43465
2007-10-29 19:58:20 +00:00
7b3f7feaea
Avoid doing something dumb like rewriting using a 64-bit iv in 32-bit mode.
...
llvm-svn: 43446
2007-10-29 07:57:50 +00:00
909a54ccd4
add a note.
...
llvm-svn: 43444
2007-10-29 06:19:48 +00:00
5e99fd8c0d
Add support for the x86-64 'q' regigster modifier, and add support for the
...
b/h/w/k/q inline asm memory modifiers, which are just ignored. This fixes
PR1748 and CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll
llvm-svn: 43430
2007-10-29 03:09:07 +00:00
c826ac533b
New entry.
...
llvm-svn: 43420
2007-10-28 04:01:09 +00:00
d07d6a411c
Fix off-by-one stack offset computations (dwarf information) for callee-saved
...
registers in case, when FP pointer was eliminated. This should fixes misc. random
EH-related crahses, when stuff is compiled with -fomit-frame-pointer.
Thanks Duncan for nailing this bug!
llvm-svn: 43381
2007-10-26 09:13:24 +00:00
7f3d02471d
Loosen up iv reuse to allow reuse of the same stride but a larger type when truncating from the larger type to smaller type is free.
...
e.g.
Turns this loop:
LBB1_1: # entry.bb_crit_edge
xorl %ecx, %ecx
xorw %dx, %dx
movw %dx, %si
LBB1_2: # bb
movl L_X$non_lazy_ptr, %edi
movw %si, (%edi)
movl L_Y$non_lazy_ptr, %edi
movw %dx, (%edi)
addw $4, %dx
incw %si
incl %ecx
cmpl %eax, %ecx
jne LBB1_2 # bb
into
LBB1_1: # entry.bb_crit_edge
xorl %ecx, %ecx
xorw %dx, %dx
LBB1_2: # bb
movl L_X$non_lazy_ptr, %esi
movw %cx, (%esi)
movl L_Y$non_lazy_ptr, %esi
movw %dx, (%esi)
addw $4, %dx
incl %ecx
cmpl %eax, %ecx
jne LBB1_2 # bb
llvm-svn: 43375
2007-10-26 01:56:11 +00:00
bf474959a3
Fix the folding of multiplication into addresses on x86, which was broken
...
by the recent {U,S}MUL_LOHI changes.
llvm-svn: 43230
2007-10-22 20:22:24 +00:00
c92446af1f
Fix an unfolding bug.
...
llvm-svn: 43212
2007-10-22 03:03:20 +00:00
8ee70112ea
Allow for copysign having f80 second argument.
...
Fixes 5550319.
llvm-svn: 43205
2007-10-21 01:07:44 +00:00
45e096c77e
Resolve unfold tables ambiguity.
...
llvm-svn: 43194
2007-10-19 23:50:58 +00:00
35ff79370b
Local spiller optimization:
...
Turn a store folding instruction into a load folding instruction. e.g.
xorl %edi, %eax
movl %eax, -32(%ebp)
movl -36(%ebp), %eax
orl %eax, -32(%ebp)
=>
xorl %edi, %eax
orl -36(%ebp), %eax
mov %eax, -32(%ebp)
This enables the unfolding optimization for a subsequent instruction which will
also eliminate the newly introduced store instruction.
llvm-svn: 43192
2007-10-19 21:23:22 +00:00
846c19dd70
Add support for byval function whose argument is not 32 bit aligned.
...
To do this it is necessary to add a "always inline" argument to the
memcpy node. For completeness I have also added this node to memmove
and memset. I have also added getMem* functions, because the extra
argument makes it cumbersome to use getNode and because I get confused
by it :-)
llvm-svn: 43172
2007-10-19 10:41:11 +00:00
463e2ab0ac
- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding.
...
- Fix some copy+paste bugs.
llvm-svn: 43153
2007-10-18 22:40:57 +00:00
aa9a225699
Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface.
...
llvm-svn: 43150
2007-10-18 21:29:24 +00:00
7f68cf0d57
Fix a typo
...
llvm-svn: 43144
2007-10-18 19:28:55 +00:00
12d5da49d3
Change fp to sint legalization on x86-32 to do 2 x i32
...
loads instead of 1 x i64 loads. This doesn't change any functionality yet.
llvm-svn: 43068
2007-10-17 06:17:29 +00:00
693cbeadff
fix some funny indentation, add comments.
...
llvm-svn: 43066
2007-10-17 06:02:13 +00:00
e5530a35d4
Check for invalid cc's in f80 select.
...
llvm-svn: 43033
2007-10-16 18:09:08 +00:00
b3d58b98d0
Correction to tail call optimization code. The new return address
...
was stored to the acutal stack slot before the parameters were
lowered to their stack slot. This could cause arguments to be
overwritten by the return address if the called function had less
parameters than the caller function. The update should remove the
last failing test case of llc-beta: SPASS.
llvm-svn: 43027
2007-10-16 09:05:00 +00:00
7bcfd8f880
LowerFP_TO_SINT must not create a stack object if it's not needed.
...
llvm-svn: 43004
2007-10-15 20:11:21 +00:00
4099f4f91a
Unbreak x86-64.
...
llvm-svn: 42962
2007-10-14 10:09:39 +00:00
cdf3609130
Revert 42908 for now.
...
llvm-svn: 42960
2007-10-14 05:57:21 +00:00
29af26f147
Clarify that fastcc has a problem with nested function
...
trampolines, rather than with nested functions themselves.
llvm-svn: 42955
2007-10-13 07:38:37 +00:00
7082dcf605
Change unfoldMemoryOperand(). User is now responsible for passing in the
...
register used by the unfolded instructions. User can also specify whether to
unfold the load, the store, or both.
llvm-svn: 42946
2007-10-13 02:35:06 +00:00
e8d0bf2669
Correcting the corrections. Bad bad baaad emacs!
...
llvm-svn: 42935
2007-10-12 21:53:12 +00:00
1f0da1fefb
Corrected many typing errors. And removed 'nest' parameter handling
...
for fastcc from X86CallingConv.td. This means that nested functions
are not supported for calling convention 'fastcc'.
llvm-svn: 42934
2007-10-12 21:30:57 +00:00
a6286bd502
Due to the new tail call optimization, trampolines can no
...
longer be created for fastcc functions.
llvm-svn: 42925
2007-10-12 19:37:31 +00:00
409fa443fc
Update.
...
llvm-svn: 42922
2007-10-12 18:22:55 +00:00
dc35bd79ca
Change the names used for internal labels to use the current
...
function symbol name instead of a codegen-assigned function
number.
Thanks Evan! :-)
llvm-svn: 42908
2007-10-12 14:53:36 +00:00
8d978da3b0
Mark vector ctpop, cttz, and ctlz as Expand on x86.
...
llvm-svn: 42905
2007-10-12 14:09:42 +00:00
09c0fe0a7f
Fold load / store into MOV32to32_ and MOV16to16_.
...
llvm-svn: 42895
2007-10-12 08:38:01 +00:00
f8c23f074b
Flag MOV32to32_ with EXTRACT_SUBREG. They should not be scheduled apart.
...
llvm-svn: 42894
2007-10-12 07:55:53 +00:00
482732af9d
Set ISD::FPOW to Expand.
...
llvm-svn: 42881
2007-10-11 23:21:31 +00:00
62f65edc32
Add missing argument to PALIGNR
...
llvm-svn: 42874
2007-10-11 20:58:37 +00:00
9ccea99165
Added tail call optimization to the x86 back end. It can be
...
enabled by passing -tailcallopt to llc. The optimization is
performed if the following conditions are satisfied:
* caller/callee are fastcc
* elf/pic is disabled OR
elf/pic enabled + callee is in module + callee has
visibility protected or hidden
llvm-svn: 42870
2007-10-11 19:40:01 +00:00
e8c8ef5234
LowerIntegerDivOrRem no longer exists.
...
llvm-svn: 42787
2007-10-09 15:45:13 +00:00
51554bf30e
Fix grammar in a comment.
...
llvm-svn: 42786
2007-10-09 15:44:37 +00:00
6d28778bfd
This is done.
...
llvm-svn: 42785
2007-10-09 15:42:21 +00:00
82bc90ac60
Under 64-bit mode use LEA64_32r instead of LEA64r to save a byte.
...
llvm-svn: 42783
2007-10-09 07:14:53 +00:00
f5ec10b64c
Bug fix. X86 was emitting redundant setcc and test instructions before a conditional move.
...
llvm-svn: 42774
2007-10-08 22:16:29 +00:00
a160361c85
Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
...
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.
llvm-svn: 42762
2007-10-08 18:33:35 +00:00
18109c88c3
Allow x86 compare to be commutable by default.
...
llvm-svn: 42761
2007-10-08 18:27:46 +00:00
b20757d578
disable this entirely: it is causing use of invalidated iterators and infinite looping.
...
llvm-svn: 42739
2007-10-07 22:00:31 +00:00
8dd66ab3b2
Fix many regressions on x86 by avoiding dereferencing the end iterator.
...
llvm-svn: 42738
2007-10-07 21:53:12 +00:00
67ac2de8bf
Oops, I really wanted to commit this part also :)
...
llvm-svn: 42700
2007-10-06 16:39:43 +00:00
c59496f737
Move merge code into new helper function.
...
llvm-svn: 42699
2007-10-06 16:17:49 +00:00
f4b5d491df
Added DAG xforms. e.g.
...
(vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr)
(vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
Remove x86 specific patterns.
llvm-svn: 42677
2007-10-06 02:46:29 +00:00
1151ffde70
Commute x86 cmove instructions by swapping the operands and change the condition
...
to its inverse.
Testing this as llcbeta
llvm-svn: 42661
2007-10-05 23:13:21 +00:00
42a13757de
This is done.
...
llvm-svn: 42656
2007-10-05 22:34:59 +00:00
484cab7a2f
Enable convertToThreeAddress for X86 by default.
...
llvm-svn: 42655
2007-10-05 22:31:10 +00:00
d3ccf00870
INC64_32r -> LEA64_32r is better than INC64_32r -> LEA32r, but it still can
...
cause performance degradation.
llvm-svn: 42653
2007-10-05 21:55:32 +00:00
fa2c828687
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g.
...
leal 1(%ecx), %edi, which requires 67H prefix.
llvm-svn: 42647
2007-10-05 20:34:26 +00:00
aac0f8e351
Add support to convert more 64-bit instructions to 3-address instructions.
...
llvm-svn: 42642
2007-10-05 18:20:36 +00:00
97eba74a52
ADC and SBB uses EFLAGS.
...
llvm-svn: 42640
2007-10-05 17:59:57 +00:00
43c29dce18
Change a few more spaces to tabs in assembly output.
...
llvm-svn: 42638
2007-10-05 15:58:41 +00:00
b074f23dff
Change a space to a tab in the assembly output of a .globl directive
...
for consistency.
llvm-svn: 42637
2007-10-05 15:54:58 +00:00
a8a9c15e30
Testing convertToThreeeAddress as X86 llcbeta.
...
llvm-svn: 42630
2007-10-05 08:04:01 +00:00
a851e2b92e
Added storeRegToAddr, loadRegFromAddr, and unfoldMemoryOperand's.
...
llvm-svn: 42624
2007-10-05 01:34:55 +00:00
6912b50958
Not needed any more.
...
llvm-svn: 42623
2007-10-05 01:34:14 +00:00
1f2b5f0e13
add a note.
...
llvm-svn: 42607
2007-10-04 15:47:27 +00:00
c731c97fac
Use empty() member functions when that's what's being tested for instead
...
of comparing begin() and end().
llvm-svn: 42585
2007-10-03 19:26:29 +00:00
4bdb84fe53
add a note
...
llvm-svn: 42579
2007-10-03 17:10:03 +00:00
21ba176c4b
Bill's example is still not enough to repro this, but it has other issues that
...
seem significant as well.
llvm-svn: 42564
2007-10-03 03:40:24 +00:00
3efc0758ae
Another micro-opt.
...
llvm-svn: 42554
2007-10-02 21:49:31 +00:00
f214ff8701
Another missed optimization with LICM.
...
llvm-svn: 42552
2007-10-02 21:43:06 +00:00
855011e5c6
Small label changes.
...
llvm-svn: 42549
2007-10-02 21:02:53 +00:00
4eb7ca4b4c
Now with source code.
...
llvm-svn: 42548
2007-10-02 21:01:16 +00:00
96ed3bb2d4
Now with LL code!
...
llvm-svn: 42547
2007-10-02 20:54:32 +00:00
9c4d61b523
Another missed optimization.
...
llvm-svn: 42546
2007-10-02 20:42:59 +00:00
88ea107fdb
Micro-optimization -- missed LICM opportunity.
...
llvm-svn: 42542
2007-10-02 19:55:05 +00:00
1f79ba6fe6
Refactor code to add load / store folded instructions -> register only
...
instructions reverse map.
llvm-svn: 42509
2007-10-01 23:44:33 +00:00
a1b7e95039
Typo. X86comi doesn't read / write chain's.
...
llvm-svn: 42492
2007-10-01 18:12:48 +00:00
0b7cf862bc
AsmPrinters overriding getAnalysisUsage should call super.
...
And not super's super, either.
llvm-svn: 42482
2007-09-30 13:39:29 +00:00
5fb5a1f389
Enabling new condition code modeling scheme.
...
llvm-svn: 42459
2007-09-29 00:00:36 +00:00
6c04ac1db0
Refactor the memcpy lowering for the x86 target.
...
The only generated code difference is that now we call memcpy when
the size of the array is unknown. This matches GCC behavior and is
better since the run time value can be arbitrarily large.
llvm-svn: 42433
2007-09-28 12:53:01 +00:00
1f516560d1
Stop inventing new words. :-)
...
llvm-svn: 42429
2007-09-28 01:35:02 +00:00
edfc5b2204
Pessimisively assume ADJCALLSTACKDOWN / ADJCALLSTACKUP (which becomes sub / add) clobbers EFLAGS.
...
llvm-svn: 42426
2007-09-28 01:19:48 +00:00
a1d46c7d0a
TargetAsmInfo::getAddressSize() was incorrect for x86-64 and 64-bit targets
...
other than PPC64. Instead of fixing it, just remove it and fix all the
places that use it to use TargetData::getPointerSize() instead, as there
aren't very many. Most of the references were in DwarfWriter.cpp.
llvm-svn: 42419
2007-09-27 23:12:31 +00:00
99dc695da5
Use GR64 in 64-bit mode.
...
llvm-svn: 42417
2007-09-27 21:50:05 +00:00
5a71402be6
Doh. Calls clobber EFLAGS.
...
llvm-svn: 42413
2007-09-27 19:01:55 +00:00
8728c3376a
- Added MRegisterInfo::getCrossCopyRegClass() hook. For register classes where reg to reg copies are not possible, this returns another register class which registers in the specified register class can be copied to (and copy back from).
...
- X86 copyRegToReg() now supports copying between EFLAGS and GR32 / GR64 registers.
llvm-svn: 42372
2007-09-26 21:31:07 +00:00
b93de587cb
Some assemblers do not recognize aliases pushfd, pushfq, popfd, and popfq. Just emit them as pushf and popf.
...
llvm-svn: 42371
2007-09-26 21:28:00 +00:00
b6d56401aa
Enable codegen for long double abs, sin, cos
...
llvm-svn: 42368
2007-09-26 21:10:55 +00:00
b4b352656a
Typos: POPQ -> POPFQ, POPD -> POPFD.
...
llvm-svn: 42348
2007-09-26 06:38:29 +00:00
c9e7b8ec50
move PR1160 here.
...
llvm-svn: 42347
2007-09-26 06:29:31 +00:00
c1e4e3743b
Allow copyRegToReg to emit cross register classes copies.
...
Tested with "make check"!
llvm-svn: 42346
2007-09-26 06:25:56 +00:00
fef69f5b4a
move PR1264 here.
...
llvm-svn: 42345
2007-09-26 06:15:48 +00:00
0a6f47cff9
Add pushf{d|q}, popf{d|q} to push and pop EFLAGS register.
...
llvm-svn: 42335
2007-09-26 01:29:06 +00:00
9b7f0e6eb4
translateX86CC updates the last two operands.
...
llvm-svn: 42333
2007-09-26 00:45:55 +00:00
e291f727e3
Correctly restore stack pointer after realignment in main() on Cygwin/Mingw32
...
llvm-svn: 42332
2007-09-26 00:13:34 +00:00
5321fa44f4
Missing load / store folding entries.
...
llvm-svn: 42323
2007-09-25 22:10:43 +00:00
90910745bb
Partly revert invalid r41774
...
llvm-svn: 42322
2007-09-25 21:52:30 +00:00
57211c5550
More explicit keywords.
...
llvm-svn: 42316
2007-09-25 20:27:06 +00:00
06919e8ef2
Fix a typo in a comment.
...
llvm-svn: 42313
2007-09-25 19:37:26 +00:00
8ee1ecfc50
New style x87 cmp instructions.
...
llvm-svn: 42312
2007-09-25 19:08:02 +00:00
31599685c7
When both x/y and x%y are needed (x and y both scalar integer), compute
...
both results with a single div or idiv instruction. This uses new X86ISD
nodes for DIV and IDIV which are introduced during the legalize phase
so that the SelectionDAG's CSE can automatically eliminate redundant
computations.
llvm-svn: 42308
2007-09-25 18:23:27 +00:00
5e1a428344
Move the setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand) and
...
the check to see if the assembler supports .loc from X86TargetLowering
into the superclass TargetLowering.
llvm-svn: 42297
2007-09-25 15:10:49 +00:00
e95f391ef1
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after
...
all the kinks are worked out.
llvm-svn: 42285
2007-09-25 01:57:46 +00:00
0241bb57b2
When mixing SSE and x87 codegen, it's possible to
...
have situations where an SSE instruction turns into
multiple blocks, with the live range of an x87
register crossing them. To do this correctly make
sure we examine all blocks when inserting
FP_REG_KILL. PR 1697. (This was exposed by my
fix for PR 1681, but the same thing could happen
mixing x87 long double with SSE.)
llvm-svn: 42281
2007-09-24 22:52:39 +00:00
1b2156fcae
Add support on x86 for having Legalize lower ISD::LOCATION to ISD::DEBUG_LOC
...
instead of ISD::LABEL with a manual .debug_line entry when the assembler
supports .file and .loc directives.
llvm-svn: 42278
2007-09-24 21:54:14 +00:00
071efe28bb
Fix the syntax for the .loc directive in preparation for using it.
...
llvm-svn: 42268
2007-09-24 19:25:06 +00:00
82dcfd2dab
The code that used the StartLabelId label was removed, so remove the
...
code that creates the label too.
llvm-svn: 42265
2007-09-24 16:44:26 +00:00
5b5484db63
claim that "st" is from the 80-bit register file. This causes x87-using inline
...
asm to die with:
ScheduleDAG.cpp:269: failed assertion `false && "Couldn't find the register class"'
instead of:
failed assertion `RegMap->getRegClass(VReg) == RC && "Register class of operand and regclass of use don't agree!"'
yay.
llvm-svn: 42259
2007-09-24 05:27:37 +00:00
e36c400255
Fix PR 1681. When X86 target uses +sse -sse2,
...
keep f32 in SSE registers and f64 in x87. This
is effectively a new codegen mode.
Change addLegalFPImmediate to permit float and
double variants to do different things.
Adjust callers.
llvm-svn: 42246
2007-09-23 14:52:20 +00:00
4730c04904
Don't add a default STACK_ALIGN (use the generic ABI alignment)
...
Implement calls to functions with byval arguments on X86
llvm-svn: 42192
2007-09-21 15:50:22 +00:00
f065f0e2a1
small cleanup: use LowerMemArgument in LowerFastCCArguments also
...
llvm-svn: 42189
2007-09-21 14:55:38 +00:00
1ff71872c2
Honor user-defined section specification of a global, ignores whether its initializer is null.
...
llvm-svn: 42182
2007-09-21 00:41:19 +00:00
4dbc582a36
Fix several more entries in the x86 reload/remat folding tables.
...
llvm-svn: 42162
2007-09-20 14:17:21 +00:00
95be037d67
another long double buglet
...
llvm-svn: 42159
2007-09-20 01:27:54 +00:00
7d67e547b5
More long double fixes. x86_64 should build now.
...
llvm-svn: 42155
2007-09-19 23:55:34 +00:00
513874cf3c
PSHUFDmi, etc. are actually folding a load, not a store.
...
llvm-svn: 42147
2007-09-19 19:02:47 +00:00
17f589f76e
Set CCR (EFLAGS) copy cost to -1, i.e. extremely expensive to copy.
...
llvm-svn: 42124
2007-09-19 01:36:39 +00:00
8cca8469de
Move the entries for 64-bit CMP, IMUL, and a few others into the correct
...
tables so that they are eligible for reload/remat folding. And add
entries for JMP and CALL.
llvm-svn: 42094
2007-09-18 14:59:14 +00:00
ff7e443792
Remove RSTRegClass case from loadRegFromStackSlot
...
and storeRegToStackSlot. Evan and I concluded this
should never be needed and it appears to be true.
(It if is needed, adjustment would be needed for
long double to work.)
llvm-svn: 42049
2007-09-17 20:15:38 +00:00
8070099fef
X86ISD::TEST is dead.
...
llvm-svn: 42037
2007-09-17 17:42:53 +00:00
3243e10ef0
Add 64-bit jmp instructions to the list of instructions that
...
can terminate a block with no fall-through.
llvm-svn: 42029
2007-09-17 15:19:08 +00:00
96aee15d33
Use xorl instead of xorq to enter a zero into a 64-bit register.
...
llvm-svn: 42027
2007-09-17 14:55:08 +00:00
863bdc332d
Emit integer x<1 as x<=0, as comparisons with zero (now includeing
...
64-bit) can use test instead of cmp with an immediate.
llvm-svn: 42026
2007-09-17 14:49:27 +00:00
51d1929b9e
Use "test reg,reg" in place of "cmp reg,0" for 64-bit operands. This was
...
previously only done for 32-bit and smaller operands.
llvm-svn: 42024
2007-09-17 14:35:24 +00:00
327e1a386c
Follow-up to patch r41999. Make the conditional that emits the personality stub
...
match the conditional that turns on exception handling emittion in the asm
printer.
llvm-svn: 42008
2007-09-16 19:21:08 +00:00
e5615156cc
Only emit the personality function as a global value if the backend actually
...
supports it. This solves this error on the Darwin x86-64 platform:
$ cat testcase.ii
struct A {
A();
};
A *bork() {
return new A;
}
$ llvm-g++ -arch x86_64 -c testcase.ii
/var/tmp//cc3U8fd8.s:52:unknown section type: non_lazy_symbol_pointers
/var/tmp//cc3U8fd8.s:52:Rest of line ignored. 1st junk character valued 76 (L).
/var/tmp//cc3U8fd8.s:53:Unknown pseudo-op: .indirect_symbol
/var/tmp//cc3U8fd8.s:53:Rest of line ignored. 1st junk character valued 95 (_).
llvm-svn: 41999
2007-09-16 10:36:17 +00:00
48ea03d169
Add patterns for SHLD64* and SHRD64*.
...
llvm-svn: 41975
2007-09-14 23:17:45 +00:00
98d3a08d8f
Remove the assumption that FP's are either float or
...
double from some of the many places in the optimizers
it appears, and do something reasonable with x86
long double.
Make APInt::dump() public, remove newline, use it to
dump ConstantSDNode's.
Allow APFloats in FoldingSet.
Expand X86 backend handling of long doubles (conversions
to/from int, mostly).
llvm-svn: 41967
2007-09-14 22:26:36 +00:00
483e1ce16e
Add implicit def of EFLAGS on those instructions that may modify flags.
...
llvm-svn: 41962
2007-09-14 21:48:26 +00:00
9da02f5ee2
Remove isReg, isImm, and isMBB, and change all their users to use
...
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.
llvm-svn: 41958
2007-09-14 20:33:02 +00:00
272f7304f0
Add support for functions with byval arguments on x86
...
llvm-svn: 41953
2007-09-14 15:48:13 +00:00
3e18e504ae
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
...
llvm-svn: 41863
2007-09-11 19:55:27 +00:00
50b6730ae4
Added status flags register: EFLAGS.
...
llvm-svn: 41862
2007-09-11 19:53:28 +00:00
245dceb06d
Add APInt interfaces to APFloat (allows directly
...
access to bits). Use them in place of float and
double interfaces where appropriate.
First bits of x86 long double constants handling
(untested, probably does not work).
llvm-svn: 41858
2007-09-11 18:32:33 +00:00
74fb0f1a1c
Add a bool to indicate if we should set the "indirect encoding" bit in the Dwarf
...
information for EH.
llvm-svn: 41852
2007-09-11 17:20:55 +00:00
86e0119822
Fold the adjust_trampoline intrinsic into
...
init_trampoline. There is now only one
trampoline intrinsic.
llvm-svn: 41841
2007-09-11 14:10:23 +00:00
1a11e1c14f
My compiler warns about the semicolon.
...
llvm-svn: 41840
2007-09-11 12:30:25 +00:00
2b8fc31df9
The personality function on Darwin needs a global stub. We then refer to
...
that global stub instead of doing the ".set" thingy we were doing before.
llvm-svn: 41838
2007-09-11 08:27:17 +00:00
8c3c198499
New entry.
...
llvm-svn: 41810
2007-09-10 22:16:37 +00:00
6777b72659
Add some notes about better flag handling.
...
llvm-svn: 41808
2007-09-10 21:43:18 +00:00
637395e6bd
It's not safe to rematerialize MOV32r0 etc. by simply cloning the original
...
instruction. These are implemented with xor which will modify the conditional
code. They should be rematerialized as move instructions.
llvm-svn: 41802
2007-09-10 20:48:53 +00:00
cef2c0efcc
TableGen no longer emit CopyFromReg nodes for implicit results in physical
...
registers. The scheduler is now responsible for emitting them.
llvm-svn: 41781
2007-09-07 23:59:02 +00:00
a95cbb0007
Avoid storing and reloading zeros and other constants from stack slots
...
by flagging the associated instructions as being trivially rematerializable.
llvm-svn: 41775
2007-09-07 21:32:51 +00:00
9e70086c8f
Apply feedback from previous patch.
...
llvm-svn: 41774
2007-09-07 21:07:57 +00:00
1de0c86717
Add support for having different alignment for objects on call frames.
...
The x86-64 ABI states that objects passed on the stack have
8 byte alignment. Implement that.
llvm-svn: 41768
2007-09-07 14:52:14 +00:00
e2f23a3abf
Add lengthof and endof templates that hide a lot of sizeof computations.
...
Patch by Sterling Stein!
llvm-svn: 41758
2007-09-07 04:06:50 +00:00
bed9dc423c
Next round of APFloat changes.
...
Use APFloat in UpgradeParser and AsmParser.
Change all references to ConstantFP to use the
APFloat interface rather than double. Remove
the ConstantFP double interfaces.
Use APFloat functions for constant folding arithmetic
and comparisons.
(There are still way too many places APFloat is
just a wrapper around host float/double, but we're
getting there.)
llvm-svn: 41747
2007-09-06 18:13:44 +00:00
189df733ed
Fix a bug in X86InstrInfo::convertToThreeAddress that caused it to codegen:
...
leal (,%rcx,8), %rcx
It should be
leal (,%rcx,8), %ecx
llvm-svn: 41735
2007-09-06 00:14:41 +00:00
623dd88775
Mac OS X X86-64 ABI is same as the standard.
...
llvm-svn: 41700
2007-09-04 16:44:41 +00:00
50ab26e835
Reapply r41578 with proper fix
...
llvm-svn: 41680
2007-09-03 00:36:06 +00:00
e636fc05d6
Initial support for calling functions with byval arguments on x86-64
...
llvm-svn: 41643
2007-08-31 15:06:30 +00:00
bb8a5cff67
Align i64 and f64 at 8 byte on x86-64.
...
This is mandated table 3.1 at
http://www.x86-64.org/documentation/abi.pdf
llvm-svn: 41642
2007-08-31 12:23:58 +00:00
3cf889f75e
Enhance APFloat to retain bits of NaNs (fixes oggenc).
...
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.
llvm-svn: 41632
2007-08-31 04:03:46 +00:00
ebb8540067
Added support to fold X86 load / store instructions. This allow rematerialized loads to be folded into their uses.
...
llvm-svn: 41599
2007-08-30 05:54:07 +00:00
c2081fe573
Mark load instructions with isLoad = 1.
...
llvm-svn: 41595
2007-08-30 05:49:43 +00:00
d246b2ca5c
Change LegalFPImmediates to use APFloat.
...
Add APFloat interfaces to ConstantFP, SelectionDAG.
Fix integer bit in double->APFloat conversion.
Convert LegalizeDAG to use APFloat interface in
ConstantFPSDNode uses.
llvm-svn: 41587
2007-08-30 00:23:21 +00:00
7741427a09
Move getX86RegNum into X86RegisterInfo and use it
...
in the trampoline lowering. Lookup the jump and
mov opcodes for the trampoline rather than hard
coding them.
llvm-svn: 41577
2007-08-29 19:01:20 +00:00
b602461f48
Add a comment about using libc memset/memcpy or generating inline code.
...
llvm-svn: 41502
2007-08-27 17:48:26 +00:00
ff33241e16
call libc memcpy/memset if array size is bigger then threshold.
...
Coping 100MB array (after a warmup) shows that glibc 2.6.1 implementation on
x86-64 (core 2) is 30% faster (from 0.270917s to 0.188079s)
llvm-svn: 41479
2007-08-27 10:18:20 +00:00
d8c9cb9182
rename isOperandValidForConstraint to LowerAsmOperandForConstraint,
...
changing the interface to allow for future changes.
llvm-svn: 41384
2007-08-25 00:47:38 +00:00
51883acec1
add a note
...
llvm-svn: 41359
2007-08-24 15:17:59 +00:00
33800d1428
add some notes on really poor codegen.
...
llvm-svn: 41319
2007-08-23 15:22:07 +00:00
862afea91e
Add the PCSymbol for Darwin x86 platforms.
...
llvm-svn: 41284
2007-08-22 18:44:05 +00:00
f335679b52
Use only 1 knob to enable exceptions on Darwin :).
...
llvm-svn: 41208
2007-08-21 00:31:30 +00:00
9c3d20d823
Partial implementation of calling functions with byval arguments:
...
*) The needed information is propagated to the DAG
*) The X86-64 backend detects it and aborts
llvm-svn: 41179
2007-08-20 15:18:24 +00:00
78846b69ae
add a note
...
llvm-svn: 41178
2007-08-20 02:14:33 +00:00
597c8b77e4
Move ReturnAddrIndex variable to X86MachineFunctionInfo structure. This fixed
...
hard to catch bugs with retaddr lowering
llvm-svn: 41104
2007-08-15 17:12:32 +00:00
db8adb9941
add a note.
...
llvm-svn: 41103
2007-08-15 16:58:38 +00:00
b2823dac69
Fix a typo pointd out by Maarten ter Huurne.
...
llvm-svn: 41059
2007-08-13 23:27:11 +00:00
ccb3611881
When x86 addresses matching exceeds its recursion limit, check to
...
see if the base register is already occupied before assuming it can be
used. This fixes bogus code generation in the accompanying testcase.
llvm-svn: 41049
2007-08-13 20:03:06 +00:00
4e7f673f65
Fix PR1607
...
llvm-svn: 41048
2007-08-13 18:42:37 +00:00
750b3dfcf5
expand a note
...
llvm-svn: 41021
2007-08-11 18:19:07 +00:00
ee44ab5b5f
With evan's explicit flag representation, hopefully we will finally be
...
able to 3-addressify away stuff like this:
movl %ecx, %eax
decl %eax
llvm-svn: 41020
2007-08-11 18:16:46 +00:00
cdbd82ee37
64-bit SSSE3 ops that use MMX registers don't require 16-byte alignment.
...
Make a 'memop' pattern just for them.
llvm-svn: 41017
2007-08-11 09:52:53 +00:00
44e79f8aba
Use subregs to improve any_extend code generation when feasible.
...
llvm-svn: 41013
2007-08-10 22:22:41 +00:00
b372abab14
Increase efficiency of sign_extend_inreg by using subregisters for truncation. As the README suggests sign_extend_subreg is selected to (sext(trunc)).
...
llvm-svn: 41010
2007-08-10 21:48:46 +00:00
f0c236fb8a
Edit README in light of previous LEA16 commit.
...
llvm-svn: 41009
2007-08-10 21:29:05 +00:00
d36d30b53c
Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled.
...
llvm-svn: 41007
2007-08-10 21:18:25 +00:00
66011c17d5
propagate struct size and alignment of byval arguments to the DAG
...
llvm-svn: 40986
2007-08-10 14:44:42 +00:00
7014615087
For kicks, I though it would be fun to use the correct opcode.
...
llvm-svn: 40985
2007-08-10 09:00:17 +00:00
2377206923
Adding SSSE3 intrinsics.
...
llvm-svn: 40982
2007-08-10 06:22:27 +00:00
f855b626e8
Temporarily backing out this change until we know why some dejagnu tests are failing.
...
llvm-svn: 40973
2007-08-09 22:25:35 +00:00
e32e923a6a
divb / mulb outputs to ah. Under x86-64 it's not legal to read ah if the instruction requires a rex prefix (i.e. outputs to r8b, etc.). So issue shift right by 8 on AX and then truncate it to 8 bits instead.
...
llvm-svn: 40972
2007-08-09 21:59:35 +00:00
a05ec4dc52
GR16_ sub-register class should be GR8_, not GR8. That is, it should only be 8-bit registers in 32-bit mode. Ditto for GR32_.
...
llvm-svn: 40970
2007-08-09 18:05:17 +00:00
ba1a98a4e0
long double 9 of N. This finishes up the X86-32 bits
...
(constants are still not handled). Adds ConvertActions
to control fp-to-fp conversions (these are currently
defaulted for all other targets, so no changes there).
llvm-svn: 40958
2007-08-09 01:04:01 +00:00
a47f7d7cfd
Long double patch 8 of N: make it partially work in
...
SSE mode (all but conversions <-> other FP types, I think):
>>Do not mark all-80-bit operations as "Requires[FPStack]"
(which really means "not SSE").
>>Refactor load-and-extend to facilitate this.
>>Update comments.
>>Handle long double in SSE when computing FP_REG_KILL.
llvm-svn: 40906
2007-08-07 20:29:26 +00:00
57c6ac5fe5
Long double patch 7 of N, unless I lost count:).
...
Last x87 bits for full functionality (not
thoroughly tested, and long doubles do not work
in SSE modes at all - use -mcpu=i486 for now)
llvm-svn: 40886
2007-08-07 01:17:37 +00:00
a010822b45
Replace 4-line function with 10-line version per review comment.
...
llvm-svn: 40881
2007-08-06 22:10:35 +00:00
d1822ea7d1
Move lengthy conditional down 1 level per review comment.
...
llvm-svn: 40878
2007-08-06 21:48:35 +00:00
75169a82d6
Get X86 long double calling convention to work
...
(on Darwin, anyway). Fix some table omissions for
LD arithmetic.
llvm-svn: 40877
2007-08-06 21:31:06 +00:00
e279fd6ce8
Make 80-bit store maintain simulated FP stack correctly.
...
llvm-svn: 40868
2007-08-06 19:50:32 +00:00
b1888e73ad
Long double patch 4 of N: initial x87 implementation.
...
Lots of problems yet but some simple things work.
llvm-svn: 40847
2007-08-05 18:49:15 +00:00
7132e00de7
This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future.
...
This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.
llvm-svn: 40807
2007-08-04 01:51:18 +00:00
b0c7585f2d
Make x86 long double alignment 32 for everything but
...
Darwin (which makes size within a struct==96)
llvm-svn: 40796
2007-08-03 22:46:15 +00:00
c5283ecd6f
long double patch 2 of N. Handle it in TargetData.
...
(I've tried to get the info right for all targets,
but I'm not expert on all of them - check yours.)
llvm-svn: 40792
2007-08-03 20:20:50 +00:00
99fbf13dc3
add an observation
...
llvm-svn: 40772
2007-08-03 00:17:42 +00:00
5f6a9da530
More explicit keywords.
...
llvm-svn: 40757
2007-08-02 21:21:54 +00:00
8932bff7fe
Fix the alignment requirements of several unpck and shuf instructions.
...
Generalize isPSHUFDMask and add a unary SHUFPD pattern so that SHUFPD's
memory operand alignment can be tested as well, with a fix to avoid
breaking MMX's use of isPSHUFDMask.
llvm-svn: 40756
2007-08-02 21:17:01 +00:00
4d436e2b7d
Fix pastos in vector arithmetic intrinsics.
...
llvm-svn: 40754
2007-08-02 21:06:40 +00:00
fa3eeeedc0
Mark the SSE and MMX load instructions that
...
X86InstrInfo::isReallyTriviallyReMaterializable knows how to handle
with the isReMaterializable flag so that it is given a chance to handle
them. Without hoisting constant-pool loads from loops this isn't very
visible, though it does keep CodeGen/X86/constant-pool-remat-0.ll from
making a copy of the constant pool on the stack.
llvm-svn: 40736
2007-08-02 14:27:55 +00:00
473c5111c3
Switch some multiplication instructions over to the new scheme for testing.
...
llvm-svn: 40723
2007-08-02 05:48:35 +00:00
d3d92890fc
Can't handle offset and scale if rip-relative addressing is to be used.
...
llvm-svn: 40703
2007-08-01 23:46:47 +00:00
9a3b2b09ad
Mac OS X X86-64 low 4G address not available.
...
llvm-svn: 40702
2007-08-01 23:46:10 +00:00
763cdfd371
Mac OS X X86-64 low 4G address not available.
...
llvm-svn: 40701
2007-08-01 23:45:51 +00:00
da549ece5c
Missing Requires.
...
llvm-svn: 40691
2007-08-01 21:42:24 +00:00
6f2ce6b842
Be more precise.
...
llvm-svn: 40689
2007-08-01 20:22:37 +00:00
d541c831c3
Change a .size directive to use a tab instead of a space, for consistency.
...
llvm-svn: 40672
2007-08-01 14:42:30 +00:00
54ec4bfa5f
Change the x86 assembly output to use tab characters to separate the
...
mnemonics from their operands instead of single spaces. This makes the
assembly output a little more consistent with various other compilers
(f.e. GCC), and slightly easier to read. Also, update the regression
tests accordingly.
llvm-svn: 40648
2007-07-31 20:11:57 +00:00
12c6be84ff
Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load )
...
llvm-svn: 40628
2007-07-31 08:04:03 +00:00
242a87734a
This isn't safe when there are uses of load's chain result.
...
llvm-svn: 40617
2007-07-31 06:21:44 +00:00
204dece054
Use tabs more consistently in assembler pseudo-ops.
...
llvm-svn: 40594
2007-07-30 15:08:02 +00:00
5fecb80efa
Change the x86 backend to use extract_subreg for truncation operations. Passes DejaGnu, SingleSource and MultiSource.
...
llvm-svn: 40578
2007-07-29 01:24:57 +00:00
ac3a364c51
Add register info needed to use subreg sets on X86.
...
llvm-svn: 40572
2007-07-28 19:03:30 +00:00
ce38853cc6
Trampoline codegen support for X86-32.
...
llvm-svn: 40566
2007-07-27 20:02:49 +00:00
4788552deb
Re-apply 40504, but with a fix for the segfault it caused in oggenc:
...
Make the alignedload and alignedstore patterns always require 16-byte
alignment. This way when they are used in the "Fs" instructions, in which
a vector instruction is used for a scalar purpose, they can still require
the full vector alignment. And add a regression test for this.
llvm-svn: 40555
2007-07-27 17:16:43 +00:00
931de40afa
Reverting 40504 for now. It's breaking oggenc.
...
llvm-svn: 40547
2007-07-27 01:37:47 +00:00
d204d08b97
Make sure epilogue esp adjustment is placed before any terminator and pop instructions.
...
llvm-svn: 40538
2007-07-26 17:45:41 +00:00
936d17aa1b
Don't pollute the meaning of isUnpredicatedTerminator.
...
llvm-svn: 40537
2007-07-26 17:32:14 +00:00
ca6e041903
Minor bug.
...
llvm-svn: 40535
2007-07-26 17:02:45 +00:00
c9edd977ea
In the .loc directive, print the fields as "debug" fields, so they
...
don't get decorated as if for immediate fields for instructions.
llvm-svn: 40529
2007-07-26 15:24:15 +00:00
cecd4b3793
Fix a whitespace difference between CMPSSrr and CMPSDrr.
...
llvm-svn: 40528
2007-07-26 15:11:50 +00:00
ce5185b181
Same goes for constantpool, etc.
...
llvm-svn: 40517
2007-07-26 07:35:15 +00:00
8455bd3fae
Remove X86ISD::LOAD_PACK and X86ISD::LOAD_UA and associated code from the
...
x86 target, replacing them with the new alignment attributes on memory
references.
llvm-svn: 40504
2007-07-26 00:31:09 +00:00
630c1f75b8
Mac OS X x86-64 lower 4G address is not available.
...
llvm-svn: 40502
2007-07-25 23:41:36 +00:00
952aa6988b
Mac OS X should use 0x90 to fill in gaps to satisfy function alignment requirements.
...
llvm-svn: 40501
2007-07-25 23:36:05 +00:00
5c6a31e9a0
Functions with LinkOnce and weak linkage still need to be aligned. Doh.
...
llvm-svn: 40499
2007-07-25 22:28:16 +00:00
cf0a5349de
Don't ignore the return value of AsmPrinter::doInitialization and
...
AsmPrinter::doFinalization.
llvm-svn: 40487
2007-07-25 19:33:14 +00:00
64b64ae591
Minor cleanup:
...
- Split EH and debug infiormation
- Make DwarfWriter more verbose in some cases
llvm-svn: 40481
2007-07-25 00:06:28 +00:00
f0bb12848f
Add const to CanBeFoldedBy, CheckAndMask, and CheckOrMask.
...
llvm-svn: 40480
2007-07-24 23:00:27 +00:00
f906c7286f
Use movaps to load a v4f32 build_vector of all-constant values into a
...
register instead of loading each element individually.
llvm-svn: 40478
2007-07-24 22:55:08 +00:00
0c46451d2b
Heal EH handling stuff by emitting correct offsets to callee-saved registers.
...
Pretty hackish, but code itself is dirty mess, so we won't make anything worse. :)
llvm-svn: 40472
2007-07-24 21:07:39 +00:00
b6a8ae20c7
Fix some uses of dyn_cast to be uses of cast.
...
llvm-svn: 40443
2007-07-23 20:24:29 +00:00
17f68f95d8
Delete the svn:executable property on these files, which aren't executable.
...
llvm-svn: 40441
2007-07-23 19:26:08 +00:00
3d88e9940a
Add missing SSE builtins:
...
__builtin_ia32_cvtss2si64
__builtin_ia32_cvttss2si64
__builtin_ia32_cvtsi642ss
__builtin_ia32_cvtsd2si64
__builtin_ia32_cvttsd2si64
__builtin_ia32_cvtsi642sd
llvm-svn: 40411
2007-07-23 03:07:27 +00:00
ac1591be42
No more noResults.
...
llvm-svn: 40132
2007-07-21 00:34:19 +00:00
9d5df0a5f6
Added -print-emitted-asm to print out JIT generated asm to cerr.
...
llvm-svn: 40123
2007-07-20 21:56:13 +00:00
8fefeffb37
Because we promote SSE logical ops and loads to v2i64, we often end up generate
...
code that cross integer / floating point domains (e.g. generate pxor / pand for
logical ops on floating point value, movdqa to load / store floating point SSE
values). Given that, it's better to use movaps instead of movdqa and movups
instead of movdqu. They have the same latency but the "aps" variants are one
byte shorter.
If the domain crossing problem is a real performance issue, then we will have to
fix it with dynamic programming based isel.
llvm-svn: 40076
2007-07-20 00:27:43 +00:00
64738536b3
Fix custom lowering of SSE FXOR.
...
llvm-svn: 40071
2007-07-19 23:36:01 +00:00
7ca3555bfa
Fix patterns so we isel the xorps, etc. for floating pt logical SSE ops. DAG combiner may fold away the (bit_convert (load)).
...
llvm-svn: 40070
2007-07-19 23:34:10 +00:00
94b5a80b93
Change instruction description to split OperandList into OutOperandList and
...
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
7b5b06805a
Only adjust esp around calls in presence of alloca.
...
llvm-svn: 40028
2007-07-19 00:42:05 +00:00
8941071ae1
Use MOV instead of LEA to restore ESP if callee-saved frame size is 0; if previous instruction updates esp, fold it in.
...
llvm-svn: 40018
2007-07-18 21:26:06 +00:00
776962a97a
Implement initial memory alignment awareness for SSE instructions. Vector loads
...
and stores that have a specified alignment of less than 16 bytes now use
instructions that support misaligned memory references.
llvm-svn: 40015
2007-07-18 20:23:34 +00:00
f314055706
New entry.
...
llvm-svn: 39998
2007-07-18 08:21:49 +00:00
97b5dc63d7
Fold prologue esp update when possible.
...
llvm-svn: 39984
2007-07-17 21:26:42 +00:00
b2bb4b4040
Make sure not to break eh_return.
...
llvm-svn: 39978
2007-07-17 18:40:47 +00:00
27ba94bf3b
Update.
...
llvm-svn: 39977
2007-07-17 18:39:45 +00:00
67e2e22e97
Missed the case where alloca is used but the stack size (not including callee-saved portion) is zero. Thanks Dan.
...
llvm-svn: 39974
2007-07-17 18:03:34 +00:00
9ae2eb43d8
Use push / pop for prologues and epilogues.
...
llvm-svn: 39967
2007-07-17 07:59:08 +00:00
383a324735
Long live the exception handling!
...
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
llvm-svn: 39855
2007-07-14 14:06:15 +00:00
bdc69595d9
another missed SSE optimization
...
llvm-svn: 39772
2007-07-12 06:31:38 +00:00
68471d263f
Fix fp_constant_op failure.
...
llvm-svn: 38514
2007-07-10 21:53:30 +00:00
23f631d87c
fix 80 columnn violations, increasing the world's
...
pedantic satisfaction level.
llvm-svn: 38512
2007-07-10 20:53:41 +00:00
f51bd666d9
add a note
...
llvm-svn: 38507
2007-07-10 20:03:50 +00:00
57111e7a60
Define non-intrinsic instructions for vector min, max, sqrt, rsqrt, and rcp,
...
in addition to the intrinsic forms. Add spill-folding entries for these new
instructions, and for the scalar min and max instrinsic instructions which
were missing. And add some preliminary ISelLowering code for using the new
non-intrinsic vector sqrt instruction, and fneg and fabs.
llvm-svn: 38478
2007-07-10 00:05:58 +00:00
517290ae52
The various "getModuleMatchQuality" implementations should return
...
zero if they see a target triple they don't understand.
llvm-svn: 38463
2007-07-09 17:25:29 +00:00
d771e05121
isUnpredicatedTerminator should treat conditional branches as unpredicated terminator.
...
llvm-svn: 37960
2007-07-06 23:22:03 +00:00
b567e3ffb0
Add the byval attribute
...
llvm-svn: 37940
2007-07-06 10:57:03 +00:00
de9c825859
Proper flag __alloca call
...
llvm-svn: 37923
2007-07-05 20:36:08 +00:00
e16561cd5d
Here is the bulk of the sanitizing.
...
Almost all occurrences of "bytecode" in the sources have been eliminated.
llvm-svn: 37913
2007-07-05 17:07:56 +00:00
3d7008cd49
Refactor X87 instructions. As a side effect, all
...
their names are changed.
llvm-svn: 37876
2007-07-04 21:07:47 +00:00
8590f920c7
Support generation of GR64 to MMX code in the JIT.
...
llvm-svn: 37866
2007-07-04 01:29:22 +00:00
3053244b27
Allow a GR64 to be moved into an MMX register via the "movd" instruction.
...
Still need to have JIT generate this code.
llvm-svn: 37863
2007-07-04 00:19:54 +00:00
c2a6089b8b
Some spacing fixes. Cosmetic.
...
llvm-svn: 37853
2007-07-03 17:07:33 +00:00
a2b3c175db
Fix for PR 1505 (and 1489). Rewrite X87 register
...
model to include f32 variants. Some factoring
improvments forthcoming.
llvm-svn: 37847
2007-07-03 00:53:03 +00:00
f9ae1c6001
Vector results may be returned in XMM0 and XMM1, not just XMM0. With
...
the recent lowering changes, this allows types like <4 x double> to
be returned, using two vector registers.
llvm-svn: 37844
2007-07-02 16:21:53 +00:00
2660cef6d7
Convert .cvsignore files
...
llvm-svn: 37801
2007-06-29 16:35:07 +00:00
444d3ca53d
No vector fneg.
...
llvm-svn: 37786
2007-06-29 00:18:15 +00:00
3bd318e298
Type of vector extract / insert index operand should be iPTR.
...
llvm-svn: 37784
2007-06-29 00:01:20 +00:00
1cbdcac409
Remove a redundant newline in the asm output for ELF .rodata sections.
...
llvm-svn: 37756
2007-06-27 15:09:47 +00:00
e8c1e428f2
Revert the earlier change that removed the M_REMATERIALIZABLE machine
...
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
a866514528
Generalize MVT::ValueType and associated functions to be able to represent
...
extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.
This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.
llvm-svn: 37719
2007-06-25 16:23:39 +00:00
2e84e3f7b7
Make minor adjustments to whitespace and comments to reduce differences
...
between SSE1 instructions and their respective SSE2 analogues.
llvm-svn: 37718
2007-06-25 15:44:19 +00:00
33209bd6b8
Fix loadv2i32 to be loadv4i32, though it isn't actually used anywhere yet.
...
llvm-svn: 37717
2007-06-25 15:19:03 +00:00
e33c4b739b
Say AT&T instead of Intel in the comments for AT&T support.
...
llvm-svn: 37716
2007-06-25 15:11:25 +00:00
309d3d51b3
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
...
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
llvm-svn: 37704
2007-06-22 14:59:07 +00:00
485531ea9b
Quote complex names for Darwin X86 and ARM.
...
llvm-svn: 37700
2007-06-22 00:54:56 +00:00
9e82064924
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
...
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
944200be45
If a function is vararg, never pass inreg arguments in registers. Thanks to
...
Anton for half of this patch.
llvm-svn: 37641
2007-06-19 00:13:10 +00:00
cea02ffd05
Look for VECTOR_SHUFFLE that's identity operation on either LHS or RHS. This can happen before DAGCombiner catches it.
...
llvm-svn: 37636
2007-06-19 00:02:56 +00:00
c98815ba32
Define the pushq instruction for x86-64.
...
llvm-svn: 37625
2007-06-18 14:12:56 +00:00
094a4e813a
Revert patch. It regresses:
...
define double @test2(i64 %A) {
%B = bitcast i64 %A to double
ret double %B
}
$ llvm-as < t.ll | llc -march=x86-64
before:
.align 4
.globl _test2
_test2:
movd %rdi, %xmm0
ret
after:
_test2:
subq $8, %rsp
movq %rdi, (%rsp)
movsd (%rsp), %xmm0
addq $8, %rsp
ret
llvm-svn: 37617
2007-06-16 23:57:15 +00:00
cd9673e565
Fix a failure to bit_convert from integer GPR to MMX register.
...
llvm-svn: 37611
2007-06-16 06:17:31 +00:00
5c4413120f
Rename MVT::getVectorBaseType to MVT::getVectorElementType.
...
llvm-svn: 37579
2007-06-14 22:58:02 +00:00
616627b002
Do not treat FP_REG_KILL as terminator in branch analysis (X86).
...
llvm-svn: 37578
2007-06-14 22:03:45 +00:00
4a4a8eb00e
Add a target hook to allow loads from constant pools to be rematerialized, and an
...
implementation for x86.
llvm-svn: 37576
2007-06-14 20:50:44 +00:00
3a8e2a8b2f
Eliminate some redundant newlines in asm output.
...
llvm-svn: 37574
2007-06-14 15:00:27 +00:00
c68554683d
Handle blocks with 2 unconditional branches in AnalyzeBranch.
...
llvm-svn: 37571
2007-06-13 17:59:52 +00:00
75372ad603
fix x86-64 mmx calling convention for real, which passes in integer gprs.
...
llvm-svn: 37534
2007-06-09 05:08:10 +00:00
a4a49e37ab
fix mmx handling bug
...
llvm-svn: 37533
2007-06-09 05:01:50 +00:00
5514bbef46
Add a utility routine to check for unpredicated terminator instruction.
...
llvm-svn: 37528
2007-06-08 21:59:56 +00:00
59ca6a846f
Misuse of hasExternalLinkage(), should be checking isDeclaration().
...
llvm-svn: 37419
2007-06-04 18:54:57 +00:00
703e0f8608
Add explicit qualification for namespace MVT members.
...
llvm-svn: 37320
2007-05-24 14:33:05 +00:00
3fb7fdfded
We only need to specify the most-implied feature for an architecture.
...
llvm-svn: 37275
2007-05-22 05:15:37 +00:00
fc94eb66d2
BlockHasNoFallThrough() now returns true if block ends with a return instruction.
...
llvm-svn: 37266
2007-05-21 18:44:17 +00:00
7ea2df6e2a
add a note
...
llvm-svn: 37239
2007-05-18 20:18:14 +00:00
eefa83e67b
Use MVT::FIRST_VECTOR_VALUETYPE and MVT::LAST_VECTOR_VALUETYPE.
...
llvm-svn: 37234
2007-05-18 18:44:07 +00:00
e20dd92792
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
...
llvm-svn: 37193
2007-05-18 00:18:17 +00:00
afa1cb6da3
Fix a bogus check that prevented folding VECTOR_SHUFFLE to UNDEF; add an optimization to fold VECTOR_SHUFFLE to a zero vector.
...
llvm-svn: 37173
2007-05-17 18:45:50 +00:00
632c3f01ed
Added missing patterns for UNPCKH* and PUNPCKH*.
...
llvm-svn: 37172
2007-05-17 18:44:37 +00:00
dade607f19
This is the correct fix for PR1427. This fixes mmx-shuffle.ll and doesn't
...
cause other regressions.
llvm-svn: 37160
2007-05-17 17:13:13 +00:00
1ad4618715
Revert patch for PR1427. It breaks almost all vector tests.
...
llvm-svn: 37159
2007-05-17 07:50:14 +00:00
13f4bf5c5e
add support for 128-bit integer add/sub
...
llvm-svn: 37154
2007-05-17 06:35:11 +00:00
6a5a46322f
Fix PR1427 and test/CodeGen/X86/mmx-shuffle.ll
...
llvm-svn: 37141
2007-05-17 03:29:42 +00:00
888653cdba
implement the missing maskmovq mmx intrinsic that akor hit.
...
llvm-svn: 37100
2007-05-16 06:08:17 +00:00
c8798d085c
fix subtle bugs in inline asm operand selection
...
llvm-svn: 37065
2007-05-15 01:28:08 +00:00
13da17843c
More DWARF-related things cleanup:
...
1. Fix PR1380
2. Apply Duncan's patch from PR1410
3. Insert workaround for "one personality function per module" as noted in PR1414
4. Emit correct debug frames for x86/linux. This partly fixes DebugInfo/2006-11-06-StackTrace.cpp: stack trace is
shown correctly, but arguments for function on top of stack are displayed incorrectly.
llvm-svn: 37015
2007-05-12 22:36:25 +00:00
623c738fe9
add some notes
...
llvm-svn: 36965
2007-05-10 00:08:04 +00:00
f985c492e1
3DNowA implies 3DNow. 64-bit implies SSE1, SSE2, and I assume MMX.
...
llvm-svn: 36860
2007-05-06 07:56:19 +00:00
4060c7ac63
Reference correct header
...
llvm-svn: 36834
2007-05-06 04:00:55 +00:00
be8f99ecbb
move CodeGen/X86/overlap-add.ll here.
...
llvm-svn: 36799
2007-05-05 22:10:24 +00:00
4db0090339
Emit sections/directives in the proper order. This fixes PR1376. Also,
...
some small cleanup was made.
llvm-svn: 36780
2007-05-05 09:04:50 +00:00
e6182267d7
Add an "implies" field to features. This indicates that, if the current
...
feature is set, then the features in the implied list should be set also.
The opposite is also enforced: if a feature in the implied list isn't set,
then the feature that owns that implies list shouldn't be set either.
llvm-svn: 36756
2007-05-04 20:38:40 +00:00
83df45a959
Fix two classes of bugs:
...
1. x86 backend rejected (&gv+c) for the 'i' constraint when in static mode.
2. the matcher didn't correctly reject and accept some global addresses.
the right predicate is GVRequiresExtraLoad, not "relomodel = pic".
llvm-svn: 36670
2007-05-03 16:52:29 +00:00
e27e6e6fa8
Sets the section names for fixed-size constants and use the mergeable
...
flag for ELF on x86 so that duplicate constants can be eliminated by
the linker. This matches what GCC does with its -fmerge-constants
option, which is enabled at most -O levels.
llvm-svn: 36666
2007-05-03 16:38:57 +00:00
8c78a0bff0
Drop 'const'
...
llvm-svn: 36662
2007-05-03 01:11:54 +00:00
b5ce7c5466
Non-algorithmic change. Moved definitions around into separate sections
...
for SSE1, SSE2, SSE3, and SSSE3.
llvm-svn: 36656
2007-05-02 23:11:52 +00:00
ba3b7ee030
Update.
...
llvm-svn: 36653
2007-05-02 21:42:20 +00:00
e95c6ad802
Use 'static const char' instead of 'static const int'.
...
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.
llvm-svn: 36652
2007-05-02 21:39:20 +00:00
f1dcf69fc3
Emit correct register move information in eh frames for X86. This allows Shootout-C++/except to pass on x86/linux
...
with non-llvm-compiled (e.g. "native") unwind runtime.
llvm-svn: 36647
2007-05-02 19:53:33 +00:00
073ad20459
Emit correct DWARF reg # for RA (return address) register
...
llvm-svn: 36646
2007-05-02 08:46:03 +00:00
b538f67b1a
Fix couple of bugs connected with eh info:
...
1. Correct output offsets on Linux
2. Fix "style" of personality function. It shouldn't be indirect.
llvm-svn: 36633
2007-05-01 22:23:12 +00:00
09f162ca6a
Do not use typeinfo to identify pass in pass manager.
...
llvm-svn: 36632
2007-05-01 21:15:47 +00:00
76c8c95466
Use correct PC symbol
...
llvm-svn: 36628
2007-05-01 10:19:31 +00:00
2ac2197a0f
Adjust correct EH-related sections
...
llvm-svn: 36627
2007-05-01 10:16:06 +00:00
5662b21db1
eliminateFrameIndex() change.
...
llvm-svn: 36626
2007-05-01 09:13:03 +00:00
39f3cffbe3
Implement protected visibility. This partly implements PR1363. Linker
...
should be taught to deal with protected symbols.
llvm-svn: 36565
2007-04-29 18:35:00 +00:00
a30eabdd6e
Fix PR1339 and CodeGen/X86/dollar-name.ll
...
llvm-svn: 36495
2007-04-26 21:07:05 +00:00
c8264ca457
Have MMX registers clobbered in x86-64 too.
...
llvm-svn: 36494
2007-04-26 21:06:48 +00:00
ce6e6db704
Fix for PR1348. If stack inc / dec amount is > 32-bits, issue a series of add / sub instructions.
...
llvm-svn: 36456
2007-04-26 01:09:28 +00:00
0ba174534c
Match MachineFunction::UsedPhysRegs changes.
...
llvm-svn: 36452
2007-04-25 22:13:27 +00:00
157d7ee7e5
Add SSSE3 as a feature of Core2. Add MMX registers to the list of registers
...
clobbered by a call.
llvm-svn: 36448
2007-04-25 21:31:48 +00:00
d20cd6658a
do the multiplication as signed, so that 2*-2 == -4 instead of 4294967292
...
when promoted to 64-bits
llvm-svn: 36442
2007-04-25 17:23:53 +00:00
a97b694c82
Implement aliases. This fixes PR1017 and it's dependent bugs. CFE part
...
will follow.
llvm-svn: 36435
2007-04-25 14:27:10 +00:00
8cd224e81c
Relex assertions to account for additional implicit def / use operands.
...
llvm-svn: 36430
2007-04-25 07:12:14 +00:00
b975bebec1
support for >4G stack frames
...
llvm-svn: 36425
2007-04-25 04:30:24 +00:00
1ef35a2721
support >4G stack frames
...
llvm-svn: 36423
2007-04-25 04:25:10 +00:00
a784d875be
Update.
...
llvm-svn: 36407
2007-04-24 21:20:03 +00:00
b3b6c35beb
Add the PADDQ to the list.
...
llvm-svn: 36406
2007-04-24 21:19:14 +00:00
5c7f25632e
Add the final MMX instructions. Correct a few wrong patterns.
...
llvm-svn: 36405
2007-04-24 21:18:37 +00:00
e2324ca17d
Remove some invalid instructions from this check.
...
llvm-svn: 36404
2007-04-24 21:17:46 +00:00
591eab8844
Support for the special case of a vector with the canonical form:
...
vector_shuffle v1, v2, <2, 6, 3, 7>
I.e.
vector_shuffle v, undef, <2, 2, 3, 3>
MMX only has a shuffle for v4i16 vectors. It needs to use the unpackh for
this type of operation.
llvm-svn: 36403
2007-04-24 21:16:55 +00:00
6db679a49a
X86 TLS: optimize the implementation of "local exec" model.
...
llvm-svn: 36359
2007-04-23 01:28:10 +00:00
efb8077ddd
X86 TLS: fix and optimize the implementation of "initial exec" model.
...
llvm-svn: 36355
2007-04-22 22:50:52 +00:00
4e91908f17
X86 TLS: Implement review feedback.
...
llvm-svn: 36318
2007-04-21 20:56:26 +00:00
5959f42498
Comment out usage of write() for now.
...
llvm-svn: 36287
2007-04-20 22:40:10 +00:00
2518889872
Implement "general dynamic", "initial exec" and "local exec" TLS models for
...
X86 32 bits.
llvm-svn: 36283
2007-04-20 21:38:10 +00:00
06a164c6bc
Specify sub-register relations. e.g. RAX: [EAX], EAX: [AX], AX: [AL,AH].
...
llvm-svn: 36279
2007-04-20 21:15:21 +00:00
6c673ac01c
Make Microsoft assembler and linker happy.
...
llvm-svn: 36265
2007-04-20 00:33:54 +00:00
29845cd40d
Fix the spelling of the prefetchnta instruction.
...
llvm-svn: 36256
2007-04-18 14:09:14 +00:00
9b91d98a30
Add comment
...
llvm-svn: 36213
2007-04-17 19:34:00 +00:00
ff0598de75
rename X86FunctionInfo to X86MachineFunctionInfo to match the header file
...
it is defined in.
llvm-svn: 36196
2007-04-17 17:21:52 +00:00
8b7aab009e
Implemented correct stack probing on mingw/cygwin for dynamic alloca's.
...
Also, fixed static case in presence of eax livin. This fixes PR331
PS: Why don't we still have push/pop instructions? :)
llvm-svn: 36195
2007-04-17 09:20:00 +00:00
62a8cbe594
SSE4 is apparently public now.
...
llvm-svn: 36185
2007-04-17 00:02:37 +00:00
6f3a548ff4
In the event that some really old non-Intel or -AMD CPU is encountered...
...
llvm-svn: 36177
2007-04-16 21:59:44 +00:00
da17029218
Before assuming that the original code didn't work for Athlon64, the person who
...
replaced it with a FIXME should have determined what did work. Then he would have
realized that the code was in fact correct, and would have avoided breaking it.
llvm-svn: 36173
2007-04-16 21:48:58 +00:00
fb80151c42
Removed tabs everywhere except autogenerated & external files. Add make
...
target for tabs checking.
llvm-svn: 36146
2007-04-16 18:10:23 +00:00
e275463e2f
add a note
...
llvm-svn: 36028
2007-04-14 23:06:09 +00:00
2805bce656
Fix mmx paddq, add support for the 'y' register class, though it isn't tested.
...
llvm-svn: 35940
2007-04-12 04:14:49 +00:00
a5fcd24746
Fix CodeGen/X86/2007-03-24-InlineAsmPModifier.ll
...
llvm-svn: 35926
2007-04-11 22:29:46 +00:00
a6aa0319f1
done
...
llvm-svn: 35884
2007-04-11 05:34:00 +00:00
f099841573
Add support for our first SSSE3 instruction "pmulhrsw".
...
llvm-svn: 35869
2007-04-10 22:10:25 +00:00
d4a9b92a13
new micro optzn
...
llvm-svn: 35867
2007-04-10 21:14:01 +00:00
808ac93f68
remove some dead hooks
...
llvm-svn: 35845
2007-04-09 23:31:19 +00:00
39f65335d5
remove some dead target hooks, subsumed by isLegalAddressingMode
...
llvm-svn: 35840
2007-04-09 22:27:04 +00:00
7451e4d6a1
move a bunch of register constraints from being handled by
...
getRegClassForInlineAsmConstraint to being handled by
getRegForInlineAsmConstraint. This allows us to let the llvm register allocator
allocate, which gives us better code. For example, X86/2007-01-29-InlineAsm-ir.ll
used to compile to:
_run_init_process:
subl $4, %esp
movl %ebx, (%esp)
xorl %ebx, %ebx
movl $11, %eax
movl %ebx, %ecx
movl %ebx, %edx
# InlineAsm Start
push %ebx ; movl %ebx,%ebx ; int $0x80 ; pop %ebx
# InlineAsm End
Now we get:
_run_init_process:
xorl %ecx, %ecx
movl $11, %eax
movl %ecx, %edx
# InlineAsm Start
push %ebx ; movl %ecx,%ebx ; int $0x80 ; pop %ebx
# InlineAsm End
llvm-svn: 35804
2007-04-09 05:49:22 +00:00
2b6b4eb471
implement support for CodeGen/X86/inline-asm-x-scalar.ll:test3 - i32/i64 values
...
used with x constraints.
llvm-svn: 35803
2007-04-09 05:31:48 +00:00
590ed5e5b7
implement CodeGen/X86/inline-asm-x-scalar.ll
...
llvm-svn: 35799
2007-04-09 05:11:28 +00:00
ac5b650a54
Adding more MMX instructions.
...
llvm-svn: 35638
2007-04-03 23:48:32 +00:00
f79fb5cad0
make a new missing features section
...
llvm-svn: 35637
2007-04-03 23:41:34 +00:00
2640b4a4ab
Updated
...
llvm-svn: 35634
2007-04-03 23:37:20 +00:00
652c7b2d73
Changed to new MMX_ recipes.
...
llvm-svn: 35617
2007-04-03 06:18:31 +00:00
e7b2a864f2
Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them.
...
llvm-svn: 35616
2007-04-03 06:00:37 +00:00
59a6fa7af6
fix breakage from last night, simplify code.
...
llvm-svn: 35560
2007-04-01 20:49:36 +00:00
a8cc1ebae1
Consistency with native compilers
...
llvm-svn: 35532
2007-03-31 13:11:52 +00:00
b72fcddd23
Fix comment.
...
llvm-svn: 35531
2007-03-31 09:36:12 +00:00
afddb2c6f8
Match GCC's MMX calling convention.
...
llvm-svn: 35523
2007-03-31 01:03:53 +00:00
1eb94d973a
implement the new addressing mode description hook.
...
llvm-svn: 35521
2007-03-30 23:15:24 +00:00
Evan Cheng