Commit Graph

3274 Commits

Author SHA1 Message Date
Evan Cheng 5e7ee0a002 Also LXCHG64 -> XCHG64rm.
llvm-svn: 49948
2008-04-19 02:05:42 +00:00
Evan Cheng 7f4240a47c xchg which references a memory operand does not need to lock prefix. Atomicity is guaranteed.
llvm-svn: 49946
2008-04-19 01:20:30 +00:00
Dan Gohman ad4071a9e1 Fix the handling of va_copy on x86-64. As of llvm-gcc r49920
llvm-gcc is now lowering va_copy on x86-64, so this completes
the fix for PR2230.

llvm-svn: 49922
2008-04-18 20:55:41 +00:00
Evan Cheng 00bd8d904a - Fix atomic operation JIT encoding.
- Remove unused instructions.

llvm-svn: 49921
2008-04-18 20:55:36 +00:00
Evan Cheng 5879213597 Also support Intel asm syntax.
llvm-svn: 49878
2008-04-17 23:35:10 +00:00
Evan Cheng 4704baa555 Fix assembly code for atomic operations.
llvm-svn: 49869
2008-04-17 21:26:35 +00:00
Evan Cheng 147cb764b5 Don't forget about sub-register indices when rematting instructions.
llvm-svn: 49830
2008-04-16 23:44:44 +00:00
Dale Johannesen c1279f5e4b Unbreak build on x86-64.
llvm-svn: 49822
2008-04-16 22:24:33 +00:00
Nicolas Geoffray a7557dfe71 Correlate stubs with functions in JIT: when emitting a stub, the JIT tells the memory manager which function
the stub will resolve.

llvm-svn: 49814
2008-04-16 20:46:05 +00:00
Nicolas Geoffray ae84bbdbed Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
llvm-svn: 49809
2008-04-16 20:10:13 +00:00
Evan Cheng a15cee1036 Initialize X863DNowLevel.
llvm-svn: 49808
2008-04-16 19:03:02 +00:00
Roman Levenstein a3ee1a38a3 Ongoing work on improving the instruction selection infrastructure:
Rename SDOperandImpl back to SDOperand.
Introduce the SDUse class that represents a use of the SDNode referred by
an SDOperand. Now it is more similar to Use/Value classes.

Patch is approved by Dan Gohman.

llvm-svn: 49795
2008-04-16 16:15:27 +00:00
Dan Gohman d43d3beeb0 Add support for the form of the SSE41 extractps instruction that
puts its result in a 32-bit GPR.

llvm-svn: 49762
2008-04-16 02:32:24 +00:00
Dan Gohman 8c99ccaf96 Recreate the size SDNode instead of reusing the old one in the x86
memcpy lowering code; this ensures that the size node has the desired
result type. This fixes a regression from r49572 with @llvm.memcpy.i64
on x86-32.

llvm-svn: 49761
2008-04-16 01:32:32 +00:00
Dan Gohman 3dd8ba6235 Remove X86_64SRet; it isn't used anymore.
llvm-svn: 49759
2008-04-16 00:24:30 +00:00
Dan Gohman 01a5d36d9d Add movd instructions to move from MMX registers
to 64-bit GPR registers on x86-64.

llvm-svn: 49757
2008-04-15 23:55:07 +00:00
Dan Gohman 2505d86783 Fix const-correctness issues with the SrcValue handling in the
memory intrinsic expansion code.

llvm-svn: 49666
2008-04-14 17:55:48 +00:00
Dale Johannesen 876224b1e8 Reverse sense of unwind-tables option. This means
stack tracebacks on Darwin x86-64 won't work by default;
nevertheless, everybody but me thinks this is a good idea.

llvm-svn: 49663
2008-04-14 17:54:17 +00:00
Anton Korobeynikov b9f38f38fa Provide option for stack alignment override
llvm-svn: 49593
2008-04-12 22:12:22 +00:00
Arnold Schwaighofer 634fc9a33a This patch corrects the handling of byval arguments for tailcall
optimized x86-64 (and x86) calls so that they work (... at least for
my test cases).

Should fix the following problems:

Problem 1: When i introduced the optimized handling of arguments for
tail called functions (using a sequence of copyto/copyfrom virtual
registers instead of always lowering to top of the stack) i did not
handle byval arguments correctly e.g they did not work at all :).

Problem 2: On x86-64 after the arguments of the tail called function
are moved to their registers (which include ESI/RSI etc), tail call
optimization performs byval lowering which causes xSI,xDI, xCX
registers to be overwritten. This is handled in this patch by moving
the arguments to virtual registers first and after the byval lowering
the arguments are moved from those virtual registers back to
RSI/RDI/RCX.

llvm-svn: 49584
2008-04-12 18:11:06 +00:00
Dan Gohman 544ab2c50b Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.

Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.

This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.

Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.

This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.

llvm-svn: 49572
2008-04-12 04:36:06 +00:00
Dan Gohman 8c7cf88f7e Fix a bug that prevented x86-64 from using rep.movsq for
8-byte-aligned data.

llvm-svn: 49571
2008-04-12 02:35:39 +00:00
Nate Begeman 7417348a7e 80 col fix
llvm-svn: 49569
2008-04-12 00:47:57 +00:00
Chris Lattner aeb23a8a34 add a note, this is actually not too bad to implement.
llvm-svn: 49466
2008-04-10 05:54:50 +00:00
Chris Lattner c692188075 move the x86-32 part of PR2108 here.
llvm-svn: 49465
2008-04-10 05:37:47 +00:00
Chris Lattner ad75302497 Fix the x86-64 side of PR2108 by adding a v2f64 version of
MOVZQI2PQIrr.  This would be better handled as a dag combine 
(with the goal of eliminating the bitconvert) but I don't know
how to do that safely.  Thoughts welcome.

llvm-svn: 49463
2008-04-10 05:13:43 +00:00
Dan Gohman 33b3300178 Make isVectorClearMaskLegal's operand list const.
llvm-svn: 49446
2008-04-09 20:09:42 +00:00
Dan Gohman 3d074a3125 Add XMM1 as a second return value register for f32 and f64 on x86-64. This
is needed for the x86-64-ABI handling of structs that contain floating-point
members that are returned by value.

llvm-svn: 49441
2008-04-09 17:54:37 +00:00
Dan Gohman cbf87313a2 Add DX as a second return value register for i16 on x86.
llvm-svn: 49440
2008-04-09 17:53:38 +00:00
Dale Johannesen fe767621ca Handle the situation in 2008-01-25-EmptyFunction.ll
correctly when unwind info is being generated.

llvm-svn: 49366
2008-04-08 00:37:56 +00:00
Dale Johannesen 344aec2952 Implement new llc flag -disable-required-unwind-tables.
Corresponds to -fno-unwind-tables (usually default in gcc).

llvm-svn: 49361
2008-04-08 00:10:24 +00:00
Dan Gohman 3bc3ddd638 Rename MemOperand to MachineMemOperand. This was suggested by
review feedback from Chris quite a while ago. No functionality
change.

llvm-svn: 49348
2008-04-07 19:35:22 +00:00
Roman Levenstein 51f532f92d Re-commit of the r48822, where the infinite looping problem discovered
by Dan Gohman is fixed.

llvm-svn: 49330
2008-04-07 10:06:32 +00:00
Gabor Greif e9ecc68d8f API changes for class Use size reduction, wave 1.
Specifically, introduction of XXX::Create methods
for Users that have a potentially variable number of
Uses.

llvm-svn: 49277
2008-04-06 20:25:17 +00:00
Evan Cheng f77b5ef3d0 Favors pshufd over shufps when shuffling elements from one vector. pshufd is faster than shufps.
llvm-svn: 49244
2008-04-05 00:30:36 +00:00
Evan Cheng 6c66bd368e Re-enable SSE4.
llvm-svn: 49158
2008-04-03 08:53:29 +00:00
Evan Cheng 6db4b4cc65 Fix x86-64 encoding bug. REX prefix must always follow 0x0F prefix. For example, extractps in 64bit mode: 66 REX 0F 3A 17, not 66 0F 3A REX 17.
llvm-svn: 49157
2008-04-03 08:53:17 +00:00
Evan Cheng d9129d1de3 Cosmetic
llvm-svn: 49156
2008-04-03 07:45:18 +00:00
Evan Cheng 3063c5546e Temporarily disabling SSE4 until we fix the encoding issues.
llvm-svn: 49129
2008-04-03 04:49:54 +00:00
Evan Cheng 025cea1126 Backing out 48222 temporarily.
llvm-svn: 49124
2008-04-03 03:13:16 +00:00
Dale Johannesen 8780ecbbac Cosmetic changes per EH patch review feedback.
llvm-svn: 49096
2008-04-02 17:04:45 +00:00
Anton Korobeynikov 20c9e4cbee Add new CC lowering rule: provide a list of registers, which can be 'shadowed',
when some another register is used for argument passing.
Currently is used on Win64.

llvm-svn: 49079
2008-04-02 05:23:57 +00:00
Dale Johannesen fd967cf3fa Recommitting EH patch; this should answer most of the
review feedback.
-enable-eh is still accepted but doesn't do anything.
EH intrinsics use Dwarf EH if the target supports that,
and are handled by LowerInvoke otherwise.
The separation of the EH table and frame move data is,
I think, logically figured out, but either one still
causes full EH info to be generated (not sure how to
split the metadata correctly).
MachineModuleInfo::needsFrameInfo is no longer used and
is removed.

llvm-svn: 49064
2008-04-02 00:25:04 +00:00
Evan Cheng b86595fb0a ReMat of load from stub in pic mode extends the life of pic base. Currently spiller doesn't do a good job of estimating the impact. Disable for now.
llvm-svn: 49059
2008-04-01 23:26:12 +00:00
Evan Cheng 19a6dd9f2a Remove unnecessary and non-deterministic checking code. Re-enable remat of load from gv stub.
llvm-svn: 49054
2008-04-01 21:38:20 +00:00
Dan Gohman cb9f8f6e4e Don't use __bzero for memset if the second argument isn't zero.
llvm-svn: 49050
2008-04-01 20:56:18 +00:00
Dan Gohman 980d7200c1 Speculatively micro-optimize memory-zeroing calls on Darwin 10.
llvm-svn: 49048
2008-04-01 20:38:36 +00:00
Dale Johannesen 5e4e051c2a Revert 49006 for the moment.
llvm-svn: 49046
2008-04-01 20:00:57 +00:00
Evan Cheng 306e3dcff4 Disabling remat of load from gv stub (temporarily) again to fix llvmgcc bootstrap miscompare.
llvm-svn: 49037
2008-04-01 07:33:13 +00:00
Dale Johannesen efa81a6979 Accept 'y' constraint (MMX) in inline asm.
llvm-svn: 49011
2008-04-01 00:57:48 +00:00