Commit Graph

101 Commits

Author SHA1 Message Date
Andrew Trick ef23569858 MISched: Cleanup, redundant statement.
llvm-svn: 170453
2012-12-18 20:52:58 +00:00
Andrew Trick d6d5ad3d7b MISched: Heuristics, compare latency more precisely. It matters more for some targets.
llvm-svn: 170452
2012-12-18 20:52:56 +00:00
Andrew Trick 44f54d97a4 MISched: Remove SchedRemainder::IsResourceLimited. I don't know how to compute it.
llvm-svn: 170451
2012-12-18 20:52:54 +00:00
Andrew Trick 493b867b5d MISched: cleanup, use the proper iterator type.
llvm-svn: 170450
2012-12-18 20:52:52 +00:00
Andrew Trick ffb6168e85 MISched: minor improvement, initialize remaining resources before the first scheduling decision.
llvm-svn: 170449
2012-12-18 20:52:49 +00:00
Chandler Carruth ed0881b2a6 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131
2012-12-03 16:50:05 +00:00
Andrew Trick b767d1eba8 misched: Fix RegisterPressureTracker handling of DebugVals.
Assertion failed: (TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker").
rdar://12790302.

llvm-svn: 169072
2012-12-01 01:22:49 +00:00
Andrew Trick e7ea8aa48a misched: fix RegionBegin when DebugValues get shuffled to the top.
assert (RemainingInstrs == 0 && "Instruction count mismatch!")

rdar://12776937.

llvm-svn: 169069
2012-12-01 01:22:38 +00:00
Benjamin Kramer aa598b3be6 misched: Recompute priority queue when DFSResults are updated.
This was found by MSVC10's STL debug mode on a test from the test suite. Sadly
std::is_heap isn't standard so there is no way to assert this without writing
our own heap verify, which looks like overkill to me.

llvm-svn: 168885
2012-11-29 14:36:26 +00:00
Andrew Trick 48d392e81e misched: Analysis that partitions the DAG into subtrees.
This is a simple, cheap infrastructure for analyzing the shape of a
DAG. It recognizes uniform DAGs that take the shape of bottom-up
subtrees, such as the included matrix multiplication example. This is
useful for heuristics that balance register pressure with ILP. Two
canonical expressions of the heuristic are implemented in scheduling
modes: -misched-ilpmin and -misched-ilpmax.

llvm-svn: 168773
2012-11-28 05:13:28 +00:00
Andrew Trick cd1c2f9fb1 misched: rename ScheduleDAGILP to ScheduleDFS to prepare for other heuristics.
llvm-svn: 168772
2012-11-28 05:13:24 +00:00
Andrew Trick cf7e6971e8 misched: Debug output fix. Use an always valid iterator.
llvm-svn: 168767
2012-11-28 03:42:47 +00:00
Andrew Trick 108c88c5b7 misched: Allow subtargets to enable misched and dependent options.
This allows me to begin enabling (or backing out) misched by default
for one subtarget at a time. To run misched we typically want to:
- Disable SelectionDAG scheduling (use the source order scheduler)
- Enable more aggressive coalescing (until we decide to always run the coalescer this way)
- Enable MachineScheduler pass itself.

Disabling PostRA sched may follow for some subtargets.

llvm-svn: 167826
2012-11-13 08:47:29 +00:00
Andrew Trick ec369d5316 misched: rename interfaceto avoid gcc warnings
llvm-svn: 167753
2012-11-12 21:28:10 +00:00
Andrew Trick 263280248a misched: Target-independent support for MacroFusion.
Uses the infrastructure from r167742 to support clustering instructure
that the target processor can "fuse". e.g. cmp+jmp.

Next step: target hook implementations with test cases, and enable.

llvm-svn: 167744
2012-11-12 19:52:20 +00:00
Andrew Trick a7714a0ff9 misched: Target-independent support for load/store clustering.
This infrastructure is generally useful for any target that wants to
strongly prefer two instructions to be adjacent after scheduling.

A following checkin will add target-specific hooks with unit
tests. Then this feature will be enabled by default with misched.

llvm-svn: 167742
2012-11-12 19:40:10 +00:00
Andrew Trick f1ff84c64e misched: Infrastructure for weak DAG edges.
This adds support for weak DAG edges to the general scheduling
infrastructure in preparation for MachineScheduler support for
heuristics based on weak edges.

llvm-svn: 167738
2012-11-12 19:28:57 +00:00
Benjamin Kramer c280f41864 Silence GCC warning about falling off the end of a non-void function.
llvm-svn: 167618
2012-11-09 15:45:22 +00:00
Andrew Trick 3ca33acb95 misched: Heuristics based on the machine model.
misched is disabled by default. With -enable-misched, these heuristics
balance the schedule to simultaneously avoid saturating processor
resources, expose ILP, and minimize register pressure. I've been
analyzing the performance of these heuristics on everything in the
llvm test suite in addition to a few other benchmarks. I would like
each heuristic check to be verified by a unit test, but I'm still
trying to figure out the best way to do that. The heuristics are still
in considerable flux, but as they are refined we should be rigorous
about unit testing the improvements.

llvm-svn: 167527
2012-11-07 07:05:09 +00:00
Andrew Trick 4d1fa712ac misched: Rename RemainingCount to avoid confusion with remaining resources.
llvm-svn: 167443
2012-11-06 07:10:34 +00:00
Andrew Trick d9d4be0d57 misched: Added handleMove support for updating all kill flags, not just for allocatable regs.
This is a medium term workaround until we have a more robust solution
in the form of a register liveness utility for postRA passes.

llvm-svn: 166001
2012-10-16 00:22:51 +00:00
Andrew Trick 90f711da9a misched: ILP scheduler for experimental heuristics.
llvm-svn: 165950
2012-10-15 18:02:27 +00:00
Andrew Trick dd79f0fcea misched: Use the TargetSchedModel interface wherever possible.
Allows the new machine model to be used for NumMicroOps and OutputLatency.

Allows the HazardRecognizer to be disabled along with itineraries.

llvm-svn: 165603
2012-10-10 05:43:09 +00:00
Andrew Trick 984d98bf6a misched: avoid scheduling an instruction twice.
llvm-svn: 165416
2012-10-08 18:53:53 +00:00
Andrew Trick a2733e9549 misched: add a hook for custom DAG postprocessing.
llvm-svn: 163915
2012-09-14 17:22:42 +00:00
Manman Ren 19f49ac624 Release build: guard dump functions with
"#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)"

No functional change. Update r163339.

llvm-svn: 163653
2012-09-11 22:23:19 +00:00
Andrew Trick 7a8e10042f Reorganize MachineScheduler interfaces and publish them in the header.
The Hexagon target decided to use a lot of functionality from the
target-independent scheduler. That's fine, and other targets should be
able to do the same. This reorg and API update makes that easy.

For the record, ScheduleDAGMI was not meant to be subclassed. Instead,
new scheduling algorithms should be able to implement
MachineSchedStrategy and be done. But if need be, it's nice to be
able to extend ScheduleDAGMI, so I also made that easier. The target
scheduler is somewhat more apt to break that way though.

llvm-svn: 163580
2012-09-11 00:39:15 +00:00
Manman Ren 742534c4dc Release build: guard dump functions with "ifndef NDEBUG"
No functional change.

llvm-svn: 163339
2012-09-06 19:06:06 +00:00
Andrew Trick ae53561b0c Simplify the computeOperandLatency API.
The logic for recomputing latency based on a ScheduleDAG edge was
shady. This bypasses the problem by requiring the client to provide
operand indices. This ensures consistent use of the machine model's
API.

llvm-svn: 162420
2012-08-23 00:39:43 +00:00
Craig Topper a538d831e6 Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed.
llvm-svn: 162347
2012-08-22 06:07:19 +00:00
Sylvestre Ledru 35521e2310 Fix a typo (the the => the)
llvm-svn: 160621
2012-07-23 08:51:15 +00:00
Andrew Trick 87255e340e I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.

llvm-svn: 159891
2012-07-07 04:00:00 +00:00
Andrew Trick 2f26b34806 misched: allow NULL InstrItineraries.
llvm-svn: 159599
2012-07-02 21:55:12 +00:00
Andrew Trick 8c9e6728b3 misched: avoid scheduling instructions that can't be dispatched.
llvm-svn: 159408
2012-06-29 03:23:24 +00:00
Andrew Trick ce27bb999d misched: count micro-ops toward the issue limit.
llvm-svn: 159407
2012-06-29 03:23:22 +00:00
Benjamin Kramer b9f84bb0ce Guard private fields that are unused in Release builds with #ifndef NDEBUG.
llvm-svn: 158608
2012-06-16 21:48:13 +00:00
Andrew Trick 05ff4667eb Move RegisterClassInfo.h.
Allow targets to access this API. It's required for RegisterPressure.

llvm-svn: 158102
2012-06-06 20:29:31 +00:00
Andrew Trick 88517f608c Move RegisterPressure.h.
Make it a general utility for use by Targets.

llvm-svn: 158097
2012-06-06 19:47:35 +00:00
Andrew Trick 4544606c71 misched: API for minimum vs. expected latency.
Minimum latency determines per-cycle scheduling groups.
Expected latency determines critical path and cost.

llvm-svn: 158021
2012-06-05 21:11:27 +00:00
Andrew Trick d36adece50 misched: comments from code review.
llvm-svn: 157975
2012-06-05 03:44:26 +00:00
Andrew Trick 4e7f6a7702 misched: trace formatting
llvm-svn: 157455
2012-05-25 02:02:39 +00:00
Kaelyn Uhrain 85d8f0cba8 Silence unused variable warnings from when assertions are disabled.
llvm-svn: 157438
2012-05-24 23:37:49 +00:00
Andrew Trick a306a8a844 misched: Use the same scheduling heuristics with -misched-topdown/bottomup.
(except the part about choosing direction)

llvm-svn: 157437
2012-05-24 23:11:17 +00:00
Andrew Trick 79d3eecbb4 misched: Trace regpressure.
llvm-svn: 157429
2012-05-24 22:11:14 +00:00
Andrew Trick a8ad5f7c7b misched: Give each ReadyQ a unique ID
llvm-svn: 157428
2012-05-24 22:11:12 +00:00
Andrew Trick 61f1a278b8 misched: Added ScoreboardHazardRecognizer.
The Hazard checker implements in-order contraints, or interlocked
resources. Ready instructions with hazards do not enter the available
queue and are not visible to other heuristics.

The major code change is the addition of SchedBoundary to encapsulate
the state at the top or bottom of the schedule, including both a
pending and available queue.

The scheduler now counts cycles in sync with the hazard checker. These
are minimum cycle counts based on known hazards.

Targets with no itinerary (x86_64) currently remain at cycle 0. To fix
this, we need to provide some maximum issue width for all targets. We
also need to add the concept of expected latency vs. minimum latency.

llvm-svn: 157427
2012-05-24 22:11:09 +00:00
Andrew Trick ca47335461 misched: Release bottom roots in reverse order.
llvm-svn: 157426
2012-05-24 22:11:05 +00:00
Andrew Trick dd375dd34a misched: rename ReadyQ class
llvm-svn: 157425
2012-05-24 22:11:03 +00:00
Andrew Trick f378617773 misched: copy comments so compareRPDelta is readable by itself.
llvm-svn: 157424
2012-05-24 22:11:01 +00:00
Andrew Trick 6a50baa26e comments
llvm-svn: 157020
2012-05-17 22:37:09 +00:00