Commit Graph

611 Commits

Author SHA1 Message Date
Colin LeMahieu 94269db8ba [Hexagon] Converting multiply and accumulate with immediate intrinsics to patterns.
llvm-svn: 226681
2015-01-21 18:13:15 +00:00
Colin LeMahieu 988c68f2a7 [Hexagon] Adding intrinsics for doubleword ALU operations.
llvm-svn: 226606
2015-01-20 20:45:05 +00:00
Colin LeMahieu 0ee02fc9fe [Hexagon] Updating muxir/ri/ii intrinsics. Setting predicate registers as compatible with i32 rather than doing custom type conversion.
llvm-svn: 226500
2015-01-19 20:31:18 +00:00
Colin LeMahieu fcd4569af6 [Hexagon] Converting intrinsics combine imm/imm, simple shifts and extends.
llvm-svn: 226483
2015-01-19 18:56:19 +00:00
Colin LeMahieu 9327bdad2f [Hexagon] Converting remaining ALU32/ALU intrinsics.
llvm-svn: 226480
2015-01-19 18:33:58 +00:00
Colin LeMahieu 663419b008 [Hexagon] Converting ALU32/ALU intrinsics to new patterns.
llvm-svn: 226478
2015-01-19 18:22:19 +00:00
Colin LeMahieu 310bad8b7e [Hexagon] Converting halfword to double accumulating multiply intrinsics.
llvm-svn: 226472
2015-01-19 17:36:32 +00:00
David Blaikie 9459832ebd std::unique_ptrify the MCStreamer argument to createAsmPrinter
llvm-svn: 226414
2015-01-18 20:29:04 +00:00
Colin LeMahieu 823415b881 [Hexagon] Converting halfword to doubleword multiply intrinsics.
llvm-svn: 226326
2015-01-16 21:41:57 +00:00
Colin LeMahieu cd9b276966 [Hexagon] Converting accumulating halfword multiply intrinsics to patterns.
llvm-svn: 226324
2015-01-16 21:36:34 +00:00
Colin LeMahieu 3b047e0ee5 [Hexagon] Beginning converting intrinsics to patterns instead of duplicated definitions. Converting halfword multiply intrinsics.
llvm-svn: 226318
2015-01-16 20:38:54 +00:00
Colin LeMahieu 54adb6a5d5 [Hexagon] Fix 226309, replacement atomic store patterns didn't actually exist, added new versions.
llvm-svn: 226315
2015-01-16 20:16:14 +00:00
Colin LeMahieu bb6718b30e [Hexagon] Removing old duplicate atomic load/store patterns.
llvm-svn: 226309
2015-01-16 19:53:35 +00:00
Colin LeMahieu 7d1f632380 [Hexagon] Converting old patterns to new versions using classes.
llvm-svn: 226304
2015-01-16 19:29:59 +00:00
Colin LeMahieu 2e3a26de0c [Hexagon] Updating call/jump instruction patterns.
llvm-svn: 226288
2015-01-16 17:05:27 +00:00
Colin LeMahieu cd9c4e3e07 [Hexagon] Adding new-value store and bit reverse instructions.
llvm-svn: 226224
2015-01-15 23:10:29 +00:00
Colin LeMahieu c59328e627 [Hexagon] Fix 226206 by uncommenting required pattern and changing patterns for simple load-extends.
llvm-svn: 226210
2015-01-15 21:35:49 +00:00
Colin LeMahieu f87697f05e [Hexagon] Updating indexed load-extend patterns and changing test to new expected output.
llvm-svn: 226206
2015-01-15 21:07:52 +00:00
Colin LeMahieu 538b85810c [Hexagon] Removing old versions of vsplice, valign, cl0, ct0 and updating references to new versions.
llvm-svn: 226194
2015-01-15 19:28:32 +00:00
Colin LeMahieu 504157f1ae [Hexagon] Adding vmux instruction. Removing old transfer instructions and updating references.
llvm-svn: 226184
2015-01-15 18:16:00 +00:00
Colin LeMahieu 2d1c14563e [Hexagon] Deleting old float comparison instruction and updating references to new ones.
llvm-svn: 226179
2015-01-15 17:28:14 +00:00
Colin LeMahieu 7959cac725 [Hexagon] Replacing old fadd/fsub instructions and updating references.
llvm-svn: 226176
2015-01-15 16:30:07 +00:00
Colin LeMahieu 8ffce23cda [Hexagon] Replacing old versions of stores and loads.
llvm-svn: 226065
2015-01-15 00:15:30 +00:00
Colin LeMahieu c7522f31f1 [Hexagon] Replacing old version of convert and load f64.
llvm-svn: 226057
2015-01-14 23:07:36 +00:00
Colin LeMahieu 11a34b385d [Hexagon] Removing old, unused !tstbit instructions.
llvm-svn: 226036
2015-01-14 20:26:15 +00:00
Colin LeMahieu c91fabc233 [Hexagon] Removing old versions of cmph and updating references.
llvm-svn: 226013
2015-01-14 18:26:14 +00:00
Colin LeMahieu ffacc6eac6 [Hexagon] Removing old versions of cmpb and updating references.
llvm-svn: 226006
2015-01-14 18:05:44 +00:00
Colin LeMahieu fa947906bf [Hexagon] Deleting versions of compare-not that don't have encoding information. Updating references.
llvm-svn: 226003
2015-01-14 16:49:12 +00:00
Chandler Carruth d9903888d9 [cleanup] Re-sort all the #include lines in LLVM using
utils/sort_includes.py.

I clearly haven't done this in a while, so more changed than usual. This
even uncovered a missing include from the InstrProf library that I've
added. No functionality changed here, just mechanical cleanup of the
include order.

llvm-svn: 225974
2015-01-14 11:23:27 +00:00
Ahmed Bougacha 2b6917b020 [SelectionDAG] Allow targets to specify legality of extloads' result
type (in addition to the memory type).

The *LoadExt* legalization handling used to only have one type, the
memory type.  This forced users to assume that as long as the extload
for the memory type was declared legal, and the result type was legal,
the whole extload was legal.

However, this isn't always the case.  For instance, on X86, with AVX,
this is legal:
    v4i32 load, zext from v4i8
but this isn't:
    v4i64 load, zext from v4i8
Whereas v4i64 is (arguably) legal, even without AVX2.

Note that the same thing was done a while ago for truncstores (r46140),
but I assume no one needed it yet for extloads, so here we go.

Calls to getLoadExtAction were changed to add the value type, found
manually in the surrounding code.

Calls to setLoadExtAction were mechanically changed, by wrapping the
call in a loop, to match previous behavior.  The loop iterates over
the MVT subrange corresponding to the memory type (FP vectors, etc...).
I also pulled neighboring setTruncStoreActions into some of the loops;
those shouldn't make a difference, as the additional types are illegal.
(e.g., i128->i1 truncstores on PPC.)

No functional change intended.

Differential Revision: http://reviews.llvm.org/D6532

llvm-svn: 225421
2015-01-08 00:51:32 +00:00
Colin LeMahieu 92b49c3e39 [Hexagon] Fix 225372 USR register is not fully complete. Removing Uses = [USR] maintains existing functionality to old instructions without encodings.
llvm-svn: 225377
2015-01-07 20:43:38 +00:00
Colin LeMahieu 627df427eb [Hexagon] Adding floating point classification and creation.
llvm-svn: 225374
2015-01-07 20:28:57 +00:00
Colin LeMahieu 290ece7d4c [Hexagon] Adding encodings for v5 floating point instructions.
llvm-svn: 225372
2015-01-07 20:24:09 +00:00
Colin LeMahieu 777abcb1d7 [Hexagon] Adding encoding for popcount, fastcorner, dword asr with rounding.
llvm-svn: 225371
2015-01-07 20:07:28 +00:00
Colin LeMahieu 507dd32703 [Hexagon] Adding compound jump encodings.
llvm-svn: 225291
2015-01-06 20:03:31 +00:00
Colin LeMahieu 68b2e050f0 [Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, dcfetch.
llvm-svn: 225283
2015-01-06 19:03:20 +00:00
Colin LeMahieu d9c605ddae [Hexagon] Adding encoding information for absolute address loads.
llvm-svn: 225279
2015-01-06 18:38:26 +00:00
Colin LeMahieu 243a5481d9 [Hexagon] Fix 225267. GP register is not yet fully implemented. Removing Uses [GP] maintains existing behavior.
llvm-svn: 225270
2015-01-06 16:52:38 +00:00
Colin LeMahieu 1445553474 [Hexagon] Adding dealloc_return encoding and absolute address stores.
llvm-svn: 225267
2015-01-06 16:15:15 +00:00
Colin LeMahieu dacf057bdc [Hexagon] Adding add/sub with carry, logical shift left by immediate and memop instructions. Removing old defs without bits and updating references.
llvm-svn: 225210
2015-01-05 21:36:38 +00:00
Colin LeMahieu 28bb02a8c7 [Hexagon] Adding rounding reg/reg variants, accumulating multiplies, and accumulating shifts.
llvm-svn: 225201
2015-01-05 20:56:41 +00:00
Colin LeMahieu abdf2b37d8 [Hexagon] Adding V4 bit manipulating instructions, removing ALU defs without encoding bits.
llvm-svn: 225199
2015-01-05 20:35:54 +00:00
Colin LeMahieu 3acfddd6b5 [Hexagon] Adding V4 logic-logic instructions and tests.
llvm-svn: 225198
2015-01-05 20:14:58 +00:00
Colin LeMahieu ff10c8c95c [Hexagon] Adding orand, bitsplit reg/reg, and modwrap instructions.
llvm-svn: 225197
2015-01-05 20:04:40 +00:00
Colin LeMahieu 5e079577e1 [Hexagon] Adding round reg/imm and bitsplit instructions.
llvm-svn: 225188
2015-01-05 18:08:21 +00:00
Craig Topper d3c02f177a Replace several 'assert(false' with 'llvm_unreachable' or fold a condition into the assert.
llvm-svn: 225160
2015-01-05 10:15:49 +00:00
Colin LeMahieu 5691eb5ee7 Reverting 225045 and 225043 and XFAIL multiline.ll on hexagon
llvm-svn: 225047
2014-12-31 17:14:35 +00:00
Colin LeMahieu 79e8ebada2 [Hexagon] Removing assertion to appease buildbot until I can reproduce the problem
llvm-svn: 225045
2014-12-31 16:20:00 +00:00
Colin LeMahieu 94272611ac [Hexagon] Changing an llvm_unreachable to an assertion and returning 0. Relocations aren't implemented yet but we don't need to abort for this in release builds.
llvm-svn: 225043
2014-12-31 15:57:38 +00:00
Colin LeMahieu bc405294f0 [Hexagon] Adding accumulating add/sub, doubleword logic-not variants, doubleword bitfield extract, word parity, accumulating multiplies with saturation.
llvm-svn: 225024
2014-12-31 00:08:34 +00:00