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3580 Commits

Author SHA1 Message Date
Evan Cheng ed23a1387e Minor bug. 
llvm-svn: 36473
 2007-04-26 08:24:22 +00:00
Evan Cheng 43a17fe826 Be careful when to add implicit kill / dead operands. Don't add them during / post reg-allocation. 
llvm-svn: 36458
 2007-04-26 01:40:09 +00:00
Evan Cheng 0ba174534c Match MachineFunction::UsedPhysRegs changes. 
llvm-svn: 36452
 2007-04-25 22:13:27 +00:00
Evan Cheng d21968d11a Change UsedPhysRegs from array bool to BitVector to save some space. Setting / getting its states now go through MachineFunction. 
llvm-svn: 36451
 2007-04-25 22:10:09 +00:00
Evan Cheng d4549c5527 Clean up. 
llvm-svn: 36449
 2007-04-25 21:34:08 +00:00
Evan Cheng 0fbe14ab87 Data structure change to improve compile time (especially in debug mode). 
llvm-svn: 36447
 2007-04-25 19:34:00 +00:00
Evan Cheng 15f269afa3 This was lefted out. Fixed sumarray-dbl. 
llvm-svn: 36445
 2007-04-25 18:33:21 +00:00
Anton Korobeynikov a97b694c82 Implement aliases. This fixes PR1017 and it's dependent bugs. CFE part 
will follow.

llvm-svn: 36435
 2007-04-25 14:27:10 +00:00
Evan Cheng 7818c03c6b Fix for PR1306. 
- A register def / use now implicitly affects sub-register liveness but does
not affect liveness information of super-registers.
- Def of a larger register (if followed by a use later) is treated as
read/mod/write of a smaller register.

llvm-svn: 36434
 2007-04-25 07:30:23 +00:00
Evan Cheng 11dc5abde1 Clean up. 
llvm-svn: 36431
 2007-04-25 07:18:20 +00:00
Chris Lattner b975bebec1 support for >4G stack frames 
llvm-svn: 36425
 2007-04-25 04:30:24 +00:00
Chris Lattner 9bd98ea4c1 support > 4G stack objects 
llvm-svn: 36422
 2007-04-25 04:20:54 +00:00
Chris Lattner cb0ed0cfbd allow support for 64-bit stack objects 
llvm-svn: 36420
 2007-04-25 04:08:28 +00:00
Chris Lattner 01a26c74ae Be more careful about folding op(x, undef) when we have vector operands. 
This fixes CodeGen/X86/2007-04-24-VectorCrash.ll

llvm-svn: 36413
 2007-04-25 00:00:45 +00:00
Bill Wendling 47917b697f Assertion when using a 1-element vector for an add operation. Get the 
real vector type in this case.

llvm-svn: 36402
 2007-04-24 21:13:23 +00:00
Scott Michel 4cfa616cee Use '-1U' where '-1UL' is obvious overkill, eliminating gcc warnings about 
tests always being true in the process.

llvm-svn: 36387
 2007-04-24 01:24:20 +00:00
Dale Johannesen 8653d29b45 modify per review commentary 
llvm-svn: 36383
 2007-04-23 23:33:31 +00:00
Dale Johannesen 14a28f13c8 make EmitAlignment work the way Chris says it should 
llvm-svn: 36368
 2007-04-23 19:58:54 +00:00
Christopher Lamb 8af6d5896f PR400 phase 2. Propagate attributed load/store information through DAGs. 
llvm-svn: 36356
 2007-04-22 23:15:30 +00:00
Lauro Ramos Venancio 4e91908f17 X86 TLS: Implement review feedback. 
llvm-svn: 36318
 2007-04-21 20:56:26 +00:00
Reid Spencer 0c1349e6bc Revert Christopher Lamb's load/store alignment changes. 
llvm-svn: 36309
 2007-04-21 18:36:27 +00:00
Christopher Lamb bff50208c8 add support for alignment attributes on load/store instructions 
llvm-svn: 36301
 2007-04-21 08:16:25 +00:00
Lauro Ramos Venancio 94314be0e0 Allow the lowering of ISD::GLOBAL_OFFSET_TABLE. 
llvm-svn: 36290
 2007-04-20 23:02:39 +00:00
Lauro Ramos Venancio 2518889872 Implement "general dynamic", "initial exec" and "local exec" TLS models for 
X86 32 bits.

llvm-svn: 36283
 2007-04-20 21:38:10 +00:00
Evan Cheng 4c53d321aa VarInfo::UsedBlocks is no longer used. Remove. 
llvm-svn: 36250
 2007-04-18 05:04:38 +00:00
Chris Lattner f03c90bee6 allow SRL to simplify its operands, as it doesn't demand all bits as input. 
llvm-svn: 36245
 2007-04-18 03:06:49 +00:00
Chris Lattner bf14f20632 When replacing a node in SimplifyDemandedBits, if the old node used any 
single-use nodes, they will be dead soon.  Make sure to remove them before
processing other nodes.  This implements CodeGen/X86/shl_elim.ll

llvm-svn: 36244
 2007-04-18 03:05:22 +00:00
Chris Lattner 15c1b820cc fix a pasto 
llvm-svn: 36242
 2007-04-18 03:01:40 +00:00
Evan Cheng b408e8f11d Don't populate TryAgainList when coalescing only physical registers with virtual registers. 
llvm-svn: 36240
 2007-04-18 02:30:19 +00:00
Evan Cheng a5a0c7c909 Increment use count of new virtuals created during PHI elimination. 
llvm-svn: 36233
 2007-04-18 00:36:11 +00:00
Chris Lattner 4aff52bf3d Fix a bug in my previous patch, grabbing the shift amount width from the 
wrong operand.

llvm-svn: 36223
 2007-04-17 22:53:02 +00:00
Chris Lattner 9a861a8550 Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used. 
This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        srwi r2, r3, 1
        extsh r3, r2
        blr

on PPC, instead of:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

GCC produces:
_baz:
        srwi r10,r4,24
        insrwi r10,r3,24,0
        srawi r9,r3,24
        srawi r3,r10,9
        extsh r3,r3
        blr

This implements CodeGen/PowerPC/shl_elim.ll

llvm-svn: 36221
 2007-04-17 21:14:16 +00:00
Evan Cheng b881bdabd9 Copy coalescing change to prevent a physical register from being pin to a 
long live interval that has low usage density.
1. Change order of coalescing to join physical registers with virtual
   registers first before virtual register intervals become too long.
2. Check size and usage density to determine if it's worthwhile to join.
3. If joining is aborted, assign virtual register live interval allocation
   preference field to the physical register.
4. Register allocator should try to allocate to the preferred register
   first (if available) to create identify moves that can be eliminated.

llvm-svn: 36218
 2007-04-17 20:32:26 +00:00
Evan Cheng 57b5214d59 Add a register allocation preference field; add a method to compute size of a live interval. 
llvm-svn: 36216
 2007-04-17 20:25:11 +00:00
Evan Cheng 8387cf1100 Keep track of number of uses within the function per virtual register. 
llvm-svn: 36214
 2007-04-17 20:22:11 +00:00
Chris Lattner 9ad5915559 SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBits 
a chance to hack on it.  This compiles:

int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

instead of:

_baz:
        srwi r2, r4, 24
        rlwimi r2, r3, 8, 0, 23
        srwi r2, r2, 9
        extsh r3, r2
        blr

This implements CodeGen/PowerPC/sign_ext_inreg1.ll

llvm-svn: 36212
 2007-04-17 19:03:21 +00:00
Reid Spencer 58ec791b4c Fix problems in the PartSet lowering having to do with incorrect bit width. 
llvm-svn: 36180
 2007-04-16 22:21:14 +00:00
Anton Korobeynikov fb80151c42 Removed tabs everywhere except autogenerated & external files. Add make 
target for tabs checking.

llvm-svn: 36146
 2007-04-16 18:10:23 +00:00
Chris Lattner 6bd7b7b30b disable switch lowering using shift/and. It still breaks ppc bootstrap for 
some reason.  :(  Will investigate.

llvm-svn: 36011
 2007-04-14 19:39:41 +00:00
Anton Korobeynikov 8a1a84f96e Fix PR1325: Case range optimization was performed in the case it 
shouldn't. Also fix some "latent" bug on 64-bit platforms

llvm-svn: 35990
 2007-04-14 13:25:55 +00:00
Chris Lattner 7196f09edc disable shift/and lowering to work around PR1325 for now. 
llvm-svn: 35985
 2007-04-14 02:26:56 +00:00
Anton Korobeynikov e288040abf Fix PR1323 : we haven't updated phi nodes in good manner :) 
llvm-svn: 35963
 2007-04-13 06:53:51 +00:00
Reid Spencer 1b9213730f Make sure intrinsics that are lowered to functions make the function weak 
linkage so we only end up with one of them in a program. These are, after
all overloaded and templatish in nature.

llvm-svn: 35956
 2007-04-12 21:53:38 +00:00
Reid Spencer 0f2f65f723 Fix bugs in generated code for part_select and part_set so that llc doesn't 
barf when CBE is run with a program that contains these intrinsics.

llvm-svn: 35946
 2007-04-12 13:30:14 +00:00
Reid Spencer 83faeb7611 Fix a bug in PartSet. The replacement value needs to be zext or trunc to 
the size of the value, not just zext. Also, give better names to two BBs.

llvm-svn: 35945
 2007-04-12 12:46:33 +00:00
Chris Lattner 5111499136 the result of an inline asm copy can be an arbitrary VT that the register 
class supports.  In the case of vectors, this means we often get the wrong
type (e.g. we get v4f32 instead of v8i16).  Make sure to convert the vector
result to the right type.  This fixes CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll

llvm-svn: 35944
 2007-04-12 06:00:20 +00:00
Chris Lattner a77cb3ce68 fold noop vbitconvert instructions 
llvm-svn: 35943
 2007-04-12 05:58:43 +00:00
Chris Lattner 784a68a702 Fix weirdness handling single element vectors. 
llvm-svn: 35941
 2007-04-12 04:44:28 +00:00
Reid Spencer c6251a7dfd For PR1284: 
Implement the "part_set" intrinsic.

llvm-svn: 35938
 2007-04-12 02:48:46 +00:00
Chris Lattner 18e4ac4107 fix an infinite loop compiling ldecod, notice by JeffC. 
llvm-svn: 35910
 2007-04-11 16:51:53 +00:00