maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
277,975 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

45084 Commits

Author SHA1 Message Date
Nikolai Bozhenov 1cf9c54e5c [Nios2] final infrastructure to provide compilation of a return from a function 
This patch includes all missing functionality needed to provide first
compilation of a simple program that just returns from a function.
I've added a test case that checks for "ret" instruction printed in assembly
output.

Patch by Andrei Grischenko (andrei.l.grischenko@intel.com)
Differential revision: https://reviews.llvm.org/D39688

llvm-svn: 320035
 2017-12-07 12:35:02 +00:00
Andrew V. Tischenko 44cfc51415 Add proper BTVER2 sched support for MOV instr. 
Differential Revision: https://reviews.llvm.org/D40345

llvm-svn: 320034
 2017-12-07 11:19:49 +00:00
Alex Bradbury ee8950efd5 [RISCV] MC layer support for the standard RV64D instruction set extension 
llvm-svn: 320029
 2017-12-07 11:04:18 +00:00
Alex Bradbury 4dd94e0ccd [RISCV] MC layer support for the standard RV64F instruction set extension 
llvm-svn: 320028
 2017-12-07 11:02:55 +00:00
Alex Bradbury 48f95a655d [RISCV] MC layer support for the standard RV64A instruction set extension 
llvm-svn: 320027
 2017-12-07 10:59:12 +00:00
Alex Bradbury 81def7224e [RISCV] MC layer support for the standard RV64M instruction set extension 
llvm-svn: 320026
 2017-12-07 10:56:07 +00:00
Alex Bradbury a6e6248307 [RISCV] MC layer support for the standard RV64I instructions 
llvm-svn: 320024
 2017-12-07 10:53:48 +00:00
Alex Bradbury 7bc2a95bb9 [RISCV] MC layer support for the standard RV32D instruction set extension 
As the FPR32 and FPR64 registers have the same names, use 
validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an 
FPR64 when necessary. The rest of this patch is very similar to the RV32F 
patch.

Differential Revision: https://reviews.llvm.org/D39895

llvm-svn: 320023
 2017-12-07 10:46:23 +00:00
Francis Visoiu Mistrih a8a83d150f [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 
Work towards the unification of MIR and debug output by refactoring the
interfaces.

For MachineOperand::print, keep a simple version that can be easily called
from `dump()`, and a more complex one which will be called from both the
MIRPrinter and MachineInstr::print.

Add extra checks inside MachineOperand for detached operands (operands
with getParent() == nullptr).

https://reviews.llvm.org/D40836

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+)<def> ([^ ]+)/kill: \1 def \2 \3/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: \1 \2 def \3/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: def ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: def \1 \2 def \3/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/<def>//g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<kill>/killed \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use,kill>/implicit killed \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<dead>/dead \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<def[ ]*,[ ]*dead>/dead \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def[ ]*,[ ]*dead>/implicit-def dead \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def>/implicit-def \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use>/implicit \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<internal>/internal \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<undef>/undef \1/g'

llvm-svn: 320022
 2017-12-07 10:40:31 +00:00
Alex Bradbury 0d6cf90663 [RISCV] MC layer support for the standard RV32F instruction set extension 
The most interesting part of this patch is probably the handling of 
rounding mode arguments. Sadly, the RISC-V assembler handles floating point 
rounding modes as a special "argument" when it would be more consistent to 
handle them like the atomics, opcode suffixes. This patch supports parsing 
this optional parameter, using InstAlias to allow parsing these floating point 
instructions when no rounding mode is specified.

Differential Revision: https://reviews.llvm.org/D39893

llvm-svn: 320020
 2017-12-07 10:26:05 +00:00
Leslie Zhai 8543d53fd9 [AVR] Override ParseDirective 
Reviewers: dylanmckay, kparzysz

Reviewed By: dylanmckay

Differential Revision: https://reviews.llvm.org/D38029

llvm-svn: 320009
 2017-12-07 06:56:09 +00:00
Dan Gohman 5cf6473903 [WebAssembly] Don't try to emit size information for unsized types 
Patch by John Sully!

Fixes PR35164.

Differential Revision: https://reviews.llvm.org/D39519

llvm-svn: 319991
 2017-12-07 00:14:30 +00:00
Florian Hahn 5d6a4e43ba [AArch64] Add patterns to replace fsub fmul with fma fneg. 
Summary:
This patch adds MachineCombiner patterns for transforming
(fsub (fmul x y) z) into (fma x y (fneg z)). This has a lower
latency on micro architectures where fneg is cheap.

Patch based on work by George Steed.

Reviewers: rengolin, joelkevinjones, joel_k_jones, evandro, efriedma

Reviewed By: evandro

Subscribers: aemerson, javed.absar, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D40306

llvm-svn: 319980
 2017-12-06 22:48:36 +00:00
Krzysztof Parzyszek d2967868be [Hexagon] Recognize vdealb, vdealh, vshuffb and vshuffh specifically 
llvm-svn: 319978
 2017-12-06 22:41:49 +00:00
Krzysztof Parzyszek 64533cf630 [Hexagon] Handle perfect shuffles on single vectors 
llvm-svn: 319965
 2017-12-06 21:25:03 +00:00
Dan Gohman ad19047d83 [WebAssembly] Remove WASM_STACK_POINTER. 
WASM_STACK_POINTER and the .stack_pointer directive are no longer needed
now that the stack pointer global is an import.

llvm-svn: 319956
 2017-12-06 20:56:40 +00:00
Alina Sbirlea 18fea013de [ModRefInfo] Do not use ModRefInfo result in if conditions as this makes 
assumptions about the values in the enum. Replace with wrapper returning
bool [NFC].

llvm-svn: 319949
 2017-12-06 19:56:37 +00:00
Simon Pilgrim 9afbe77a91 [X86][AVX512] Tag mask reg op instruction scheduler classes 
llvm-svn: 319945
 2017-12-06 19:36:00 +00:00
Tim Shen b684b1aa35 [Hexagon] Suppress more warnings on unused variables defined for asserts. 
llvm-svn: 319944
 2017-12-06 19:33:42 +00:00
Tim Shen 7654ed03e3 [Hexagon] Suppress warnings on unused variables defind for asserts. 
llvm-svn: 319940
 2017-12-06 19:22:19 +00:00
Davide Italiano 9c60c7dcf4 [Target] dumpr() is defined only in debug builds. 
This fixes the clang build on macOS.

llvm-svn: 319923
 2017-12-06 18:54:17 +00:00
Simon Pilgrim d255a6201d [X86][AVX512] Tag scalar insert/extract instruction scheduler classes 
Classes don't look great but match what we're doing on SSE/AVX

llvm-svn: 319920
 2017-12-06 18:46:06 +00:00
Craig Topper 8b0f185c31 [X86] Simplify the TTI code for getInterleavedMemoryOpCost around for AVX512BW. NFCI 
Previously the lambda for AVX512 passed out a flag that indicated whether AVX512BW was required and that was checked against the AVX512BW subtarget flag outside.

This patch changes the interface to pass the AVX512BW subtarget bit in and return its value if we detect 16 or 8 bit types.

llvm-svn: 319919
 2017-12-06 18:40:46 +00:00
Simon Pilgrim 809c024b3d [X86][AVX2] Tag MASKMOV instruction scheduler classes 
llvm-svn: 319915
 2017-12-06 18:24:48 +00:00
Simon Pilgrim df05251921 [X86][AVX512] Tag aligned/unaligned move instruction scheduler classes 
llvm-svn: 319913
 2017-12-06 17:59:26 +00:00
Artem Belevich a659d2590e [NVPTX,CUDA] Added llvm.nvvm.fns intrinsic and matching __nvvm_fns builtin in clang. 
Differential Revision: https://reviews.llvm.org/D40872

llvm-svn: 319909
 2017-12-06 17:50:05 +00:00
Jonas Paulsson a74ff71a37 [SystemZ] Add IntrWriteMem flag to int_s390_tabort intrinsic 
Tabort (transaction abort) does not load from memory.

mayLoad flag removed from corresponding TABORT machine instruction.

Review: Ulrich Weigand
llvm-svn: 319905
 2017-12-06 17:01:08 +00:00
Krzysztof Parzyszek 7d37dd8902 [Hexagon] Generate HVX code for vector construction and access 
Support for:
  - build vector,
  - extract vector element, subvector,
  - insert vector element, subvector,
  - shuffle.

llvm-svn: 319901
 2017-12-06 16:40:37 +00:00
Simon Pilgrim aa902be158 [X86][AVX512] Tag BROADCAST instruction scheduler classes 
llvm-svn: 319900
 2017-12-06 15:48:40 +00:00
Nirav Dave 7d8f3e0c93 [ARM][AArch64][DAG] Reenable post-legalize store merge 
Reenable post-legalize stores with constant merging computation and
corresponding test case.

 * Properly truncate store merge constants
 * Disable merging of truncated stores floating points
 * Ensure merges of constant stores into a single vector are
   constructed from legal elements.

Reviewers: eastig, efriedma

Reviewed By: eastig

Subscribers: spatel, rengolin, aemerson, javed.absar, kristof.beyls, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D40701

llvm-svn: 319899
 2017-12-06 15:30:13 +00:00
Jonas Paulsson 19380bae05 [SystemZ] Bugfix in expandRxSBG() 
Csmith discovered a program that caused wrong code generation with -O0:

When handling a SIGN_EXTEND in expandRxSBG(), RxSBG.BitSize may be less than
the Input width (if a truncate was previously traversed), so maskMatters()
should be called with a masked based on the width of the sign extend result
instead.

Review: Ulrich Weigand
llvm-svn: 319892
 2017-12-06 13:53:24 +00:00
Benjamin Kramer 1e9bf765a1 [X86] Avoid unused variable warning in Release builds. NFCI. 
llvm-svn: 319891
 2017-12-06 13:32:36 +00:00
Simon Pilgrim 07dc6d6975 [X86][AVX512] Drop default NoItinerary arguments that aren't needed 
Requires reordering of AVX512_maskable_common arguments, but helps track what is still missing itinerary tags

llvm-svn: 319890
 2017-12-06 13:14:44 +00:00
Simon Dardis 515f42cbaa [mips] Fix definition of 'bc' instruction 
llvm-svn: 319888
 2017-12-06 12:42:49 +00:00
Simon Pilgrim bfe969c49b [X86][AVX512] Tag Mask<->Vector instructions scheduler classes 
llvm-svn: 319887
 2017-12-06 11:59:05 +00:00
Simon Pilgrim 75673946fc [X86][AVX512] Cleanup scalar move scheduler classes 
llvm-svn: 319884
 2017-12-06 11:23:13 +00:00
Craig Topper 3275eb7a68 [X86] Split 512-bit vector extends from types other than vXi1 out of LowerZERO_EXTEND_AVX512/LowerSIGN_EXTEND_AVX512. NFCI 
Most of the code in these routines is for handling extends from vXi1 types. The 512-bit handling for other extends is very much like the AVX2 code. So make the special routines just do vXi1 types and move the other 512-bit handling to the place that handles AVX2.

llvm-svn: 319878
 2017-12-06 07:37:20 +00:00
Derek Schuff 8122ca92c8 [WebAssembly] Only emit stack pointer delcaration in BinFormatWasm assembly 
llvm-svn: 319870
 2017-12-06 01:38:29 +00:00
Craig Topper 647e4f590f [X86] Update to getSetCCResultType to be more robust to EVT types. 
Attempt to determine what the type will be legalized to and then analyze that to see if we will be able to use a vXi1 compare.

llvm-svn: 319861
 2017-12-06 00:15:17 +00:00
Joel Galenson 3e40883e4c [AArch64] Do not abort if overflow check does not use EQ or NE. 
As suggested by Eli Friedman, instead of aborting if an overflow check
uses something other than SETEQ or SETNE, simply do not apply the
optimization.

Differential Revision: https://reviews.llvm.org/D39147

llvm-svn: 319837
 2017-12-05 21:33:12 +00:00
Simon Pilgrim d495301414 [X86][AVX512] Tag BLENDM instruction scheduler classes 
llvm-svn: 319833
 2017-12-05 21:05:25 +00:00
Simon Pilgrim b69dae42e3 [X86][AVX512] Tag GATHER/SCATTER instruction scheduler classes 
NOTE: At the moment these use the WriteLoad/WriteStore classes, which severely underestimates the costs. This needs to be reviewed.
llvm-svn: 319829
 2017-12-05 20:47:11 +00:00
Matt Arsenault 8ae38bc0bd AMDGPU: Fix SDWA crash on inline asm 
This was only searching for explicit defs,
and asserting for any implicit or variadic
instruction defs, like inline asm.

llvm-svn: 319826
 2017-12-05 20:32:01 +00:00
Hans Wennborg 5df9f0878b Re-commit r319490 "XOR the frame pointer with the stack cookie when protecting the stack" 
The patch originally broke Chromium (crbug.com/791714) due to its failing to
specify that the new pseudo instructions clobber EFLAGS. This commit fixes
that.

> Summary: This strengthens the guard and matches MSVC.
>
> Reviewers: hans, etienneb
>
> Subscribers: hiraditya, JDevlieghere, vlad.tsyrklevich, llvm-commits
>
> Differential Revision: https://reviews.llvm.org/D40622

llvm-svn: 319824
 2017-12-05 20:22:20 +00:00
Simon Pilgrim 13d449d3e2 [X86][AVX512] Tag VPSLLDQ/VPSRLDQ instruction scheduler classes 
llvm-svn: 319822
 2017-12-05 20:16:22 +00:00
Alina Sbirlea 63d2250a42 Modify ModRefInfo values using static inline method abstractions [NFC]. 
Summary:
The aim is to make ModRefInfo checks and changes more intuitive
and less error prone using inline methods that abstract the bit operations.

Ideally ModRefInfo would become an enum class, but that change will require
a wider set of changes into FunctionModRefBehavior.

Reviewers: sanjoy, george.burgess.iv, dberlin, hfinkel

Subscribers: nlopes, llvm-commits

Differential Revision: https://reviews.llvm.org/D40749

llvm-svn: 319821
 2017-12-05 20:12:23 +00:00
Ulrich Weigand 5bfed6cb7c [SystemZ] Validate shifted compare value in adjustForTestUnderMask 
When folding a shift into a test-under-mask comparison, make sure that
there is no loss of precision when creating the shifted comparison
value.  This usually never happens, except for certain always-true
comparisons in unoptimized code.

Fixes PR35529.

llvm-svn: 319818
 2017-12-05 19:42:07 +00:00
Simon Pilgrim 833c260a4b [X86][AVX512] Tag VPTRUNC/VPMOVSX/VPMOVZX instruction scheduler classes 
llvm-svn: 319815
 2017-12-05 19:21:28 +00:00
Matt Arsenault 7f0a527300 AMDGPU: Fix infinite loop with dbg_value 
Surprisingly SIOptimizeExecMaskingPreRA can infinite loop
in some case with DBG_VALUE. Most tests using dbg_value are
run at -O0, so don't run this pass. This seems to only
happen when the value argument is undef.

llvm-svn: 319808
 2017-12-05 18:23:17 +00:00
Simon Pilgrim 65f805fe30 [X86][X87] Tag FCMOV instruction scheduler classes 
llvm-svn: 319804
 2017-12-05 18:01:26 +00:00