Commit Graph

66154 Commits

Author SHA1 Message Date
Kostya Serebryany 530e207d8a [asan] don't unpoison redzones on function exit in use-after-return mode.
Summary:
Before this change the instrumented code before Ret instructions looked like:
  <Unpoison Frame Redzones>
  if (Frame != OriginalFrame) // I.e. Frame is fake
     <Poison Complete Frame>

Now the instrumented code looks like:
  if (Frame != OriginalFrame) // I.e. Frame is fake
     <Poison Complete Frame>
  else
     <Unpoison Frame Redzones>

Reviewers: eugenis

Reviewed By: eugenis

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2458

llvm-svn: 197907
2013-12-23 14:15:08 +00:00
Kostya Serebryany ff7bde1582 [asan] produce fewer stores when poisoning stack shadow
llvm-svn: 197904
2013-12-23 09:24:36 +00:00
Roman Divacky bc1655b4b0 Use r2 when encoding tls on ppc32. Fixes PR18305.
llvm-svn: 197878
2013-12-22 10:45:37 +00:00
Benjamin Kramer 2151e63c71 Dwarf: Fix a copy-paste bug.
This tag isn't emitted by any compiler at the moment. PR18306.

llvm-svn: 197877
2013-12-22 10:23:23 +00:00
Elena Demikhovsky fe24a30e38 AVX512: SETCC returns i1 for AVX-512 and i8 for all others
llvm-svn: 197876
2013-12-22 10:13:18 +00:00
Roman Divacky 8854e76944 Add some comments.
llvm-svn: 197875
2013-12-22 09:48:38 +00:00
Alp Toker ce91fe5569 TableGen: Generate valid identifiers for anonymous records
Backends like OptParserEmitter assume that record names can be used as valid
identifiers.

The period '.' in generated anonymous names broke that assumption, causing a
build-time error and in practice forcing all records to be named.

llvm-svn: 197869
2013-12-21 18:51:00 +00:00
Mark Lacey 1d7c97eff3 Fix typo in assert message: s/load/store
llvm-svn: 197846
2013-12-21 00:00:49 +00:00
Yuchen Wu 5947c8fa99 BlockFrequencyInfo: Readded getEntryFreq.
llvm-svn: 197839
2013-12-20 22:11:11 +00:00
Lang Hames 18c98a587f ARM AnalyzeBranch should ignore DEBUG_VALUES while analyzing terminators.
Found by inspection by Julien Lerouge. Thanks Julian!

llvm-svn: 197833
2013-12-20 20:27:51 +00:00
Timur Iskhodzhanov 09069e0ff3 clang-format a couple of mis-formatted functions
llvm-svn: 197831
2013-12-20 20:16:51 +00:00
Timur Iskhodzhanov c1fb2d6111 [COFF] Add support for the .secidx directive
Reviewed at http://llvm-reviews.chandlerc.com/D2445

llvm-svn: 197826
2013-12-20 18:15:00 +00:00
Roman Divacky 32143e2bda Implement initial-exec TLS for PPC32.
llvm-svn: 197824
2013-12-20 18:08:54 +00:00
Zoran Jovanovic ce02486d16 Support for microMIPS FPU instructions 1.
llvm-svn: 197815
2013-12-20 15:44:08 +00:00
Rafael Espindola e23b87746a Make this array const.
llvm-svn: 197814
2013-12-20 15:21:32 +00:00
Richard Sandiford 83a0b6abd0 [SystemZ] Optimize comparisons with truncated extended loads
If the extension of a loaded value is compared against zero and used in
other arithmetic, InstCombine will change the comparison to use the
unextended load.  It's also possible that the comparison could be against
the unextended load from the outset.

In DAG form this becomes a truncation of an extending load.  We want to
strip the truncation if possible so that we can use load-and-test instructions.

llvm-svn: 197804
2013-12-20 11:56:02 +00:00
Richard Sandiford 220ee49bce [SystemZ] Extend RISBG optimization
The handling of ANY_EXTEND and ZERO_EXTEND was too strict.  In this context
we can treat ZERO_EXTEND in much the same way as an AND and then also handle
outermost ZERO_EXTENDs.

I couldn't find a test that benefited from the ANY_EXTEND change, but it's
more obvious to write it this way once SIGN_EXTEND and ZERO_EXTEND are
handled differently.

llvm-svn: 197802
2013-12-20 11:49:48 +00:00
Kai Nacke b38bf9626a Add support for krait cpu in llvm::sys::getHostCPUName()
Recently, support for krait cpu was added. This commit extends getHostCPUName()
to return krait as cpu for the APQ8064 (a Krait 300).

llvm-svn: 197792
2013-12-20 09:24:13 +00:00
Justin Bogner 0ba3f211c4 Transforms: Don't create bad weights when eliminating dead cases
If we happen to eliminate every case in a switch that has branch
weights, we currently try to create metadata for the one remaining
branch, triggering an assert. Instead, we need to check that the
metadata we're trying to create is sensible.

llvm-svn: 197791
2013-12-20 08:21:30 +00:00
Saleem Abdulrasool 6e6c239e33 ARM IAS: add support for the .pool directive
The .pool directive is an alias for the .ltorg directive used to create a
literal pool.  Simply treat .pool as if .ltorg was passed.

llvm-svn: 197787
2013-12-20 07:21:16 +00:00
Tom Stellard eddfa69465 R600: Allow ftrunc
v2: Add ftrunc->TRUNC pattern instead of replacing int_AMDGPU_trunc
v3: move ftrunc pattern next to TRUNC definition, it's available since R600

Patch By: Jan Vesely

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 197783
2013-12-20 05:11:55 +00:00
Eric Christopher 565ab11a35 Ranges in the .debug_range section need to have begin and end labels,
assert that this is so.

llvm-svn: 197780
2013-12-20 04:34:22 +00:00
Eric Christopher 46e2343554 Add support for a CU to output a set of ranges for the CU. This is useful
when you want to have the full list of addresses for a particular CU or
when you have multiple modules linked together and can't depend upon the
ordering of a single CU for begin/end ranges.

llvm-svn: 197776
2013-12-20 04:16:18 +00:00
Dmitri Gribenko 8da5f7a96d When parsing data layout string looking for endianness, use the correct default
llvm-svn: 197771
2013-12-20 02:54:35 +00:00
Dmitri Gribenko 5362ad579e Correctly apply the default pointer size
llvm-svn: 197770
2013-12-20 02:46:23 +00:00
Eric Christopher c0a5aaeab0 [x86] Rename In32BitMode predicate to Not64BitMode
That's what it actually means, and with 16-bit support it's going to be
a little more relevant since in a few corner cases we may actually want
to distinguish between 16-bit and 32-bit mode (for example the bare 'push'
aliases to pushw/pushl etc.)

Patch by David Woodhouse

llvm-svn: 197768
2013-12-20 02:04:49 +00:00
Alp Toker 171b0c36a3 Fix documentation typos
llvm-svn: 197757
2013-12-20 00:33:39 +00:00
Kevin Enderby 36eba25fee Un-revert: the buildbot failure in LLVM on lld-x86_64-win7 had me with
this commit as the only one on the Blamelist so I quickly reverted this.
However it was actually Nick's change who has since fixed that issue.

Original commit message:

Changed the X86 assembler for intel syntax to work with directional labels.

The X86 assembler as a separate code to parser the intel assembly syntax
in X86AsmParser::ParseIntelOperand().  This did not parse directional labels.
And if something like 1f was used as a branch target it would get an
"Unexpected token" error.

The fix starts in X86AsmParser::ParseIntelExpression() in the case for
AsmToken::Integer, it needs to grab the IntVal from the current token
then look for a 'b' or 'f' following an Integer.  Then it basically needs to
do what is done in AsmParser::parsePrimaryExpr() for directional
labels.  It saves the MCExpr it creates in the IntelExprStateMachine
in the Sym field.

When it returns to X86AsmParser::ParseIntelOperand() it looks
for a non-zero Sym field in the IntelExprStateMachine and if
set it creates a memory operand not an immediate operand
it would normally do for the Integer.

rdar://14961158

llvm-svn: 197744
2013-12-19 23:16:14 +00:00
Rafael Espindola 458a4851dd Change getStringRepresentation to skip defaults.
I have a pending change for clang to use getStringRepresentation to check
that its DataLayout is in sync with llvm's.

getStringRepresentation is not called from llvm itself, so far it is mostly
a debugging aid, so the shorter strings are an independent improvement.

llvm-svn: 197740
2013-12-19 23:03:03 +00:00
David Peixotto 52303f6ed3 Ensure deterministic when printing ARM assembler constant pools
We dump any non-empty assembler constant pools after a successful
parse of an assembly file that uses the ldr pseudo opcode. These
per-section constant pools should be output in a deterministic order
to ensure that we always generate the same output when printing the
output with an AsmStreamer.

This patch changes the map data struture used to associate a section
with its constant pool to a MapVector to ensure deterministic
output. Because this map type does not support deletion, we now
check that the constant pool is not empty before dumping its entries
and clear the entries after emitting them with the streamer.

llvm-svn: 197735
2013-12-19 22:41:56 +00:00
Kevin Enderby d6f2a63791 Revert my change to the X86 assembler for intel syntax to work with
directional labels.  Because it doesn't work for windows :)

llvm-svn: 197731
2013-12-19 22:24:09 +00:00
Kevin Enderby 592d3ac226 Changed the X86 assembler for intel syntax to work with directional labels.
The X86 assembler has a separate code to parser the intel assembly syntax
in X86AsmParser::ParseIntelOperand().  This did not parse directional labels.
And if something like 1f was used as a branch target it would get an
"Unexpected token" error.

The fix starts in X86AsmParser::ParseIntelExpression() in the case for
AsmToken::Integer, it needs to grab the IntVal from the current token
then look for a 'b' or 'f' following the Integer.  Then it basically needs to
do what is done in AsmParser::parsePrimaryExpr() for directional
labels.  It saves the MCExpr it creates in the IntelExprStateMachine
in the Sym field.

When it returns to X86AsmParser::ParseIntelOperand() it looks
for a non-zero Sym field in the IntelExprStateMachine and if
set it creates a memory operand not an immediate operand
it would normally do for the Integer.

rdar://14961158

llvm-svn: 197728
2013-12-19 22:02:03 +00:00
Hans Wennborg fabf8bfdea Make sys::ThreadLocal<> zero-initialized on non-thread builds (PR18205)
According to the docs, ThreadLocal<>::get() should return NULL
if no object has been set. This patch makes that the case also for non-thread
builds and adds a very basic unit test to check it.

(This was causing PR18205 because PrettyStackTraceHead didn't get zero-
initialized and we'd crash trying to read past the end of that list. We didn't
notice this so much on Linux since we'd crash after printing all the entries,
but on Mac we print into a SmallString, and would crash before printing that.)

llvm-svn: 197718
2013-12-19 20:32:44 +00:00
Kay Tiong Khoo e37d52095e Stay classy (and legal) LLVM. Remove links to 3rd party SMT solver whose links may not be permanent.
llvm-svn: 197713
2013-12-19 18:35:54 +00:00
Quentin Colombet 90a646e4d1 [X86][fast-isel] Fix select lowering.
The condition in selects is supposed to be i1.
Make sure we are just reading the less significant bit
of the 8 bits width value to match this constraint.

<rdar://problem/15651765>

llvm-svn: 197712
2013-12-19 18:32:04 +00:00
David Peixotto 80c083a678 Implement the .ltorg directive for ARM assembly
This directive will write out the assembler-maintained constant
pool for the current section. These constant pools are created to
support the ldr-pseudo instruction (e.g. ldr r0, =val).

The directive can be used by the programmer to place the constant
pool in a location that can be reached by a pc-relative offset in
the ldr instruction.

llvm-svn: 197711
2013-12-19 18:26:07 +00:00
David Peixotto e407d093e8 Implement the ldr-pseudo opcode for ARM assembly
The ldr-pseudo opcode is a convenience for loading 32-bit constants.
It is converted into a pc-relative load from a constant pool. For
example,

  ldr r0, =0x10001
  ldr r1, =bar

will generate this output in the final assembly

  ldr r0, .Ltmp0
  ldr r1, .Ltmp1
  ...
  .Ltmp0: .long 0x10001
  .Ltmp1: .long bar

Sketch of the LDR pseudo implementation:
  Keep a map from Section => ConstantPool

  When parsing ldr r0, =val
    parse val as an MCExpr
    get ConstantPool for current Section
    Label = CreateTempSymbol()
    remember val in ConstantPool at next free slot
    add operand to ldr that is MCSymbolRef of Label

  On finishParse() callback
    Write out all non-empty constant pools
    for each Entry in ConstantPool
      Emit Entry.Label
      Emit Entry.Value

Possible improvements to be added in a later patch:
  1. Does not convert load of small constants to mov
     (e.g. ldr r0, =0x1 => mov r0, 0x1)
  2. Does reuse constant pool entries for same constant

The implementation was tested for ARM, Thumb1, and Thumb2 targets on
linux and darwin.

llvm-svn: 197708
2013-12-19 18:12:36 +00:00
David Peixotto 308e7e4367 Add a finishParse() callback to the targer asm parser
This callback is invoked when the parse has finished successfuly. It
will be used to write out ARM constant pools to implement the ldr
pseudo.

llvm-svn: 197706
2013-12-19 18:08:08 +00:00
Kay Tiong Khoo a570b5adb5 Improved fix for PR17827 (instcombine of shift/and/compare).
This change fixes the case of arithmetic shift right - do not attempt to fold that case.
This change also relaxes the conditions when attempting to fold the logical shift right and shift left cases.

No additional IR-level test cases included at this time. See http://llvm.org/bugs/show_bug.cgi?id=17827 for proofs that these are correct transformations.

llvm-svn: 197705
2013-12-19 18:07:17 +00:00
Rafael Espindola 4fa79758b7 Small simplification, p0 is the same as p.
llvm-svn: 197699
2013-12-19 16:51:03 +00:00
Zoran Jovanovic 8e918c3c4d Support for microMIPS control instructions.
llvm-svn: 197696
2013-12-19 16:25:00 +00:00
Rafael Espindola 9ec26f395b Long doubles are required to be aligned to 128 bits and svr4 32 bits.
Clang was already getting this right.

llvm-svn: 197694
2013-12-19 16:23:59 +00:00
Hal Finkel 2345347eb9 Add a disassembler to the PowerPC backend
The tests for the disassembler were adapted from the encoder tests, and for the
most part, the output from the disassembler matches that encoder-test inputs.
There are some places where more-informative mnemonics could be produced
(notably for the branch instructions), and those cases are noted in the tests
with FIXMEs.

Future work includes:

 - Generating more-informative mnemonics when possible (this may also be done
   in the printer).

 - Remove the dependence on positional "numbered" operand-to-variable mapping
   (for both encoding and decoding).

 - Internally using 64-bit instruction variants in 64-bit mode (if this turns
   out to matter).

llvm-svn: 197693
2013-12-19 16:13:01 +00:00
Zoran Jovanovic ff9d5f3284 Support for microMIPS LL and SC instructions.
llvm-svn: 197692
2013-12-19 16:12:56 +00:00
Zoran Jovanovic 69be811a6e Support for microMIPS TLS relocations.
llvm-svn: 197685
2013-12-19 16:02:32 +00:00
Evgeniy Stepanov a284e559d7 [dfsan] Simplify code after r197677.
llvm-svn: 197679
2013-12-19 14:37:03 +00:00
Evgeniy Stepanov a9164e9e2a Add an explicit insert point argument to SplitBlockAndInsertIfThen.
Currently SplitBlockAndInsertIfThen requires that branch condition is an
Instruction itself, which is very inconvenient, because it is sometimes an
Operator, or even a Constant.

llvm-svn: 197677
2013-12-19 13:29:56 +00:00
NAKAMURA Takumi 6e3c4235be GCOV.cpp: Fix format strings, %lf. Don't use %lf to double.
llvm-svn: 197663
2013-12-19 08:46:28 +00:00
Matt Arsenault a98cd6a56e R600/SI: Make private pointers be 32-bit.
Different sized address spaces should theoretically work
most of the time now, and since 64-bit add is currently
disabled, using more 32-bit pointers fixes some cases.

llvm-svn: 197659
2013-12-19 05:32:55 +00:00
Saleem Abdulrasool c0da2cb3b4 ARM IAS: support .inst directive
This adds support for the .inst directive.  This is an ARM specific directive to
indicate an instruction encoded as a constant expression.  The major difference
between .word, .short, or .byte and .inst is that the latter will be
disassembled as an instruction since it does not get flagged as data.

llvm-svn: 197657
2013-12-19 05:17:58 +00:00
Josh Magee 22b8ba2d67 [stackprotector] Use analysis from the StackProtector pass for stack layout in PEI a nd LocalStackSlot passes.
This changes the MachineFrameInfo API to use the new SSPLayoutKind information
produced by the StackProtector pass (instead of a boolean flag) and updates a
few pass dependencies (to preserve the SSP analysis).

The stack layout follows the same approach used prior to this change - i.e.,
only LargeArray stack objects will be placed near the canary and everything
else will be laid out normally.  After this change, structures containing large
arrays will also be placed near the canary - a case previously missed by the
old implementation.

Out of tree targets will need to update their usage of
MachineFrameInfo::CreateStackObject to remove the MayNeedSP argument. 

The next patch will implement the rules for sspstrong and sspreq.  The end goal
is to support ssp-strong stack layout rules.

WIP.

Differential Revision: http://llvm-reviews.chandlerc.com/D2158

llvm-svn: 197653
2013-12-19 03:17:11 +00:00
Rafael Espindola 2fc7101e3c Add stack alignment information for Sparc.
This matches the data in clang which was added by Jakob Stoklund Olesen in
r179596.

Thanks for erikjv on irc for pointing me to the relevant documents:
http://sparc.com/standards/64.psabi.1.35.ps.Z
page 25: Every stack frame must be 16-byte aligned.

http://sparc.com/standards/psABI3rd.pdf
page 3-10: Although the architecture requires only word alignment, software convention and the operating system require every stack frame to be doubleword aligned.

I tried to add a test, but it looks like sparc doesn't implement dynamic stack
realignment. This will be tested in clang shortly.

llvm-svn: 197646
2013-12-19 02:21:16 +00:00
Reid Kleckner a534a38130 Begin adding docs and IR-level support for the inalloca attribute
The inalloca attribute is designed to support passing C++ objects by
value in the Microsoft C++ ABI.  It behaves the same as byval, except
that it always implies that the argument is in memory and that the bytes
are never copied.  This attribute allows the caller to take the address
of an outgoing argument's memory and execute arbitrary code to store
into it.

This patch adds basic IR support, docs, and verification.  It does not
attempt to implement any lowering or fix any possibly broken transforms.

When this patch lands, a complete description of this feature should
appear at http://llvm.org/docs/InAlloca.html .

Differential Revision: http://llvm-reviews.chandlerc.com/D2173

llvm-svn: 197645
2013-12-19 02:14:12 +00:00
Rafael Espindola ddb913cc8f Synchronize the NaCl DataLayout strings with the ones in clang.
Patch by Derek Schuff.

llvm-svn: 197640
2013-12-19 00:44:37 +00:00
Reed Kotler 47f3c64a48 Make cosmetic changes as part of Mips internal post commit review of
patch r196331.

llvm-svn: 197638
2013-12-19 00:43:08 +00:00
Yuchen Wu bb6a477131 llvm-cov: Added -f option for function summaries.
Similar to the file summaries, the function summaries output line,
branching and call statistics. The file summaries have been moved
outside the initial loop so that all of the function summaries can be
outputted before file summaries.

Also updated test cases.

llvm-svn: 197633
2013-12-19 00:29:25 +00:00
Reed Kotler 2500bd6c20 Fix a problem with mips16 stubs when calls are transformed during
tail call optimization. Some more work may be needed for indirect
calls but this patch fixes the current regression in Prolangc++/trees.
S2 optimization as part of the general cleanup and optimization
of prolog and epilog was not saving S2 in this case and needed to.

llvm-svn: 197630
2013-12-18 23:57:48 +00:00
Weiming Zhao 63871d255f [aarch32] fix bug 18268: Incorrect condition of vsel
Given vsel_cc, op1, op2, since vsel has no LE/LT, to generate vsel for
such selection, it needs to inverse cc and swap op1 and op2. To inverse
cc, both L/G and E bits should be flipped.

llvm-svn: 197615
2013-12-18 22:25:17 +00:00
Adrian Prantl 99c7af26b7 Debug info: Implement (rvalue) reference qualifiers for C++11 non-static
member functions. Paired commit with CFE.

rdar://problem/15356637

llvm-svn: 197613
2013-12-18 21:48:19 +00:00
Adrian Prantl 31631e4a47 Pull in a couple of new constants from the upcoming DWARF 5 standard.
llvm-svn: 197611
2013-12-18 21:48:14 +00:00
Rafael Espindola 84a8726a31 Correctly handle the degenerated triple "thumb".
Fixes a crash in llc where some parts think the target is thumb and others think
it is ARM.

llvm-svn: 197607
2013-12-18 21:29:44 +00:00
Yuchen Wu 8256ee6d4a llvm-cov: Print coverage summary to STDOUT.
File summaries will now be optionally outputted which will give line,
branching and call coverage info. Unfortunately, clang's current
instrumentation does not give enough information to deduce function
calls, something that gcc is able to do. Thus, no calls are always
outputted to be consistent with gcov output.

Also updated tests.

llvm-svn: 197606
2013-12-18 21:12:51 +00:00
Yuchen Wu c9b2dcdbee llvm-cov: s/(.*)Executed/\1Exec/
llvm-svn: 197595
2013-12-18 18:46:25 +00:00
Yuchen Wu 73dc38187b llvm-cov: Added -c option for branch counts.
This will cause llvm-cov to output branch counts instead of branch
probabilities. -b must be enabled.

Also updated tests.

llvm-svn: 197594
2013-12-18 18:40:15 +00:00
Logan Chien a39510aeaa [arm] Rename Tag_VFP_arch to Tag_FP_arch.
According to "Addenda to ABI for ARM architecture", Tag_FP_arch is the
new name for the equivalent Tag_VFP_arch.  This commit renames
Tag_VFP_arch to Tag_FP_arch.

llvm-svn: 197587
2013-12-18 17:23:15 +00:00
Rafael Espindola 988f35e999 Fix f64 and f128 for ppc-darwin.
This patch adds -f64:32:64 to 32 bit ppc darwin since a f64 inside a
structure are only 32 bit aligned.

The patch also drop -f128:64:128 from all ppc darwin, since f128 is
128 bit aligned.

llvm-svn: 197574
2013-12-18 15:06:25 +00:00
Rafael Espindola 382ee385fd One ppc32-darwin, a i64 inside a structure can have 32 bit alignment.
Thanks for Iain Sandoe for testing this with the original gcc.

Clang was already getting this right.

llvm-svn: 197572
2013-12-18 14:35:37 +00:00
Tim Northover f1c31b95e0 ARM: update comment to match reality
llvm-svn: 197570
2013-12-18 14:18:36 +00:00
Tobias Grosser 84db1e744d DiagnosticInfo: Add missing namespace
llvm-svn: 197556
2013-12-18 10:12:06 +00:00
Tim Northover 44594ad7e2 ARM: set default float ABI based on triple.
Clang sets the float-abi target option manually, but no longer
annotates each function with its ABI. This can lead to confusing
mistmatch between "clang -emit-llvm | llc" and normal clang
invocations.

Besides which, gnueabihf actually *is* hard-float. Defaulting to soft
was just perverse.

llvm-svn: 197554
2013-12-18 09:27:33 +00:00
Kevin Qin 53eaea0104 [AArch64 NEON]Implment loading vector constant form constant pool.
llvm-svn: 197551
2013-12-18 06:26:04 +00:00
Saleem Abdulrasool 88186c49c5 AsmParser: add support for .end directive
The .end directive indicates the end of the file.  No further instructions are
processed after a .end directive is encountered.

One potential (glaringly obvious) optimisation that could be pursued here is to
extend MCAsmParser with a DiscardRemainder method to avoid processing lexemes to
the end of the file.  It was unclear at this point if that would be worth
adding, and could easily be added in a follow on change.

Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org>
llvm-svn: 197547
2013-12-18 02:53:03 +00:00
David Blaikie 47f615eae5 DebugInfo: Introduce new DIValue, DIETypeSignature to encode references to type units via their signatures
This simplifies type unit and type unit reference creation as well as
setting the stage for inter-type hashing across type unit boundaries.

llvm-svn: 197539
2013-12-17 23:32:35 +00:00
Rafael Espindola febb8d2b96 Fix N32 registers and stack alignment.
This patch fixes the "n" and "S" components of the data layout for mips. Clang
already gets this right.

This will be tested in clang.

llvm-svn: 197536
2013-12-17 23:15:58 +00:00
Hal Finkel b4b99e545b Eliminate PPC instruction decoding ambiguities
The instruction definitions in the PPC backend have a number of variants
defined for the same instruction to represent differences between 64-bit and
32-bit semantics. In order to generate a disassembler for the PPC backend, we
need to mark all but one of these as CodeGen only.

No functionality change intended; this is prep work for PPC disassembly
support.

llvm-svn: 197535
2013-12-17 23:05:18 +00:00
Quentin Colombet 98e79a0604 [DiagnosticPrinter] Use the appropriate method to print a Twine object in a
raw_ostream.

llvm-svn: 197531
2013-12-17 22:35:07 +00:00
Reid Kleckner d4e53f55f1 MC COFF: Emit the 'b' section flag for .bss sections in GNU assembly
Without this, assembling clang's disassembly would produce an object
file with the IMAGE_SCN_CNT_INITIALIZED_DATA section characteristic
rather than the uninitialized one.  link.exe would warn when merging
comdats with different flags.

llvm-svn: 197529
2013-12-17 22:12:40 +00:00
Rafael Espindola 8c08120dba On APCS, only try to align aggregates to 32 bits instead of 64.
This matches clang's behavior and since it is only a preference, it is not
an ABI issue.

llvm-svn: 197526
2013-12-17 21:36:54 +00:00
Rafael Espindola 9704fd03d1 Handle i64 first for clarity. No functionality change.
llvm-svn: 197524
2013-12-17 21:28:36 +00:00
Duncan P. N. Exon Smith ab5dbebc11 Assert that the last operand is actually EFLAGS
This is another follow-up to r197503, after a post-commit review by
Andy.

<rdar://problem/15627766>

llvm-svn: 197520
2013-12-17 20:28:21 +00:00
Andrew Trick e4083f9e85 Disabled subregister copy coalescing during MachineCSE.
This effectively backs out r197465 but leaves some of the general
fixes in place. Not all targets are ready to handle this feature. To
enable it, some infrastructure work is needed to better handle
register class constraints.

llvm-svn: 197514
2013-12-17 19:29:36 +00:00
Quentin Colombet b4c44d239c Add warning capabilities in LLVM.
This reapplies r197438 and fixes the link-time circular dependency between
IR and Support. The fix consists in moving the diagnostic support into IR.

The patch adds a new LLVMContext::diagnose that can be used to communicate to
the front-end, if any, that something of interest happened.
The diagnostics are supported by a new abstraction, the DiagnosticInfo class.
The base class contains the following information:
- The kind of the report: What this is about.
- The severity of the report: How bad this is.

This patch also adds 2 classes:
- DiagnosticInfoInlineAsm: For inline asm reporting. Basically, this diagnostic
will be used to switch to the new diagnostic API for LLVMContext::emitError.
- DiagnosticStackSize: For stack size reporting. Comes as a replacement of the
hard coded warning in PEI.

This patch also features dynamic diagnostic identifiers. In other words plugins
can use this infrastructure for their own diagnostics (for more details, see
getNextAvailablePluginDiagnosticKind).

This patch introduces a new DiagnosticHandlerTy and a new DiagnosticContext in
the LLVMContext that should be set by the front-end to be able to map these
diagnostics in its own system.

http://llvm-reviews.chandlerc.com/D2376
<rdar://problem/15515174>

llvm-svn: 197508
2013-12-17 17:47:22 +00:00
Matheus Almeida 8cc8b35a73 [mips] Fix off by one issue when applying a fixup.
The branch offset for a R_MIPS_PC16 relocation is indeed a 16-bit signed
immediate.

llvm-svn: 197506
2013-12-17 17:10:00 +00:00
Duncan P. N. Exon Smith 512601d77f Revert "Revert "Mark vastart_save_xmm_regs as changing EFLAGS""
This reverts commit r197481, recommiting r197469 with an extra fix.

The vastart_save_xmm_regs pseudo-instruction expands to a test and a
branch, so it modifies EFLAGS.  Mark it so, or else the scheduler might
place it in the middle of another test+branch.

This fixes a bug exposed by r192750, which changed the initial scheduler
to source-order as part of enabling the MI Scheduler for X86.

This re-commit changes the VASTART_SAVE_XMM_REGS custom inserter not to
try to save %flags, and adds a test that catches the bad behavior of
r197469.

<rdar://problem/15627766>

llvm-svn: 197503
2013-12-17 15:54:45 +00:00
Rafael Espindola 345d718d16 Fix the pointer size for the PS3 datalayout.
This will be tested from clang.

llvm-svn: 197501
2013-12-17 15:29:48 +00:00
Stepan Dyatkovskiy 7f7c2710e0 Fix for PR18045:
http://llvm.org/bugs/show_bug.cgi?id=18045

Short issue description:
For X86 machines with sse < sse4.1 we got failures for some
particular load/store vector sequences:

$ clang-trunk -m32 -O2 test-case.c
fatal error: error in backend: Cannot select: 0x4200920: v4i32,ch = load 0x41d6ab0, 0x4205850,
      0x41dcb10<LD16[getelementptr inbounds ([4 x i32]* @e, i32 0, i32 0)](align=4)> [ORD=82]
      [ID=58]
  0x4205850: i32 = X86ISD::Wrapper 0x41d5490 [ORD=26] [ID=43]
    0x41d5490: i32 = TargetGlobalAddress<[4 x i32]* @e> 0 [ORD=26] [ID=23]
  0x41dcb10: i32 = undef [ID=2]

The reason is that EltsFromConsecutiveLoads could emit such load instruction
both before and after legalize stage. Though this instruction is not legal for
machines with SSSE3 and lower.

The fix: In EltsFromConsecutiveLoads, if we have passed legalize stage, we
check whether nodes it emits are legal. 

P.S.: If you get failure in time from 12:00 and till 22:00 (UTC-8),
perhaps I'll slow with response, so you better reject this commit. Thanks!

llvm-svn: 197492
2013-12-17 12:07:33 +00:00
Yaron Keren 7da8e45b57 There are no __register_frame and __deregister_frame functions
when using structured exception handling (SEH) on Windows 64.

http://llvm-reviews.chandlerc.com/D2378

Patch by Jonathan Liu!

llvm-svn: 197483
2013-12-17 08:40:11 +00:00
Elena Demikhovsky c5f6726a24 AVX-512: Added implementation of CONCAT_VECTORS for v8i1 vectors (by Alexey Bader).
Added implementation of "truncate" from integer type (i64/i32/i16/i8) to i1.

llvm-svn: 197482
2013-12-17 08:33:15 +00:00
Duncan P. N. Exon Smith b2d4274d3f Revert "Mark vastart_save_xmm_regs as changing EFLAGS"
This reverts commit r197469.

The sanitizer and dragonegg buildbots are failing, I think because of
this change.  Reverting until I figure out why.

llvm-svn: 197481
2013-12-17 07:13:58 +00:00
Duncan P. N. Exon Smith a4acde39e9 Mark vastart_save_xmm_regs as changing EFLAGS
The vastart_save_xmm_regs pseudo-instruction expands to a test and a
branch, so it modifies EFLAGS.  Mark it so, or else the scheduler might
place it in the middle of another test+branch.

This fixes a bug exposed by r192750, which turned on the MI Scheduler
for X86.

<rdar://problem/15627766>

llvm-svn: 197469
2013-12-17 06:12:05 +00:00
Andrew Trick e339828b90 Allow MachineCSE to coalesce trivial subregister copies the same way that it coalesces normal copies.
Without this, MachineCSE is powerless to handle redundant operations with truncated source operands.

This required fixing the 2-addr pass to handle tied subregisters. It isn't clear what combinations of subregisters can legally be tied, but the simple case of truncated source operands is now safely handled:

     %vreg11<def> = COPY %vreg1:sub_32bit; GR32:%vreg11 GR64:%vreg1
     %vreg12<def> = COPY %vreg2:sub_32bit; GR32:%vreg12 GR64:%vreg2
     %vreg13<def,tied1> = ADD32rr %vreg11<tied0>, %vreg12<kill>, %EFLAGS<imp-def>

Test case: cse-add-with-overflow.ll.

This exposed an existing bug in
PPCInstrInfo::commuteInstruction. Thanks to Rafael for the test case:
PowerPC/crash.ll.

llvm-svn: 197465
2013-12-17 04:50:45 +00:00
Andrew Trick 9defbd882b whitespace
llvm-svn: 197464
2013-12-17 04:50:40 +00:00
Jim Grosbach 04caa27387 Make comment more explicit.
Re-reading the comment I updated in previous commit, it's better to make
it more explicit and avoid ambiguity more effectively.

llvm-svn: 197458
2013-12-17 02:18:02 +00:00
Jim Grosbach dde043b3fd Typo. s/reserved/preserved/
llvm-svn: 197457
2013-12-17 02:01:13 +00:00
Jim Grosbach ea2db453dd Add a machine code print in DEBUG() following instruction selection.
Make debugging ISel a bit easier by printing out a dump of the generated
code at the end.

llvm-svn: 197456
2013-12-17 02:01:10 +00:00
Quentin Colombet 382b135d92 Revert r197438 and r197447 until we figure out how to avoid circular dependency at link time
llvm-svn: 197451
2013-12-17 01:19:59 +00:00
Arnold Schwaighofer 50b8302c55 LoopVectorizer: Don't if-convert constant expressions that can trap
A phi node operand or an instruction operand could be a constant expression that
can trap (division). Check that we don't vectorize such cases.

PR16729
radar://15653590

llvm-svn: 197449
2013-12-17 01:11:01 +00:00
Quentin Colombet 0caf4fef47 [LLVM Diagnostic Capabilities] Remove useless includes from
DiagnosticPrinter.cpp.
These was creating a link time dependencies of IR on CodeGen and Analysis.

Part of <rdar://problem/15515174>

llvm-svn: 197447
2013-12-17 00:56:19 +00:00
Quentin Colombet 66673f4075 Add warning capabilities in LLVM.
The patch adds a new LLVMContext::diagnose that can be used to communicate to
the front-end, if any, that something of interest happened.
The diagnostics are supported by a new abstraction, the DiagnosticInfo class.
The base class contains the following information:
- The kind of the report: What this is about.
- The severity of the report: How bad this is.

This patch also adds 2 classes:
- DiagnosticInfoInlineAsm: For inline asm reporting. Basically, this diagnostic
will be used to switch to the new diagnostic API for LLVMContext::emitError.
- DiagnosticStackSize: For stack size reporting. Comes as a replacement of the
hard coded warning in PEI.

This patch also features dynamic diagnostic identifiers. In other words plugins
can use this infrastructure for their own diagnostics (for more details, see
getNextAvailablePluginDiagnosticKind).

This patch introduces a new DiagnosticHandlerTy and a new DiagnosticContext in
the LLVMContext that should be set by the front-end to be able to map these
diagnostics in its own system.

http://llvm-reviews.chandlerc.com/D2376
<rdar://problem/15515174>

llvm-svn: 197438
2013-12-16 23:22:51 +00:00
Yi Jiang 6ab044ee35 Enable double to float shrinking optimizations for binary functions like 'fmin/fmax'. Fix radar:15283121
llvm-svn: 197434
2013-12-16 22:42:40 +00:00
Yuchen Wu 66d93b82ac llvm-cov: Added -u option for unconditional branch info.
Outputs branch information for unconditional branches in addition to
conditional branches. -b option must be enabled.

Also updated tests.

llvm-svn: 197432
2013-12-16 22:14:02 +00:00
Juergen Ributzka 9ed985baad [Stackmap] Allow WebKit_JS calling convention to store 4 byte sized and aligned arguments.
This allows the WebKit_JS calling convention to perform partial writes on a 4
byte granularity to stack slots.

llvm-svn: 197431
2013-12-16 22:05:32 +00:00
Matt Arsenault cb34f84e39 Fix typo in instruction name.
SI_KIL -> SI_KILL

llvm-svn: 197425
2013-12-16 20:58:33 +00:00
Rafael Espindola f152836788 Revert "Allow MachineCSE to coalesce trivial subregister copies the same way that it coalesces normal copies."
This reverts commit r197414.

It broke the ppc64 bootstrap. I will post a testcase in a sec.

llvm-svn: 197424
2013-12-16 20:57:09 +00:00
Yuchen Wu 8742a28560 llvm-cov: Removed extra semicolon from ;;.
llvm-svn: 197418
2013-12-16 20:03:11 +00:00
Juergen Ributzka b1612c18ab [Stackmap] The first integer argument is passed in register for the WebKit_JS calling convention.
Pass the first integer argument (callee) in register to optimize inline caches.

llvm-svn: 197416
2013-12-16 19:53:31 +00:00
Andrew Trick 88bd8629b2 Allow MachineCSE to coalesce trivial subregister copies the same way
that it coalesces normal copies.

Without this, MachineCSE is powerless to handle redundant operations
with truncated source operands.

This required fixing the 2-addr pass to handle tied subregisters. It
isn't clear what combinations of subregisters can legally be tied, but
the simple case of truncated source operands is now safely handled:

     %vreg11<def> = COPY %vreg1:sub_32bit; GR32:%vreg11 GR64:%vreg1
     %vreg12<def> = COPY %vreg2:sub_32bit; GR32:%vreg12 GR64:%vreg2
     %vreg13<def,tied1> = ADD32rr %vreg11<tied0>, %vreg12<kill>, %EFLAGS<imp-def>

llvm-svn: 197414
2013-12-16 19:36:21 +00:00
Andrew Trick cccd82f21f whitespace
llvm-svn: 197413
2013-12-16 19:36:18 +00:00
Rafael Espindola e89b41495a One last cleanup of LLVM's DataLayout strings.
Produce them in the same order on every target. The order is that of
getStringRepresentation: e|E-i*-f*-v*-a*-s*-n*-S*.

llvm-svn: 197411
2013-12-16 19:31:14 +00:00
Rafael Espindola 0eb1ebeaac Structure R600's computeDataLayout more like every other target.
While there, simplify "p3:32:32:32" to "p3:32:32".

llvm-svn: 197407
2013-12-16 19:18:57 +00:00
Joerg Sonnenberger 8fe41b7319 Recognize EABIHF as environment and use it for RTAPI + VFP.
llvm-svn: 197405
2013-12-16 18:51:28 +00:00
Chad Rosier 5f87edb484 [AArch64] Fix v1fx patterns for Floating-point Multiply Extend and Floating-point Compare to Zero.
llvm-svn: 197402
2013-12-16 18:29:35 +00:00
Reid Kleckner 86a8e1e0e4 MemoryBuffer: Increase the alignment of small file buffers to 16
This was manifesting as an LLVM_ASSUME_ALIGNED() failure in an ELF debug
info test when building LLVM with clang in the Microsoft C++ ABI.

llvm-svn: 197401
2013-12-16 18:18:12 +00:00
Rafael Espindola bccb9d45ad The preferred alignment defaults to the abi alignment. Omit if it is the same.
llvm-svn: 197400
2013-12-16 18:01:51 +00:00
Rafael Espindola f057093fdc Don't duplicate the DataLayout defaults for integer, floats and vectors.
llvm-svn: 197398
2013-12-16 17:41:15 +00:00
Rafael Espindola 8afbb28cea On DataLayout, omit the default of p:64:64:64.
llvm-svn: 197397
2013-12-16 17:15:29 +00:00
Hal Finkel 0a576d52fa Set has_asmparser in PowerPC/LLVMBuild.txt
PowerPC now has an asm parser (and has for many months now); indicate this in
PowerPC/LLVMBuild.txt.

llvm-svn: 197393
2013-12-16 15:48:09 +00:00
Elena Demikhovsky 47fc44e52e AVX-512: Added legal type MVT::i1 and VK1 register for it.
Added scalar compare VCMPSS, VCMPSD.
Implemented LowerSELECT for scalar FP operations.
I replaced FSETCCss, FSETCCsd with one node type FSETCCs.
Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.

llvm-svn: 197384
2013-12-16 13:52:35 +00:00
Evgeniy Stepanov a1df6379a6 Fix Android regression in r197332.
llvm-svn: 197366
2013-12-16 07:02:51 +00:00
Hao Liu 774cabb538 [AArch64]Fix the pattern match failure for v1i8/v1i16/v1i32 types.
Currently we have such types as legal vector types. The DAG combiner may generate some DAG nodes having such types but we don't have patterns to match them.
E.g. a load i32 and a bitcast i32 to v1i32 will be combined into a load v1i32:
     bitcast (load i32) to v1i32 -> load v1i32.
So this patch fixes such problems for load/dup instructions.
If v1i8/v1i16/v1i32 are not legal any more, the code in this patch can be deleted. So I also add some FIXME.

llvm-svn: 197361
2013-12-16 02:51:28 +00:00
Reed Kotler b69ea1e92e remove an uneeded statement (condition is covered by the statement
that follows).

llvm-svn: 197358
2013-12-15 23:33:59 +00:00
Reed Kotler 06b3c4f484 Fix some indentation.
llvm-svn: 197357
2013-12-15 23:03:35 +00:00
Reed Kotler 4d030b4e89 Get rid of an superfluous tab in the .s file. This was originally
part of a multi-line pseudo which worked around a linker bug for mips16.

llvm-svn: 197356
2013-12-15 22:02:31 +00:00
Reed Kotler 5c29d63a66 Last change for mips16 prolog/epilog cleanup and optimization.
Some tiny cosmetic code changes to follow. Because of the wide
ranging nature of the patch a full 24 test cycle was needed to
check against regression. This was the smallest patch I could
make to progress from the earlier ones in the series. 

llvm-svn: 197350
2013-12-15 20:49:30 +00:00
Joerg Sonnenberger ddb582896a There is no exp10 on NetBSD.
llvm-svn: 197348
2013-12-15 20:36:17 +00:00
Michael Kuperstein e31b486cdd Fix AsmWriter's handling of SPIR calling conventions. Patch by Boaz Ouriel.
llvm-svn: 197335
2013-12-15 10:01:20 +00:00
Joerg Sonnenberger 7466979f20 Replace string matching with a switch on Triple::getEnvironment.
llvm-svn: 197332
2013-12-15 00:12:52 +00:00
Juergen Ributzka c26b68a94f [Stackmap] Refactor operand parsing.
llvm-svn: 197329
2013-12-14 23:06:19 +00:00
Matt Arsenault 52226f9a8e Don't manually calculate size in bytes
llvm-svn: 197327
2013-12-14 18:21:59 +00:00
Iain Sandoe e0b4cb62f5 [Powerpc darwin] AsmParser Base implementation.
This is a base implementation of the powerpc-apple-darwin asm parser dialect.

* Enables infrastructure (essentially isDarwin()) and fixes up the parsing of asm directives to separate out ELF and MachO/Darwin additions.
* Enables parsing of {r,f,v}XX as register identifiers.
* Enables parsing of lo16() hi16() and ha16() as modifiers.

The changes to the test case are from David Fang (fangism).

llvm-svn: 197324
2013-12-14 13:34:02 +00:00
Juergen Ributzka db9ee00b59 Remove weak vtables. No functional change.
llvm-svn: 197323
2013-12-14 12:23:14 +00:00
Juergen Ributzka e82947539e [Stackmap] Liveness Analysis Pass
This optional register liveness analysis pass can be enabled with either
-enable-stackmap-liveness, -enable-patchpoint-liveness, or both. The pass
traverses each basic block in a machine function. For each basic block the
instructions are processed in reversed order and if a patchpoint or stackmap
instruction is encountered the current live-out register set is encoded as a
register mask and attached to the instruction.

Later on during stackmap generation the live-out register mask is processed and
also emitted as part of the stackmap.

This information is optional and intended for optimization purposes only. This
will enable a client of the stackmap to reason about the registers it can use
and which registers need to be preserved.

Reviewed by Andy

llvm-svn: 197317
2013-12-14 06:53:06 +00:00
Juergen Ributzka 36f4619753 [Stackmap] Only the AnyReg calling convention should preserve all registers.
llvm-svn: 197316
2013-12-14 06:52:59 +00:00
Juergen Ributzka 310034e166 Convert register liveness tracking to work on a sub-register level instead of just register units.
Reviewed by Andy

llvm-svn: 197315
2013-12-14 06:52:56 +00:00
Rafael Espindola 456f047546 Refactor NVPTX's computeDataLayout.
No functionality change.

llvm-svn: 197312
2013-12-14 06:42:48 +00:00
Rafael Espindola 307d7abc7f Turn NVPTXSubtarget::getDataLayout into a static function.
No functionality change.

llvm-svn: 197311
2013-12-14 06:36:30 +00:00
Rafael Espindola ceb0c4962a Turn AMDGPUSubtarget::getDataLayout into a static function.
No functionality change.

llvm-svn: 197310
2013-12-14 06:13:44 +00:00
Michael Gottesman 5e985ee5b5 [block-freq] Rename getEntryFrequency() -> getEntryFreq() to match getBlockFreq() in all *BlockFrequencyInfo*.
llvm-svn: 197304
2013-12-14 02:37:38 +00:00
Michael Gottesman fb9164f0d2 [block-freq] Teach branch probability how to return the edge weight in between a BasicBlock and one of its successors.
IMHO At some point BasicBlock should be refactored along the lines of
MachineBasicBlock so that successors/weights are actually embedded within the
block. Now is not that time though.

llvm-svn: 197303
2013-12-14 02:24:25 +00:00
Michael Gottesman 8f17dccdcb [block-freq] Add a right shift to BlockFrequency that saturates at 1.
llvm-svn: 197302
2013-12-14 02:24:22 +00:00
Michael Gottesman 8c79ee409a [block-freq] Remove old BlockFrequency entry frequency and printing code.
llvm-svn: 197297
2013-12-14 00:57:18 +00:00
Michael Gottesman 9f49d74413 [block-freq] Refactor LiveInterals::getSpillWeight to use the new MachineBlockFrequencyInfo methods.
This is slightly more interesting than the previous batch of changes.
Specifically:

1. We refactor getSpillWeight to take a MachineBlockFrequencyInfo (MBFI)
object. This enables us to completely encapsulate the actual manner we
use the MachineBlockFrequencyInfo to get our spill weights. This yields
cleaner code since one does not need to fetch the actual block frequency
before getting the spill weight if all one wants it the spill weight. It
also gives us access to entry frequency which we need for our
computation.

2. Instead of having getSpillWeight take a MachineBasicBlock (as one
might think) to look up the block frequency via the MBFI object, we
instead take in a MachineInstr object. The reason for this is that the
method is supposed to return the spill weight for an instruction
according to the comments around the function.

llvm-svn: 197296
2013-12-14 00:53:32 +00:00
Matt Arsenault d3ee7af2f4 Teach MemoryBuiltins about address spaces
llvm-svn: 197292
2013-12-14 00:27:48 +00:00
Michael Gottesman 092647b37a [block-freq] Store MBFI as a field on SpillPlacement so we can access it to get the entry frequency while processing data.
llvm-svn: 197291
2013-12-14 00:25:47 +00:00
Michael Gottesman b78dec8faf [block-freq] Update MachineBlockPlacement and RegAllocGreedy to use the new MachineBlockFrequencyInfo methods.
llvm-svn: 197290
2013-12-14 00:25:45 +00:00
Michael Gottesman b0c1ed8f4c [block-freq] Update BlockFrequencyInfo/MachineBlockFrequencyInfo to use the new print methods.
llvm-svn: 197289
2013-12-14 00:25:42 +00:00
Matt Arsenault 68c38fd6d1 Print the address space of a MachineMemOperand
llvm-svn: 197288
2013-12-14 00:24:02 +00:00
Michael Gottesman fd5c4b2c09 [block-freq] Add the equivalent methods to MachineBlockFrequencyInfo and BlockFrequencyInfo that were added to BlockFrequencyImpl in r197285 and r197284.
llvm-svn: 197287
2013-12-14 00:06:03 +00:00
Rafael Espindola f39136c39f Pointer sizes are stored in Bytes. Fix variables names to say so.
Also update for the current naming style.

llvm-svn: 197283
2013-12-13 23:15:20 +00:00
Kevin Enderby 651898c19f Fixed a bug in getARMFixupKindMachOInfo() where three ARM fixup kinds
were falling into the cases for 24-bit branch kinds which are not 24-bit
branches.  The routine is to return false for fixups are expected to always
be resolvable at assembly time. Which these three fixups are as they have
limited displacement and are for local references within a function.

rdar://15586725

llvm-svn: 197282
2013-12-13 22:46:54 +00:00