Commit Graph

66154 Commits

Author SHA1 Message Date
Logan Chien 05ae744813 [arm] Add softvfp to supported FPU names.
llvm-svn: 198313
2014-01-02 15:50:02 +00:00
Rafael Espindola d89b16dcb8 Make the ARM ABI selectable via SubtargetFeature.
This patch makes it possible to select the ABI with -mattr. It will be used to
forward clang's -target-abi option to llvm's CodeGen.

llvm-svn: 198304
2014-01-02 13:40:08 +00:00
Arnold Schwaighofer 0d10a9d579 BasicAA: Fix value equality and phi cycles
When there are cycles in the value graph we have to be careful interpreting
"Value*" identity as "value" equivalence. We interpret the value of a phi node
as the value of its operands.
When we check for value equivalence now we make sure that the "Value*" dominates
all cycles (phis).

%0 = phi [%noaliasval, %addr2]
%l = load %ptr
%addr1 = gep @a, 0, %l
%addr2 = gep @a, 0, (%l + 1)
store %ptr ...

Before this patch we would return NoAlias for (%0, %addr1) which is wrong
because the value of the load is from different iterations of the loop.

Tested on x86_64 -mavx at O3 and O3 -flto with no performance or compile time
regressions.

PR18068
radar://15653794

llvm-svn: 198290
2014-01-02 03:31:36 +00:00
Rafael Espindola 6994fdf33c Remove the 's' DataLayout specification
During the years there have been some attempts at figuring out how to
align byval arguments. A look at the commit log suggests that they
were

* Use the ABI alignment.
* When that was not sufficient for x86-64, I added the 's' specification to
  DataLayout.
* When that was not sufficient Evan added the virtual getByValTypeAlignment.
* When even that was not sufficient, we just got the FE to add the alignment
  to the byval.

This patch is just a simple cleanup that removes my first attempt at fixing the
problem. I also added an AArch64 implementation of getByValTypeAlignment to
make sure this patch is a nop. I also left the 's' parsing for backward
compatibility.

I will send a short email to llvmdev about the change for anyone maintaining
an out of tree target.

llvm-svn: 198287
2014-01-01 22:29:43 +00:00
Venkatraman Govindaraju 9a3da52ea2 [Sparc] Handle atomic loads/stores in sparc backend.
llvm-svn: 198286
2014-01-01 22:11:54 +00:00
Craig Topper 3321c99a06 Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables.
llvm-svn: 198284
2014-01-01 21:52:57 +00:00
Venkatraman Govindaraju 77011e861b [SparcV9]: Custom lower UMULO/SMULO so that the arguments are send to __multi3() in correct order.
llvm-svn: 198281
2014-01-01 20:22:45 +00:00
Venkatraman Govindaraju acf0233a46 [SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL does not clear top 32 bit, only SRL does.
llvm-svn: 198280
2014-01-01 19:00:10 +00:00
NAKAMURA Takumi 545b6803c3 X86Disassembler.cpp: Prune stray @return on translateFPRegister(). [-Wdocumentation]
llvm-svn: 198279
2014-01-01 16:19:26 +00:00
Craig Topper 9155118602 Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.
llvm-svn: 198278
2014-01-01 15:29:32 +00:00
Elena Demikhovsky de3f751baf AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp
Printing rounding control.
Enncoding for EVEX_RC (rounding control).

llvm-svn: 198277
2014-01-01 15:12:34 +00:00
Craig Topper 623b0d64b3 Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.
llvm-svn: 198276
2014-01-01 14:22:37 +00:00
Nick Lewycky 2d4ba2ebba Fold vector selects with undef elements in the condition. Fixes PR18319.
Patch by Ilia Filippov!

llvm-svn: 198267
2013-12-31 19:30:47 +00:00
Craig Topper e98c8cb9f0 Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases.
llvm-svn: 198265
2013-12-31 17:21:44 +00:00
Craig Topper b771ffaf4c Remove old comment referring to an argument that no longer exists.
llvm-svn: 198263
2013-12-31 15:29:14 +00:00
Mark Seaborn c3bd177ec2 Fix misaligned indentation in "if" block in MipsMCCodeEmitter.cpp
llvm-svn: 198262
2013-12-31 13:05:15 +00:00
Craig Topper df912ba6ec Add missing MRM_XX forms to the old JIT emitter for consistency.
llvm-svn: 198258
2013-12-31 03:26:24 +00:00
Craig Topper 99f02458e5 Remove MRMInitReg form now that it's last use is gone.
llvm-svn: 198257
2013-12-31 03:19:03 +00:00
Alp Toker 1bcdd6ae02 Silence g++ 4.9 build issue
lib/Support/ThreadLocal.cpp:53:15: error: typedef 'SIZE_TOO_BIG' locally defined but not used [-Werror=unused-local-typedefs]
   typedef int SIZE_TOO_BIG[sizeof(pthread_key_t) <= sizeof(data) ? 1 : -1];

Done the C++11 way, switching on and using LLVM_STATIC_ASSERT() instead of LLVM_ATTRIBUTE_UNUSED.

llvm-svn: 198255
2013-12-31 03:16:55 +00:00
Craig Topper 854f644781 Handle MOV32r0 in expandPostRAPseudo instead of MCInst lowering. No functional change intended.
llvm-svn: 198254
2013-12-31 03:05:38 +00:00
Craig Topper 258ab6abc9 Merge case statements to remove redundant code.
llvm-svn: 198241
2013-12-30 19:47:49 +00:00
Craig Topper 0e21bca6dd Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.
llvm-svn: 198238
2013-12-30 19:16:48 +00:00
Saleem Abdulrasool e3a9dc134d ARM IAS: account for predicated pre-UAL mnemonics
Checking the trailing letter of the mnemonic is insufficient.  Be more thorough
in the scanning of the instruction to ensure that we correctly work with the
predicated mnemonics.

llvm-svn: 198235
2013-12-30 18:38:01 +00:00
Eric Christopher 05893f475b Refactor and reduce code duplication for non-split dwarf strings.
llvm-svn: 198233
2013-12-30 18:32:31 +00:00
Eric Christopher d86672037b Revert r198208 and reapply:
r198196: Use a pointer to keep track of the skeleton unit for each normal unit and construct it up front.
      r198199: Reapply r198196 with a fix to zero initialize the skeleton pointer.
      r198202: Fix aranges and split dwarf by ensuring that the symbol and relocation back to the compile unit from the aranges section is to the skeleton unit and not the one in the dwo.

with a fix to use integer 0 for DW_AT_low_pc since the relocation to the text section symbol was causing issues with COFF. Accordingly remove addLocalLabelAddress and machinery since we're not currently using it.

llvm-svn: 198222
2013-12-30 17:22:27 +00:00
NAKAMURA Takumi 17b7310858 Revert r198199 (and r198202). It broke 3 DebugInfo tests for targeting i686-cygming.
r198196: Use a pointer to keep track of the skeleton unit for each normal unit and construct it up front.
  r198199: Reapply r198196 with a fix to zero initialize the skeleton pointer.
  r198202: Fix aranges and split dwarf by ensuring that the symbol and relocation back to the compile unit from the aranges section is to the skeleton unit and not the one in the dwo.

They could be reproducible with explicit target.

  llvm/lib/MC/WinCOFFObjectWriter.cpp:224: bool {anonymous}::COFFSymbol::should_keep() const: Assertion `Section->Number != -1 && "Sections with relocations must be real!"' failed.

llvm-svn: 198208
2013-12-30 09:26:10 +00:00
Eric Christopher c2d401e952 Fix aranges and split dwarf by ensuring that the symbol and relocation
back to the compile unit from the aranges section is to the skeleton
unit and not the one in the dwo.

Do this by adding a method to grab a forwarded on local sym and local
section by querying the skeleton if one exists and using that. Add
a few tests to verify the relocations are back to the correct section.

llvm-svn: 198202
2013-12-30 05:25:49 +00:00
Bill Wendling 6c1d9599d4 Keep comment with 'Subtarget' ivar.
llvm-svn: 198201
2013-12-30 05:17:29 +00:00
Eric Christopher d039baad05 Reapply r198196 with a fix to zero initialize the skeleton pointer.
llvm-svn: 198199
2013-12-30 03:40:32 +00:00
Eric Christopher be4c91c57c Temporarily revert "Use a pointer to keep track of the skeleton unit for
each normal unit" as it seems to be causing problems in the asan tests.

llvm-svn: 198197
2013-12-30 03:12:31 +00:00
Eric Christopher 83fff3fce7 Use a pointer to keep track of the skeleton unit for each normal unit
and construct it up front. Add address ranges at the end and a helper
routine so that we're not needlessly using an indirction in the case
of split dwarf.

Update testcases according to the new ordering of attributes on
the compile unit.

llvm-svn: 198196
2013-12-30 03:02:12 +00:00
Jiangning Liu a0acf70af1 For AArch64 Neon, simplify scalar dup by lane0 for fp.
llvm-svn: 198194
2013-12-30 02:44:35 +00:00
Hao Liu fe3bfc8c41 [AArch64]Add code to spill/fill Q register tuples such as QPair/QTriple/QQuad.
llvm-svn: 198193
2013-12-30 02:38:12 +00:00
Hao Liu b591f835d6 [AArch64]Can't select shift left 0 of type v1i64
llvm-svn: 198192
2013-12-30 02:12:46 +00:00
Kevin Qin ede9ce1933 Fix a bug in DAGcombiner about zero-extend after setcc.
For AArch64 backend, if DAGCombiner see "sext(setcc)", it will
combine them together to a single setcc with extended value type.
Then if it see "zext(setcc)", it assumes setcc is Vxi1, and try to
create "(and (vsetcc), (1, 1, ...)". While setcc isn't Vxi1,
DAGcombiner will create wrong node and get wrong code emitted.

llvm-svn: 198190
2013-12-30 02:05:13 +00:00
Hao Liu 74107fe526 [AArch64]Fix the problem that can't select mul of v1i64/v2i64 types.
E.g. Can't select such IR:
     %tmp = mul <2 x i64> %a, %b

llvm-svn: 198188
2013-12-30 01:38:41 +00:00
Nico Weber 1226531099 Set LLVM_EXPORTED_SYMBOL_FILE in CMakeLists whose corresponding Makefiles do so.
(unittests/ExecutionEngine/JIT/CMakeLists.txt is still missing for now, since
it handles export files in a strange way: It generates a .exports file from a
.def file instead of the other way round.)

llvm-svn: 198183
2013-12-29 23:06:49 +00:00
Saleem Abdulrasool aca443c02c ARM IAS: fix after r198172
The DPR and SPR register lists are also register lists.  Furthermore, the
registers need not be checked individually since the register type can be
checked via the list kind.  Use that to simplify the logic and fix the incorrect
assertion.

llvm-svn: 198174
2013-12-29 18:53:16 +00:00
Saleem Abdulrasool 4da9c6e566 ARM: provide VFP aliases for pre-V6 mnemonics
In order to provide compatibility with the GNU assembler, provide aliases for
pre-UAL mnemonics for floating point operations.

llvm-svn: 198172
2013-12-29 17:58:35 +00:00
Saleem Abdulrasool a1937cbc62 ARM: fix a few typos in comments
llvm-svn: 198171
2013-12-29 17:58:31 +00:00
Saleem Abdulrasool da96a81ee6 ARM: fix typo in VFP instruction definition
The vstm family of VFP instructions belong to the VFP store itinerary class, not
the VFP load itinerary class.

llvm-svn: 198170
2013-12-29 17:58:27 +00:00
Mark Seaborn 774c24385e Fix indentation alignment of a declaration in MipsMCCodeEmitter.cpp
llvm-svn: 198162
2013-12-29 10:47:04 +00:00
Bill Wendling 76cce1906a Store the global variable that's created so that it's reclaimed afterwards.
This plugs a memory leak in ARM's FastISel by storing the GV in Module so that
it's reclaimed.
PR17978

llvm-svn: 198160
2013-12-29 08:00:04 +00:00
Venkatraman Govindaraju 3e3a29a2e9 [SparcV9] Use separate instruction patterns for 64 bit arithmetic instructions instead of reusing 32 bit instruction patterns.
This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot.

llvm-svn: 198157
2013-12-29 07:15:09 +00:00
Venkatraman Govindaraju 5ac9c8faec [SparcV9] For codegen generated library calls that return float, set inreg flag manually in LowerCall().
This makes the sparc backend to generate Sparc64 ABI compliant code.

llvm-svn: 198149
2013-12-29 04:27:21 +00:00
Craig Topper a448bd868f Make more of the x86 lowering helper functions static.
llvm-svn: 198146
2013-12-29 01:48:38 +00:00
Venkatraman Govindaraju 0776cc0acd [SparcV9]: Implement lowering of long double (fp128) arguments in Sparc64 ABI.
Also, pass fp128 arguments to varargs through integer registers if necessary.

llvm-svn: 198145
2013-12-29 01:20:36 +00:00
Craig Topper 059e8e0da1 Switch from EVT to MVT in more of the x86 instruction lowering code.
llvm-svn: 198144
2013-12-29 01:10:06 +00:00
Saleem Abdulrasool 7230b377df CodeGen: silence a C++11 feature warning
llvm-svn: 198133
2013-12-28 22:47:55 +00:00
Saleem Abdulrasool 0c4b10264b ARM IAS: handle errors more appropriately
Directive parsers must return false if the target assembler is interested in
handling the directive.  The Error member function returns true always.  Using
the 'return Error()' pattern would incorrectly indicate to the general parser
that the target was not interested in the directive, when in reality it simply
encountered a badly formed directive or some other error.  This corrects the
behaviour to ensure that the parser behaves appropriately.

llvm-svn: 198132
2013-12-28 22:47:53 +00:00