maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
294,864 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

3 Commits

Author SHA1 Message Date
Alex Bradbury 96f492d7df [RISCV] Add codegen support for atomic load/stores with RV32A 
Fences are inserted according to table A.6 in the current draft of version 2.3
of the RISC-V Instruction Set Manual, which incorporates the memory model
changes and definitions contributed by the RISC-V Memory Consistency Model
task group.

Instruction selection failures will now occur for 8/16/32-bit atomicrmw and 
cmpxchg operations when targeting RV32IA until lowering for these operations 
is added in a follow-on patch.

Differential Revision: https://reviews.llvm.org/D47589

llvm-svn: 334591
 2018-06-13 12:04:51 +00:00
Alex Bradbury 48f95a655d [RISCV] MC layer support for the standard RV64A instruction set extension 
llvm-svn: 320027
 2017-12-07 10:59:12 +00:00
Alex Bradbury 8c345c5aa9 [RISCV] MC layer support for the standard RV32A instruction set extension 
llvm-svn: 317791
 2017-11-09 15:00:03 +00:00