Commit Graph

193737 Commits

Author SHA1 Message Date
Tom Stellard 1ca873bbc5 R600/SI: Don't set isCodeGenOnly = 1 on all instructions
We only need to set this on pseudo instructions which won't
be used by the assembler.

llvm-svn: 229689
2015-02-18 16:08:17 +00:00
Tom Stellard c34c37ae66 R600/SI: Add missing VOP1 instructions
llvm-svn: 229688
2015-02-18 16:08:15 +00:00
Tom Stellard 894b9883f4 R600/SI: Add missing VOP2 instructions
llvm-svn: 229687
2015-02-18 16:08:14 +00:00
Tom Stellard 0c0008cb6e R600/SI: Add definition for S_CBRANCH_G_FORK
llvm-svn: 229686
2015-02-18 16:08:13 +00:00
Tom Stellard ce449ade7e R600/SI: Add missing SOP1 instructions
llvm-svn: 229685
2015-02-18 16:08:11 +00:00
Tom Stellard ee21faa029 R600/SI: Refactor SOP2 definitions
llvm-svn: 229684
2015-02-18 16:08:09 +00:00
Tamas Berghammer c2c3d7185d Merge lldb-platform and lldb-gdbserver into a single binary
This commit merges lldb-platform and lldb-gdbserver into a single binary
of the same size as each of the previous individual binaries. Execution
mode is controlled by the first argument being either platform or
gdbserver.

Patch from: flackr <flackr@google.com>

Differential revision: http://reviews.llvm.org/D7545

llvm-svn: 229683
2015-02-18 15:39:41 +00:00
Ilia K e8b362a885 Fix make_symlink in case when symlink already exists (after r229517)
llvm-svn: 229682
2015-02-18 15:30:18 +00:00
Hafiz Abid Qadeer 5de6192e12 Fix line crossing 80 column border.
llvm-svn: 229681
2015-02-18 15:25:25 +00:00
Zoran Jovanovic 26a1216a74 Change representation of member function pointers for MIPS targets
Differential Revision: http://reviews.llvm.org/D7148

llvm-svn: 229680
2015-02-18 15:21:35 +00:00
Timur Iskhodzhanov 805d807139 [ASan/Win] Speculative fix to make the sed command line work with all sed implementations
llvm-svn: 229679
2015-02-18 15:14:07 +00:00
Dmitry Vyukov 8870ee7755 tsan: fix signal handling during stop-the-world
Long story short: stop-the-world briefly resets SIGSEGV handler to SIG_DFL.
This breaks programs that handle and continue after SIGSEGV (namely JVM).
See the test and comments for details.

http://reviews.llvm.org/D7722

llvm-svn: 229678
2015-02-18 15:13:29 +00:00
John Thompson eaa4c73d62 Updated file comment on modularize usage, as it was out-of-date.
llvm-svn: 229677
2015-02-18 15:11:12 +00:00
Daniel Sanders 933f0a04d3 Fix test/CodeGen/atomic_ops.c failure on clang-cmake-mips builder (and others).
Not all targets generate 'store atomic' instructions for
'_Atomic(_Complex int)'. Some targets use the __atomic_store builtin instead. 

This commit makes the test accept either one.

llvm-svn: 229676
2015-02-18 15:08:37 +00:00
Vasileios Kalintiris 611cb70b83 [mips] Avoid redundant sign extension of the result of binary bitwise instructions.
Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7581

llvm-svn: 229675
2015-02-18 14:57:05 +00:00
Ilia K 335c29ed0b Fix typo in make_symlink after r229517. It fixes symlinks on a UNIX style platform.
llvm-svn: 229674
2015-02-18 14:16:48 +00:00
Daniel Jasper c0b7c80fe6 Prevent use after free caused by accessing a member into a dense set.
The member gets invalidated as elements are added to the dense set. Directly
access the underlying pointer instead. Not sure how to create a test case for
this :-(. Maybe Richard can help.

llvm-svn: 229673
2015-02-18 14:13:46 +00:00
Benjamin Kramer 6ca8992018 X86: Use bitset to manage a bag of bits. NFC.
Doesn't matter in terms of memory usage or perf here, but it's a neat
simplification.

llvm-svn: 229672
2015-02-18 14:10:44 +00:00
Toma Tabacu 8874eac5e6 [mips] [IAS] Fix using .cpsetup with local labels (PR22518).
Summary:
Parse for an MCExpr instead of an Identifier and use the symbol for relocations, not just the symbol's name.

This fixes errors when using local labels in .cpsetup (PR22518).

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: seanbruno, emaste, llvm-commits

Differential Revision: http://reviews.llvm.org/D7697

llvm-svn: 229671
2015-02-18 13:46:53 +00:00
Chandler Carruth bbb377c3a1 [x86] Tighten the assertions to document that canonicalization has
actually removed all but a *very* small number of choices for v2i64.
Also remove dead code handling cases that simply cannot arise.

llvm-svn: 229670
2015-02-18 11:46:29 +00:00
Chandler Carruth 811f0ee8c1 [x86] Switch an if which is trivially true to an assert. NFC
llvm-svn: 229669
2015-02-18 11:46:27 +00:00
Chandler Carruth 8f3e585b17 [x86] Remove some more 'bit' nomenclature from the generic shift
lowering.

llvm-svn: 229668
2015-02-18 11:46:23 +00:00
Mohit K. Bhakkad 518946e440 [MSan][MIPS] VarArgHelper for MIPS64
Reviewers: Reviewers: eugenis, kcc, samsonov, petarj

Subscribers: dsanders, sagar, llvm-commits

Differential Revision: http://reviews.llvm.org/D7182

llvm-svn: 229667
2015-02-18 11:41:24 +00:00
Tamas Berghammer 81e9239e07 Remove alias template from GDBRemoteCommunicationServerCommon
It is required because MSVC 2013 doesn't generate correct code for
template aliases.

llvm-svn: 229666
2015-02-18 11:37:46 +00:00
Renato Golin ee130d1c2a Enable ASAN build and test on AArch64
llvm-svn: 229665
2015-02-18 11:34:41 +00:00
Hafiz Abid Qadeer 019ea8a7c0 Fix some warnings in MSVC build.
Platform.h was causing soem warning due to multiple defined maros.
It already has a define that excludes the singal.h but that was not being
used at correct place. It has been fixed now.

Tested by building on Windows(MSVC) and Linux(gcc).

llvm-svn: 229664
2015-02-18 11:12:11 +00:00
Hafiz Abid Qadeer dfbe605985 Fix a typo.
llvm-svn: 229663
2015-02-18 11:04:17 +00:00
Chandler Carruth 672a98ea28 [x86] Fold together the two shift lowering strategies. They were doing
quite literally the same work, we just need to special case the >64-bit
element shift code emission to emit the byte shift instructions and
offsets. This also makes reasoning about each of the vector lowering
strategies easier as we don't have to remember to use both forms.

llvm-svn: 229662
2015-02-18 10:40:38 +00:00
Bradley Smith d86d670e85 [ARM] Add missing M/R class CPUs
Add some of the missing M and R class Cortex CPUs, namely:

Cortex-M0+ (called Cortex-M0plus for GCC compatibility)
Cortex-M1
SC000
SC300
Cortex-R5

llvm-svn: 229661
2015-02-18 10:34:48 +00:00
Bradley Smith 26c9922a59 [ARM] Add missing M/R class CPUs
Add some of the missing M and R class Cortex CPUs, namely:

Cortex-M0+ (called Cortex-M0plus for GCC compatibility)
Cortex-M1
SC000
SC300
Cortex-R5

llvm-svn: 229660
2015-02-18 10:33:30 +00:00
Michael Kuperstein af9befa6b7 Fixes two issue in SimplifyDemandedBits of sext_in_reg:
1) We should not try to simplify if the sext has multiple uses
2) There is no need to simplify is the source value is already sign-extended.

Patch by Gil Rapaport <gil.rapaport@intel.com>

Differential Revision: http://reviews.llvm.org/D6949

llvm-svn: 229659
2015-02-18 09:43:40 +00:00
Ulrich Weigand b7e5909a42 [SystemZ] Clean up warning
Removed (unreachable) default case in switch to clean up warning:

lib/Target/SystemZ/SystemZISelLowering.cpp:1974:5:
error: default label in switch which covers all enumeration values
[-Werror,-Wcovered-switch-default]

llvm-svn: 229658
2015-02-18 09:42:23 +00:00
Dmitry Vyukov 2a80437038 tsan: add -Wno-maybe-uninitialized to mingw gcc build flags
As per discussion with David Blaikie here:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20150216/260289.html

llvm-svn: 229657
2015-02-18 09:37:31 +00:00
Mohit K. Bhakkad b40fed04e7 [MSan][MIPS] Fix for some failing tests on MIPS64
Enabling internal ptrace for mips, which fixes some
ptrace related tests. Along with this fixing some
other failures.

Reviewers: Reviewers: eugenis, kcc, samsonov

Subscribers: dsanders, sagar, lldb-commits

Differential Revision: http://reviews.llvm.org/D7332

llvm-svn: 229656
2015-02-18 09:24:19 +00:00
Chandler Carruth 48cc6c623a [x86] Refactor the bit shift code the same as I just did the byte shift
code.

While this didn't have the miscompile (it used MatchLeft consistently)
it missed some cases where it could use right shifts. I've added a test
case Craig Topper came up with to exercise the right shift matching.

This code is really identical between the two. I'm going to merge them
next so that we don't keep two copies of all of this logic.

llvm-svn: 229655
2015-02-18 09:19:58 +00:00
Ulrich Weigand 7db6918e2b [SystemZ] Support all TLS access models - CodeGen part
The current SystemZ back-end only supports the local-exec TLS access model.
This patch adds all required CodeGen support for the other TLS models, which
means in particular:

- Expand initial-exec TLS accesses by loading TLS offsets from the GOT
  using @indntpoff relocations.

- Expand general-dynamic and local-dynamic accesses by generating the
  appropriate calls to __tls_get_offset.  Note that this routine has
  a non-standard ABI and requires loading the GOT pointer into %r12,
  so the patch also adds support for the GLOBAL_OFFSET_TABLE ISD node.

- Add a new platform-specific optimization pass to remove redundant
  __tls_get_offset calls in the local-dynamic model (modeled after
  the corresponding X86 pass).

- Add test cases verifying all access models and optimizations.

llvm-svn: 229654
2015-02-18 09:13:27 +00:00
Igor Laevsky b2b31cfc3f Testing commit access
llvm-svn: 229653
2015-02-18 09:11:50 +00:00
Ulrich Weigand 7bdd7c2346 [SystemZ] Support all TLS access models - MC part
The current SystemZ back-end only supports the local-exec TLS access model.
This patch adds all required MC support for the other TLS models, which
means in particular:

- Support additional relocation types for
  Initial-exec model: R_390_TLS_IEENT
  Local-dynamic-model: R_390_TLS_LDO32, R_390_TLS_LDO64,
                       R_390_TLS_LDM32, R_390_TLS_LDM64, R_390_TLS_LDCALL
  General-dynamic model: R_390_TLS_GD32, R_390_TLS_GD64, R_390_TLS_GDCALL

- Support assembler syntax to generate additional relocations
  for use with __tls_get_offset calls:
    :tls_gdcall:
    :tls_ldcall:

The patch also adds a new test to verify fixups and relocations,
and removes the (already unused) FK_390_PLT16DBL/FK_390_PLT32DBL
fixup kinds.

llvm-svn: 229652
2015-02-18 09:11:36 +00:00
NAKAMURA Takumi a250484c4c Reformat.
llvm-svn: 229651
2015-02-18 08:36:14 +00:00
NAKAMURA Takumi fa520c5f49 Revert r229622: "[LoopAccesses] Make VectorizerParams global" and others. r229622 brought cyclic dependencies between Analysis and Vector.
r229622: "[LoopAccesses] Make VectorizerParams global"
  r229623: "[LoopAccesses] Stash the report from the analysis rather than emitting it"
  r229624: "[LoopAccesses] Cache the result of canVectorizeMemory"
  r229626: "[LoopAccesses] Create the analysis pass"
  r229628: "[LoopAccesses] Change debug messages from LV to LAA"
  r229630: "[LoopAccesses] Add canAnalyzeLoop"
  r229631: "[LoopAccesses] Add missing const to APIs in VectorizationReport"
  r229632: "[LoopAccesses] Split out LoopAccessReport from VectorizerReport"
  r229633: "[LoopAccesses] Add -analyze support"
  r229634: "[LoopAccesses] Change LAA:getInfo to return a constant reference"
  r229638: "Analysis: fix buildbots"

llvm-svn: 229650
2015-02-18 08:34:47 +00:00
Daniel Jasper ed9eb7209e NFC: Use range-based for loops and more consistent naming.
No functional changes intended.

(I plan on doing some modifications to this function and would like to
have as few unrelated changes as possible in the patch)

llvm-svn: 229649
2015-02-18 08:19:16 +00:00
Daniel Jasper 4d7b04384e Remove experimental options to control machine block placement.
This reverts r226034. Benchmarking with those flags has not revealed
anything interesting.

llvm-svn: 229648
2015-02-18 08:18:07 +00:00
Elena Demikhovsky 6ddd998589 Minor fix after 229495.
Removed metadata and function attributes from the test.

llvm-svn: 229647
2015-02-18 08:09:28 +00:00
Sanjoy Das c1065b9a4f Address post commit review on r229600.
llvm-svn: 229646
2015-02-18 08:03:22 +00:00
Elena Demikhovsky 714f23bcdb AVX-512: Added support for FP instructions with embedded rounding mode.
By Asaf Badouh <asaf.badouh@intel.com>

llvm-svn: 229645
2015-02-18 07:59:20 +00:00
David Majnemer 7ff7eb706a Itanium ABI: Mangle <mangled-name> according to the ABI
We attempted to be compatible with GCC's buggy mangling for templates
with a declaration for a template argument.

However, we weren't completely successful in copying their bug in cases
like:
  char foo;
  template <char &C> decltype(C) f() { return foo; };
  template char &f<foo>();

Instead, just follow the ABI specification.  This fixes PR22621.

llvm-svn: 229644
2015-02-18 07:47:09 +00:00
Craig Topper 55ac42426e [X86] Add another test case for the bug fixed in r229642. With the bug a vpsrldq was emitted instead of pslldq.
llvm-svn: 229643
2015-02-18 07:45:43 +00:00
Chandler Carruth 55553f5299 [x86] Rewrite the byte shift detection to not use boolean variables to
track state.

I didn't like this in the code review because the pattern tends to be
error prone, but I didn't see a clear way to rewrite it. Turns out that
there were bugs here, I found them when fuzz testing our shuffle
lowering for correctness on x86.

The core of the problem is that we need to consistently test all our
preconditions for the same directionality of shift and the same input
vector. Instead, formulate this as two predicates (one doesn't depend on
the input in any way), pass things like the directionality and input
vector as inputs, and loop over the alternatives.

This fixes a pattern of very rare miscompiles coming out of this code.
Turned up roughly 4 out of every 1 million v8 shuffles in my fuzz
testing. The new code is over half a million test runs with no failures
yet. I've also fuzzed every other function in the lowering code with
over 3.5 million test cases and not discovered any other miscompiles.

llvm-svn: 229642
2015-02-18 07:13:48 +00:00
Craig Topper 1348f17205 [X86] Remove AVX512 pslldq/psrldq shift intrinsics. They aren't implemented yet and when they are they should be done with shuffles like SSE2 and AVX2.
llvm-svn: 229641
2015-02-18 06:24:49 +00:00
Craig Topper b324e43aed [X86] Remove AVX2 and SSE2 pslldq and psrldq intrinsics. We can represent them in IR with vector shuffles now. All their uses have been removed from clang in favor of shuffles.
llvm-svn: 229640
2015-02-18 06:24:44 +00:00