1c7597693c
Use existing function.
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llvm-svn: 140615
2011-09-27 17:55:08 +00:00
e41b1d59f0
Fix function MipsRegisterInfo::getRegisterNumbering.
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Return numbers of 64-bit registers.
llvm-svn: 140609
2011-09-27 17:15:27 +00:00
ff5d0965b0
Do not add the pass that restores $gp if target is Mips64.
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llvm-svn: 140607
2011-09-27 16:58:43 +00:00
86de1a666d
Have the verifier check that all landingpad operands are constants.
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llvm-svn: 140606
2011-09-27 16:43:19 +00:00
38b3b83362
Cleanup PromoteIntOp_EXTRACT_VECTOR_ELT and PromoteIntRes_SETCC.
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Add a new method: getAnyExtOrTrunc and use it to replace the manual check.
llvm-svn: 140603
2011-09-27 11:16:47 +00:00
1b857d2762
Revert r140463; The patch assumes that <4 x i1> is saved to memory as 4 x i8,
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while the decision is to bit-pack small values.
llvm-svn: 140601
2011-09-27 10:48:29 +00:00
bb050745e7
Mark MipsPseudo isPseudo.
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llvm-svn: 140598
2011-09-27 04:57:54 +00:00
9f01f89386
PTX: Add support for sitofp in backend
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llvm-svn: 140593
2011-09-27 01:04:47 +00:00
90f90da156
Split the landing pad basic block with the correct function. Also merge the
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split landingpad instructions into a PHI node.
PR11016
llvm-svn: 140592
2011-09-27 00:59:31 +00:00
581243919d
Disable LSR retry by default.
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Disabling aggressive LSR saves compilation time, and with the new
indvars behavior usually improves performance.
llvm-svn: 140590
2011-09-27 00:44:14 +00:00
8868faec63
LSR, one of the new Cost::isLoser() checks did not get merged in the previous checkin.
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llvm-svn: 140583
2011-09-26 23:35:25 +00:00
b1a9f65487
Remove extraneous commit garbage.
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llvm-svn: 140581
2011-09-26 23:14:02 +00:00
784729d408
LSR cost metric minor fix and verification.
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The minor bug heuristic was noticed by inspection. I added the
isLoser/isValid helpers because they will become more
important with subsequent checkins.
llvm-svn: 140580
2011-09-26 23:11:04 +00:00
a6a9c20c23
Set register class of a register according to value of HasMips64.
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llvm-svn: 140570
2011-09-26 21:55:17 +00:00
7b502920ef
Define variable HasMips64 in MipsTargetLowering.
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llvm-svn: 140569
2011-09-26 21:47:02 +00:00
e5ce709022
In single float mode, double precision FP arguments are passed in integer
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registers, so there is no need to check here.
llvm-svn: 140568
2011-09-26 21:37:50 +00:00
f01e2de5e6
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
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llvm-svn: 140560
2011-09-26 21:06:22 +00:00
5c91891cf3
Enhance alias analysis for atomic instructions a bit. Upgrade a couple alias-analysis tests to the new atomic instructions.
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llvm-svn: 140557
2011-09-26 20:15:28 +00:00
da2919dbd8
PTX: Fix memcpy intrinsic to handle 64-bit pointers
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llvm-svn: 140556
2011-09-26 19:19:48 +00:00
b40da7f956
PTX: Implement PTXSelectionDAGInfo
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llvm-svn: 140549
2011-09-26 18:57:27 +00:00
c3edaddfea
PTX: Implement ISD::ANY_EXTEND
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llvm-svn: 140548
2011-09-26 18:57:24 +00:00
1395cf8423
PTX: Fix detection of stack load/store vs. global load/store, as well as fix the
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printing of local offsets
llvm-svn: 140547
2011-09-26 18:57:22 +00:00
0ceb8cadd2
Fix emission of debug data for global variables. getContext() on DIGlobalVariables is not valid any more.
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llvm-svn: 140539
2011-09-26 17:40:42 +00:00
f8dd701bf9
PTX: SM > 2.0 implies +double
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llvm-svn: 140536
2011-09-26 16:20:36 +00:00
14defde057
PTX: Fix some lingering issues with stack allocation
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llvm-svn: 140535
2011-09-26 16:20:34 +00:00
37fd87675f
PTX: Split up the TableGen instruction definitions into logical units
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llvm-svn: 140534
2011-09-26 16:20:31 +00:00
d40f5ababf
PTX: Unify handling of loads/stores
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llvm-svn: 140533
2011-09-26 16:20:28 +00:00
8c80019352
PTX: Handle FrameIndex nodes
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llvm-svn: 140532
2011-09-26 16:20:25 +00:00
b1fbf9ff26
PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval
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llvm-svn: 140516
2011-09-26 06:13:20 +00:00
45faba98b4
Fix VEX decoding in i386 mode. Fixes PR11008.
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llvm-svn: 140515
2011-09-26 05:12:43 +00:00
df977fedb6
Add target hook for pseudo instruction expansion.
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Many targets use pseudo instructions to help register allocation. Like
the COPY instruction, these pseudos can be expanded after register
allocation. The early expansion can make life easier for PEI and the
post-ra scheduler.
This patch adds a hook that is called for all remaining pseudo
instructions from the ExpandPostRAPseudos pass.
llvm-svn: 140472
2011-09-25 19:21:35 +00:00
2279949129
[vector-select] Address one of the issues in pr10902. EXTRACT_VECTOR_ELEMENT
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SDNodes may return values which are wider than the incoming element types. In
this patch we fix the integer promotion of these nodes.
Fixes spill-q.ll when running -promote-elements.
llvm-svn: 140471
2011-09-25 18:59:42 +00:00
fd719d184e
Clean up code after renaming LowerSubregs -> ExpandPostRAPseudos.
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No functional change intended.
llvm-svn: 140470
2011-09-25 16:46:08 +00:00
f152df1e6b
Rename LowerSubregs to ExpandPostRAPseudos.
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I'll fix the file contents in the next commit.
This pass is currently expanding the COPY and SUBREG_TO_REG pseudos. I
am going to add a hook so targets can expand more pseudo-instructions
after register allocation.
Many targets have pseudo-instructions that assist the register
allocator. They can be expanded after register allocation, before PEI
and PostRA scheduling.
llvm-svn: 140469
2011-09-25 16:46:00 +00:00
f550fa9173
Sort CMakeLists.txt.
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llvm-svn: 140465
2011-09-24 22:06:35 +00:00
c2deabd202
Implement Duncan's suggestion to use the result of getSetCCResultType if it is legal
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(this is always the case for scalars), otherwise use the promoted result type.
Fix test/CodeGen/X86/vsplit-and.ll when promote-elements is enabled.
llvm-svn: 140464
2011-09-24 19:48:19 +00:00
77426a754b
[Vector-Select] Address one of the problems in 10902.
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When generating the trunc-store of i1's, we need to use the vector type and not
the scalar type.
This patch fixes the assertion in CodeGen/Generic/bool-vector.ll when
running with -promote-elements.
llvm-svn: 140463
2011-09-24 18:32:19 +00:00
7d7ee0c3ac
Add .td file.
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llvm-svn: 140446
2011-09-24 01:40:18 +00:00
e96273e75d
Preparation for adding simple Mips64 instructions.
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llvm-svn: 140443
2011-09-24 01:34:44 +00:00
55cf2ed148
Only run MF.verify() with EXPENSIVE_CHECKS=1.
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llvm-svn: 140441
2011-09-24 01:11:19 +00:00
9b92e2be30
sys::Process: Add a SetWorkingDirectory method.
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llvm-svn: 140433
2011-09-23 23:23:36 +00:00
8b2fe2f744
LSR minor bug fix in RateRegister.
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No test case. Noticed by inspection and I doubt it ever affects the
outcome of the overall heuristic, let alone final codegen.
llvm-svn: 140431
2011-09-23 23:05:19 +00:00
3bb99bc957
Verify that terminators follow non-terminators.
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This exposes a -segmented-stacks bug.
llvm-svn: 140429
2011-09-23 22:45:39 +00:00
8a15a5aa93
PR10998: It is not legal to sink an instruction past the terminator of a block; make sure we don't do that.
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llvm-svn: 140428
2011-09-23 22:41:57 +00:00
4916840eb8
Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0.
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llvm-svn: 140426
2011-09-23 22:25:02 +00:00
2056d15bd9
Also match negative offsets for addrmode3 and addrmode5.
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Math is hard, and isScaledConstantInRange() always returned false for
negative constants. It was doing unsigned division of negative numbers
before casting back to signed.
llvm-svn: 140425
2011-09-23 22:10:33 +00:00
b0b865d658
Add more fixed bits to USAT16 encoding to filter out incorrect decodings.
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llvm-svn: 140422
2011-09-23 21:57:50 +00:00
737beaf86d
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
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llvm-svn: 140420
2011-09-23 21:26:40 +00:00
987a878946
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
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llvm-svn: 140415
2011-09-23 21:07:25 +00:00
ffa8428acf
Revert r140412. This affects more instructions than intended.
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llvm-svn: 140413
2011-09-23 21:02:01 +00:00
Jakob Stoklund Olesen