Commit Graph

68 Commits

Author SHA1 Message Date
Daniel Neilson 6e938effaa Change memcpy/memove/memset to have dest and source alignment attributes (Step 1).
Summary:
  Upstream LLVM is changing the the prototypes of the @llvm.memcpy/memmove/memset
intrinsics. This change updates the Clang tests for this change.

  The @llvm.memcpy/memmove/memset intrinsics currently have an explicit argument
which is required to be a constant integer. It represents the alignment of the
dest (and source), and so must be the minimum of the actual alignment of the
two.

 This change removes the alignment argument in favour of placing the alignment
attribute on the source and destination pointers of the memory intrinsic call.

 For example, code which used to read:
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 100, i32 4, i1 false)
will now read
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %dest, i8* align 4 %src, i32 100, i1 false)

 At this time the source and destination alignments must be the same (Step 1).
Step 2 of the change, to be landed shortly, will relax that contraint and allow
the source and destination to have different alignments.

llvm-svn: 322964
2018-01-19 17:12:54 +00:00
Abderrazek Zaafrani f58a132eef [AARch64] Add ARMv8.2-A FP16 vector intrinsics
Putting back the code that was reverted few weeks ago.

Differential Revision: https://reviews.llvm.org/D34161

llvm-svn: 321294
2017-12-21 19:20:01 +00:00
Sjoerd Meijer 98ee78578b This reverts r305820 (ARMv.2-A FP16 vector intrinsics) because it shows
problems in testing, see comments in D34161 for some more details.
A fix is in progres in D35011, but a revert seems better now as the fix will
probably take some more time to land.

llvm-svn: 307277
2017-07-06 16:37:31 +00:00
Abderrazek Zaafrani f10ca93f34 [AArch64] ADD ARMv.2-A FP16 vector intrinsics
Differential Revision: https://reviews.llvm.org/D34161

llvm-svn: 305820
2017-06-20 18:54:57 +00:00
Vedant Kumar a44a6ac81f Revert "[AArch64] Add ARMv8.2-A FP16 vefctor intrinsics"
This reverts commit r304493. It breaks all the Darwin bots:
http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental_check/37168

Failure:
Failing Tests (2):
    Clang :: CodeGen/aarch64-v8.2a-neon-intrinsics.c
    Clang :: CodeGen/arm_neon_intrinsics.c

llvm-svn: 304509
2017-06-02 01:22:14 +00:00
Abderrazek Zaafrani a44e5f601d [AArch64] Add ARMv8.2-A FP16 vefctor intrinsics
llvm-svn: 304493
2017-06-01 23:22:29 +00:00
Mehdi Amini 6aa9e9b41a IRGen: Add optnone attribute on function during O0
Amongst other, this will help LTO to correctly handle/honor files
compiled with O0, helping debugging failures.
It also seems in line with how we handle other options, like how
-fnoinline adds the appropriate attribute as well.

Differential Revision: https://reviews.llvm.org/D28404

llvm-svn: 304127
2017-05-29 05:38:20 +00:00
Matt Arsenault 7c4c1cb2f5 Fix tests after speculatable intrinsics patch
These were relying on the attribute group numbering

llvm-svn: 301996
2017-05-03 03:04:40 +00:00
Adam Nemet 5827756e90 Remove -ffp-contract=fast from this test
It does not need it and causes mismatch after -ffp-contract=fast is turned
into an FMF.

llvm-svn: 298469
2017-03-22 00:58:18 +00:00
David Majnemer 12b9e76b62 Update for LLVM changes
InstSimplify has gained the ability to remove needless bitcasts which
perturbed some clang codegen tests.

llvm-svn: 276728
2016-07-26 05:52:37 +00:00
Ahmed Bougacha 1d9de10130 [ARM NEON] Define vfms_f32 on ARM, and all vfms using vfma.
r259537 added vfma/vfms to armv7, but the builtin was only lowered
on the AArch64 side. Instead of supporting it on ARM, get rid of it.

The vfms builtin lowered to:
  %nb = fsub float -0.0, %b
  %r = @llvm.fma.f32(%a, %nb, %c)

Instead, define the operation in terms of vfma, and swap the
multiplicands. It now lowers to:
  %na = fsub float -0.0, %a
  %r = @llvm.fma.f32(%na, %b, %c)

This matches the instruction more closely, and lets current LLVM
generate the "natural" operand ordering:
  fmls.2s v0, v1, v2
instead of the crooked (but equivalent):
  fmls.2s v0, v2, v1
Except for theses changes, assembly is identical.

LLVM accepts both commutations, and the LLVM tests in:
  test/CodeGen/AArch64/arm64-fmadd.ll
  test/CodeGen/AArch64/fp-dp3.ll
  test/CodeGen/AArch64/neon-fma.ll
  test/CodeGen/ARM/fusedMAC.ll
already check either the new one only, or both.

Also verified against the test-suite unittests.

llvm-svn: 266807
2016-04-19 19:44:45 +00:00
Tim Northover 67181e3c3a ARM & AArch64: fix IR-converted tests.
My script was converting %a0 to [[A]]0 if it had seen %a defined before %a0.
Oops.

llvm-svn: 263056
2016-03-09 20:06:10 +00:00
Tim Northover 58672974a9 ARM & AArch64: convert asm tests to LLVM IR and restrict optimizations.
This is mostly a one-time autoconversion of tests that checked assembly after
"-Owhatever" compiles to only run "opt -mem2reg" and check the assembly. This
should make them much more stable to changes in LLVM so they won't break on
unrelated changes.

"opt -mem2reg" is a compromise designed to increase the readability of tests
that check dataflow, while minimizing dependency on LLVM. Hopefully mem2reg is
stable enough that no surpises will come along.

Should address http://llvm.org/PR26815.

llvm-svn: 263048
2016-03-09 18:54:42 +00:00
Chad Rosier 36577d037f Revert "[Reassociate] Update test cases due to r222142."
This reverts commit r222144.  Commit r222142 is being reverted due to
a spec2006/gcc execution-time regression.

Update mips-varargs test as well.

llvm-svn: 222397
2014-11-19 23:20:35 +00:00
Chad Rosier 0837f63fd2 [Reassociate] Update test cases due to r222142.
llvm-svn: 222144
2014-11-17 16:34:47 +00:00
Tim Northover 831d728f9a AArch64: re-enable tests that were looking for a non-existent backend.
In the final phase of the merge, I managed to disable a bunch of Clang
tests accidentally. Fortunately none of them seem to have broken in
the interim.

llvm-svn: 211149
2014-06-18 08:37:28 +00:00
Tim Northover 25e8a6754e AArch64/ARM64: update Clang after AArch64 removal.
A few (mostly CodeGen) parts of Clang were tightly coupled to the
AArch64 backend. Now that it's gone, they will not even compile.

I've also deduplicated RUN lines in many of the AArch64 tests. This
might improve "make check-all" time noticably: some of those NEON
tests were monsters.

llvm-svn: 209578
2014-05-24 12:51:25 +00:00
Hao Liu 9f9492b657 [ARM64]Fix the bug right shift uint64_t by 64 generates incorrect result.
llvm-svn: 208761
2014-05-14 08:59:30 +00:00
Tim Northover f4aee52345 AArch64: update tests to new way of printing NEON lists.
llvm-svn: 207117
2014-04-24 14:06:31 +00:00
Tim Northover 761aa37e3e ARM64: update NEON test to improved backend codegen
llvm-svn: 206890
2014-04-22 12:45:55 +00:00
James Molloy 75f5f9e629 [ARM64] Allow the disabling of NEON and crypto instructions. Update tests to pass -target-feature +neon.
llvm-svn: 206394
2014-04-16 15:33:48 +00:00
Tim Northover 0c68faa455 ARM64: enable aarch64-neon-intrinsics.c test
This adds support for the various NEON intrinsics used by
aarch64-neon-intrinsics.c (originally written for AArch64) and enables the
test.

My implementations are designed to be semantically correct, the actual code
quality looks like its a wash between the two backends, and is frequently
different (hence the large number of CHECK changes).

llvm-svn: 205210
2014-03-31 15:47:09 +00:00
Tim Northover 926a235fea AArch64: convert NEON tests to use CHECK-LABEL.
llvm-svn: 202703
2014-03-03 11:34:36 +00:00
Kevin Qin ce1f0e85ba [AArch64 NEON] Fix a bug about vcles_f32 and vcled_f64.
As vcles_f32() and vcled_f64 are implemented by FCMGE, operands
should make a swap.

llvm-svn: 199866
2014-01-23 03:42:06 +00:00
Jiangning Liu 38799b1471 Add some missing test cases for ACLE intrinsics of AArch64 NEON.
llvm-svn: 197994
2013-12-25 01:23:43 +00:00
Chad Rosier 75df5680fe [AArch64] Fix v1fx patterns for Floating-point Multiply Extend and Floating-point Compare to Zero.
llvm-svn: 197403
2013-12-16 18:29:54 +00:00
Kevin Qin daaae418d8 Fix Incorrect CHECK message [0-31]+ in test case.
In regular expression, [0-31]+ equals to [0-3]+, not the number from
0 to 31. So change it to [0-9]+.

llvm-svn: 197112
2013-12-12 02:17:35 +00:00
Hao Liu 844a7da243 [AArch64]Add missing pair intrinsics such as:
int32_t vminv_s32(int32x2_t a) 
which should be compiled into SMINP Vd.2S,Vn.2S,Vm.2S

llvm-svn: 196750
2013-12-09 03:52:22 +00:00
Kevin Qin 8903f8df4b [AArch64 NEON] Add missing compare intrinsics.
llvm-svn: 196359
2013-12-04 07:53:09 +00:00
Hao Liu a5246fde90 [AArch64]Add missing floating point convert, round and misc intrinsics.
E.g. int64x1_t vcvt_s64_f64(float64x1_t a) -> FCVTZS Dd, Dn

llvm-svn: 196211
2013-12-03 06:07:13 +00:00
Hao Liu 38658a8186 AArch64: add missing ACLE intrinsics mapping to general arithmetic operation from VFP instructions.
E.g. float64x1_t vadd_f64(float64x1_t a, float64x1_t b) -> FADD Dd, Dn, Dm.

llvm-svn: 196209
2013-12-03 05:58:49 +00:00
Hao Liu 4b850c5e0d revert r196152.
This is a duplicate implementation.
E.g. this patch defines:
     float64_t vabd_f64(float64_t a, float64_t b)
But there is already a similar intrinsic "vabdd_f64" with the same types.
Also, this intrinsic will be conflicted to the vector type intrinsic as following(Which is implemented by me and will be committed to trunk):
     float64x1_t vabd_f64(float64x1_t a, float64x1_t b).
Two functions shouldn't have a same name in arm_neon.h.
According to ARM ACLE document, such vabd_f64 with float64_t is not existing.
So I revert this commit.

llvm-svn: 196205
2013-12-03 05:35:17 +00:00
Hao Liu ce258820ca AArch64: Add missing scalar pair intrinsics.
E.g. "float32_t vaddv_f32(float32x2_t a)" to be matched into "faddp s0, v1.2s".

llvm-svn: 196199
2013-12-03 03:40:08 +00:00
Jiangning Liu 2d31f6f610 Add some missing AArch64 Neon intrinsics like vuqadd_s64 and friends.
llvm-svn: 196191
2013-12-03 01:33:16 +00:00
Chad Rosier b0574f3bf7 [AArch64] Add missing NEON scalar floating-point to integer convert ACLEs.
llvm-svn: 196152
2013-12-02 21:07:24 +00:00
Hao Liu 8a0099e02c Fix the problem that the range check for scalar narrow shift is too wide.
E.g. the immediate value of vshrns_n_s16 is [1,16], which should be [1,8].

llvm-svn: 195942
2013-11-29 02:13:17 +00:00
Jiangning Liu 24173dd4b1 Add missing intrinsic function vbsl_f64 for AArch64 NEON.
llvm-svn: 195940
2013-11-29 01:38:49 +00:00
Chad Rosier 9e59285cc8 [AArch64] Add support for NEON scalar floating-point absolute difference.
llvm-svn: 195804
2013-11-27 01:46:19 +00:00
Hao Liu 5e4ce1ae9d Implement the newly added AArch64 ACLE functions for ld1/st1 with 2/3/4 vectors.
The functions are like: vst1_s8_x2 ...

llvm-svn: 194991
2013-11-18 06:33:43 +00:00
Hao Liu 9e49704f59 Implement vreinterpret ACLE functions in Clang.
llvm-svn: 194954
2013-11-17 09:32:59 +00:00
Chad Rosier 7fa60db4a9 These ACLE tests no longer need to cast the return value.
llvm-svn: 194854
2013-11-15 21:28:24 +00:00
Chad Rosier 7aaee48bf0 [AArch64] Add support for legacy AArch32 NEON scalar shift right by immediate
and accumulate instructions.

llvm-svn: 194732
2013-11-14 22:02:24 +00:00
Chad Rosier e714a962b5 [AArch64] Tests for legacy AArch32 NEON scalar shift by immediate instructions.
A number of non-overloaded intrinsics have been replaced by thier overloaded
counterparts.

llvm-svn: 194599
2013-11-13 20:05:44 +00:00
Chad Rosier 09f5251c4d [AArch64] The shift right/left and insert immediate builtins expect 3
source operands, a vector, an element to insert, and a shift amount.

llvm-svn: 194407
2013-11-11 19:11:19 +00:00
Chad Rosier 249c714bb4 [AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions.
llvm-svn: 194395
2013-11-11 18:04:22 +00:00
Chad Rosier 74329d6cff [AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions.
llvm-svn: 193817
2013-10-31 22:37:08 +00:00
Chad Rosier bdca387884 [AArch64] Add support for NEON scalar shift immediate instructions.
llvm-svn: 193791
2013-10-31 19:29:05 +00:00
Chad Rosier 4d55e6e0a4 [AArch64] Add support for NEON scalar floating-point compare instructions.
llvm-svn: 193692
2013-10-30 15:20:07 +00:00
Chad Rosier c2a0b13c25 [AArch64] Add the constraint to NEON scalar mla/mls instructions.
llvm-svn: 193118
2013-10-21 20:12:01 +00:00
Chad Rosier 3c03dee1d1 [AArch64] Add support for NEON scalar extract narrow instructions.
llvm-svn: 192971
2013-10-18 14:03:36 +00:00