Konstantin Zhuravlyov
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2a87a42035
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[AMDGPU] Handle f16 select{_cc}
- Select `select` to `v_cndmask_b32`
- Expand `select_cc`
- Refactor patterns
Differential Revision: https://reviews.llvm.org/D26714
llvm-svn: 287074
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2016-11-16 03:16:26 +00:00 |
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Matt Arsenault
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81da114e65
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AMDGPU: Set hasExtraSrcRegAllocReq on v_div_scale_*
This doesn't solve any problems I know about, but this should have
more conservative assumptions about the operands'
llvm-svn: 286913
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2016-11-15 00:05:42 +00:00 |
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Konstantin Zhuravlyov
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f86e4b7266
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[AMDGPU] Add f16 support (VI+)
Differential Revision: https://reviews.llvm.org/D25975
llvm-svn: 286753
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2016-11-13 07:01:11 +00:00 |
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Tom Stellard
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115a61560e
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AMDGPU: Add VI i16 support
Patch By: Wei Ding
Differential Revision: https://reviews.llvm.org/D18049
llvm-svn: 286464
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2016-11-10 16:02:37 +00:00 |
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Tom Stellard
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2d2d33f1dc
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Revert "AMDGPU: Add VI i16 support"
This reverts commit r285939 and r285948. These broke some conformance tests.
llvm-svn: 285995
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2016-11-04 13:06:34 +00:00 |
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Tom Stellard
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2b3379cdff
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AMDGPU: Add VI i16 support
Patch By: Wei Ding
Differential Revision: https://reviews.llvm.org/D18049
llvm-svn: 285939
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2016-11-03 17:13:50 +00:00 |
|
Valery Pykhtin
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355103f6c0
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[AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions
Differential revision: https://reviews.llvm.org/D24738
llvm-svn: 282234
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2016-09-23 09:08:07 +00:00 |
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Valery Pykhtin
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e330cfa294
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[AMDGPU] Refactor VOP3 instruction TD definitions
Differential revision: https://reviews.llvm.org/D24664
llvm-svn: 281965
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2016-09-20 10:41:16 +00:00 |