01e65d2cfc
AMDGPU/SI: Remove zero_extend patterns for i16 ops selected to 32-bit insts
...
Summary:
The 32-bit instructions don't zero the high 16-bits like the 16-bit
instructions do.
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D26828
llvm-svn: 287342
2016-11-18 13:53:34 +00:00
d23de360db
AMDGPU/SI: Fix pattern for i16 = sign_extend i1
...
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D26670
llvm-svn: 287035
2016-11-15 21:25:56 +00:00
f86e4b7266
[AMDGPU] Add f16 support (VI+)
...
Differential Revision: https://reviews.llvm.org/D25975
llvm-svn: 286753
2016-11-13 07:01:11 +00:00
115a61560e
AMDGPU: Add VI i16 support
...
Patch By: Wei Ding
Differential Revision: https://reviews.llvm.org/D18049
llvm-svn: 286464
2016-11-10 16:02:37 +00:00
2d2d33f1dc
Revert "AMDGPU: Add VI i16 support"
...
This reverts commit r285939 and r285948. These broke some conformance tests.
llvm-svn: 285995
2016-11-04 13:06:34 +00:00
2b3379cdff
AMDGPU: Add VI i16 support
...
Patch By: Wei Ding
Differential Revision: https://reviews.llvm.org/D18049
llvm-svn: 285939
2016-11-03 17:13:50 +00:00
a3ec5c10e2
[AMDGPU] Assembler: support v_mac_f32 DPP and SDWA. Move getNamedOperandIdx to AMDGPUBaseInfo.h
...
Reviewers: artem.tamazov, tstellarAMD
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D25084
llvm-svn: 283560
2016-10-07 14:46:06 +00:00
355103f6c0
[AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions
...
Differential revision: https://reviews.llvm.org/D24738
llvm-svn: 282234
2016-09-23 09:08:07 +00:00
Tom Stellard