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3 Commits

Author SHA1 Message Date
Ayke van Laethem 15bf42d503
[AVR] Implement disassembly of 32-bit instructions 
This needed two fixes:

  * 32-bit instructions were read in the wrong order. The machine code
    swaps the two 16-bit instruction words, which wasn't undone when
    decoding instructions.
  * Jump and call instructions don't encode the lowest address bit,
    which is always zero. Therefore, the address needed to be shifted by
    one to fix that.

Differential Revision: https://reviews.llvm.org/D81961
 2020-06-18 11:26:58 +02:00
Dylan McKay 2e8718bcbb [AVR] Fix a bug so that we now emit R_AVR_16 fixups with the correct offset 
Before this, the LDS/STS instructions would have their opcodes
overwritten while linking.

llvm-svn: 301782
 2017-04-30 23:33:52 +00:00
Dylan McKay 3ffc449597 [AVR] Add all of the machine code test suite 
Summary: This adds all of the AVR machine code tests.

Reviewers: arsenm, kparzysz

Subscribers: wdng, japaric

Differential Revision: https://reviews.llvm.org/D26387

llvm-svn: 286417
 2016-11-09 23:46:25 +00:00