Commit Graph

152744 Commits

Author SHA1 Message Date
Evgeniy Stepanov 1bd0fe447f [sanitizer] Fix Android build.
llvm-svn: 185432
2013-07-02 14:51:31 +00:00
Evgeniy Stepanov aa23bd83e5 [msan] Intercept mempcpy, wmempcpy.
llvm-svn: 185431
2013-07-02 14:49:24 +00:00
Richard Osborne e4cc98686a [XCore] Fix instruction selection for zext, mkmsk instructions.
r182680 replaced CountLeadingZeros_32 with a template function
countLeadingZeros that relies on using the correct argument type to give
the right result. The type passed in the XCore backend after this
revision was incorrect in a couple of places.

Patch by Robert Lytton.

llvm-svn: 185430
2013-07-02 14:46:34 +00:00
Tobias Grosser 24bb46bc66 [autoconf/cmake] Make sure we detect the latest version of isl.
llvm-svn: 185429
2013-07-02 14:11:32 +00:00
Evgeniy Stepanov 69a387e6ae [sanitizer] Fix GLOB_NOMATCH behaviour and refactor the interceptor a bit.
llvm-svn: 185428
2013-07-02 14:08:52 +00:00
Ed Maste d3561c6abe Build standalone debug symbol file support on FreeBSD too
llvm-svn: 185425
2013-07-02 13:52:38 +00:00
Evgeniy Stepanov 165d759a6a [sanitizer] Intercept mbtowc, mbrtowc, get_current_dir_name.
Move getcwd to common interceptors.

llvm-svn: 185424
2013-07-02 13:34:44 +00:00
Daniel Jasper a3fc21a0f1 Fix ranges computed by git clang-format.
Before, the computed byte range would include the trailing newline.
clang-format on the other hand counts whitespace as belonging to the
following token, so that git-clang-format inadvertendly reformats the
first unmodified line as well.

It is not entirely clear whether clang-format's behavior itself should
be modified, but for now this seems to be a safe change.

llvm-svn: 185423
2013-07-02 13:20:35 +00:00
Logan Chien c931fce404 Fix ARM EHABI compact model 1 and 2 without handlerdata.
According to ARM EHABI section 9.2, if the
__aeabi_unwind_cpp_pr1() or __aeabi_unwind_cpp_pr2() is
used, then the handler data must be emitted after the unwind
opcodes.  The handler data consists of several words, and
should be terminated by zero.

In case that the .handlerdata directive is not specified by
the programmer, we should emit zero to terminate the handler
data.

llvm-svn: 185422
2013-07-02 12:43:27 +00:00
Elena Demikhovsky e4fd5ed056 Fixed alignment of code sections in the JIT mode. Added a test to the JITMemoryManager.
llvm-svn: 185421
2013-07-02 12:24:22 +00:00
Rui Ueyama 2fa2a727bb Removed unused friend declaration.
llvm-svn: 185420
2013-07-02 11:13:43 +00:00
Tim Northover 6823900e55 DAGCombiner: fix use-counting issue when forming zextload
DAGCombiner was counting all uses of a load node  when considering whether it's
worth combining into a zextload. Really, it wants to ignore the chain and just
count real uses.

rdar://problem/13896307

llvm-svn: 185419
2013-07-02 09:58:53 +00:00
Daniel Jasper dba1c5587c Fix formatting of long declarations with const type.
Before (exceeding the column limit):
LoooooooooooooooooooooooooooooooooooooooongType const LoooooooooooooooooooooooooooooooooooooooongVariable;

After:
LoooooooooooooooooooooooooooooooooooooooongType const
LoooooooooooooooooooooooooooooooooooooooongVariable;

llvm-svn: 185418
2013-07-02 09:47:29 +00:00
Pavel Labath 868bebf844 Teach static analyzer about AttributedStmts
Summary:
Static analyzer used to abort when encountering AttributedStmts, because it
asserted that the statements should not appear in the CFG. This is however not
the case, since at least the clang::fallthrough annotation makes it through.

This commit simply makes the analyzer ignore the statement attributes.

CC: cfe-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1030

llvm-svn: 185417
2013-07-02 09:38:48 +00:00
Evgeniy Stepanov 1df4dfe87a [sanitizer] Intercept setlocale.
llvm-svn: 185416
2013-07-02 09:23:45 +00:00
Hal Finkel fdbe161b1a Revert r185257 (InstCombine: Be more agressive optimizing 'udiv' instrs with 'select' denoms)
I'm reverting this commit because:

 1. As discussed during review, it needs to be rewritten (to avoid creating and
then deleting instructions).

 2. This is causing optimizer crashes. Specifically, I'm seeing things like
this:

    While deleting: i1 %
    Use still stuck around after Def is destroyed:  <badref> = select i1 <badref>, i32 0, i32 1
    opt: /src/llvm-trunk/lib/IR/Value.cpp:79: virtual llvm::Value::~Value(): Assertion `use_empty() && "Uses remain when a value is destroyed!"' failed.

   I'd guess that these will go away once we're no longer creating/deleting
instructions here, but just in case, I'm adding a regression test.

Because the code is bring rewritten, I've just XFAIL'd the original regression test. Original commit message:

	InstCombine: Be more agressive optimizing 'udiv' instrs with 'select' denoms

	Real world code sometimes has the denominator of a 'udiv' be a
	'select'.  LLVM can handle such cases but only when the 'select'
	operands are symmetric in structure (both select operands are a constant
	power of two or a left shift, etc.).  This falls apart if we are dealt a
	'udiv' where the code is not symetric or if the select operands lead us
	to more select instructions.

	Instead, we should treat the LHS and each select operand as a distinct
	divide operation and try to optimize them independently.  If we can
	to simplify each operation, then we can replace the 'udiv' with, say, a
	'lshr' that has a new select with a bunch of new operands for the
	select.

llvm-svn: 185415
2013-07-02 05:21:11 +00:00
Nick Lewycky 26fcc51f15 Add missing break statements. Noticed by inspection.
llvm-svn: 185414
2013-07-02 05:02:56 +00:00
Tobias Grosser 38f66b233c Fix typo in comment
llvm-svn: 185413
2013-07-02 04:15:28 +00:00
Hal Finkel 52727c6b82 Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handling
There are a couple of (small) related changes here:

1. The printed name of the VRSAVE register has been changed from VRsave to
vrsave in order to match the name accepted by GNU binutils.

2. Support for parsing vrsave has been added to the asm parser (it seems that
there was no test case specifically covering this code, so I've added one).

3. The list of Altivec registers, which was common to all calling conventions,
has been separated out. This allows us to define the base CSR lists, and then
lists for each ABI with Altivec included. This allows SjLj, for example, to
work correctly on non-Altivec targets without using unnatural definitions of
the NoRegs CSR list.

4. VRSAVE is now always reserved on non-Darwin targets and all Altivec
registers are reserved when Altivec is disabled.

With these changes, it is now possible to compile a function containing
__builtin_unwind_init() on Linux/PPC64 with debugging information. This did not
work previously because GNU binutils assumes that all .cfi_offset offsets will
be 8-byte aligned on PPC64 (and errors out if you provide a non-8-byte-aligned
offset). This is not true for the vrsave register, however, because this
register is used only on Darwin, GCC does not bother printing a .cfi_offset
entry for it (even though there is a slot in the stack frame for it as
specified by the ABI). This change allows us to do the same: we will also not
print .cfi_offset directives for vrsave.

llvm-svn: 185409
2013-07-02 03:39:34 +00:00
Tobias Grosser effd02c91d IRVerifier: Correctly check attribute types
Add missing parenthesis such that all and not only the very first attribute
is checked.

Testing this piece of code is not possible with an LLVM-IR test file, as the
LLVM-IR parser has a similar check such that the wrong IR does not even arrive
at the verifier.

llvm-svn: 185408
2013-07-02 03:28:10 +00:00
Jim Ingham b0b4513ea2 Use the "last created watchpoint" rather than asserting on watchpoint commands passing no watchpoint ID.
<rdar://problem/14327560> 

llvm-svn: 185406
2013-07-02 02:09:46 +00:00
Eli Friedman 92821745bf Don't skip lambdas when mangling local vars.
This commit rearranges the logic in CXXNameMangler::mangleLocalName and
GetLocalClassDecl so that it doesn't accidentally skip over lambdas.  It
also reduces code duplication a bit.

llvm-svn: 185402
2013-07-02 02:01:18 +00:00
Jordan Rose 686df32216 [analyzer] Explicitly disallow mixed Loc-NonLoc comparisons.
The one bit of code that was using this is gone, and neither C nor C++
actually allows this. Add an assertion and remove dead code.

Found by Matthew Dempsky!

llvm-svn: 185401
2013-07-02 01:37:40 +00:00
Jason Molenda 54d04f3bec Change the default timeout for KDP communications to be 5 seconds.
<rdar://problem/13793059> 

llvm-svn: 185400
2013-07-02 01:29:59 +00:00
Akira Hatanaka b34ad7860f [mips] Add new InstrItinClasses for move from/to coprocessor instructions and
floating point loads and stores.

No changes in functionality.

llvm-svn: 185399
2013-07-02 00:00:02 +00:00
David Blaikie 8466ca86fe PR14728: DebugInfo: TLS variables with -gsplit-dwarf
llvm-svn: 185398
2013-07-01 23:55:52 +00:00
Michael Gottesman 228156c04f [APFloat] Ensure that we can properly parse strings that do not have null terminators.
rdar://14323230

llvm-svn: 185397
2013-07-01 23:54:08 +00:00
Richard Trieu 0e6e4aa5db Fix up some asserts that are within an if statement. This removes the need
for assert(0 && "text").

llvm-svn: 185396
2013-07-01 23:42:53 +00:00
Jakob Stoklund Olesen 3b4e9ccfe3 Tweak some comments that referred to the old bias computations.
llvm-svn: 185395
2013-07-01 23:36:37 +00:00
Ulrich Weigand f11efe7f48 [PowerPC] Add support for TLS data relocations
This adds support for TLS data relocations and modifiers:
       .quad target@dtpmod
       .quad target@tprel
       .quad target@dtprel
Currently exploited by the asm parser only.

llvm-svn: 185394
2013-07-01 23:33:29 +00:00
Jakob Stoklund Olesen 55daed27b7 Remove floating point computations form SpillPlacement.cpp.
Patch by Benjamin Kramer!

Use the BlockFrequency class instead of floats in the Hopfield network
computations. This rescales the node Bias field from a [-2;2] float
range to two block frequencies BiasN and BiasP pulling in opposite
directions. This construct has a more predictable behavior when block
frequencies saturate.

The per-node scaling factors are no longer necessary, assuming the block
frequencies around a bundle are consistent.

This patch can cause the register allocator to make different spilling
decisions. The differences should be small.

llvm-svn: 185393
2013-07-01 23:19:39 +00:00
Richard Trieu fab01e5cea Change if (cond) ... else llvm_unreachable("text") to assert(cond && "text") ...
llvm-svn: 185392
2013-07-01 23:06:23 +00:00
Howard Hinnant 4a142ec6b0 XFAIL this test on 10.7 and 10.8
llvm-svn: 185391
2013-07-01 22:59:14 +00:00
Ulrich Weigand 704ebd78cb [PowerPC] Fix 32-bit PowerPC TLS relocs
Some TLS relocs were copied incorrectly from ppc64 to ppc32,
and some were missing completely.

llvm-svn: 185390
2013-07-01 22:27:57 +00:00
David Blaikie 1b01ae8648 PR16493: DebugInfo with TLS on PPC crashing due to invalid relocation
Restrict the current TLS support to X86 ELF for now. Test that we don't
produce it on PPC & we can flesh that test case out with the right thing
once someone implements it.

llvm-svn: 185389
2013-07-01 21:45:25 +00:00
Greg Clayton ab70d5dbaa Added SymbolVendorELF to the wrong target (lldb-tool), now it is correctly added to lldb-core.
llvm-svn: 185388
2013-07-01 21:44:02 +00:00
Ulrich Weigand 85c6f7f7a7 [PowerPC] Support all condition register logical instructions
This adds support for all missing condition register logical
instructions and extended mnemonics to the asm parser.

llvm-svn: 185387
2013-07-01 21:40:54 +00:00
Greg Clayton 8918b4b4a2 Fixed Xcode project to include SymbolVendorELF.
llvm-svn: 185386
2013-07-01 21:37:51 +00:00
Chad Rosier 797ee3e3c6 Add a newline.
llvm-svn: 185385
2013-07-01 21:31:10 +00:00
Eli Friedman d02bbeb44e Simplify code in mangler.
llvm-svn: 185384
2013-07-01 21:29:48 +00:00
Manman Ren 74c188f026 Debug Info: clean up usage of Verify.
No functionality change. It should suffice to check the type of a debug info
metadata, instead of calling Verify.

llvm-svn: 185383
2013-07-01 21:02:01 +00:00
Greg Clayton 7fba2634f5 Recognize "decltype(nullptr)" as a valid DW_AT_name for DW_TAG_unspecified_type tags as meaning the C++11 null pointer type.
llvm-svn: 185382
2013-07-01 21:01:52 +00:00
Eli Friedman c48d31c31c Simplify linkage code for static local vars.
The key insight here is that weak linkage for a static local variable
should always mean linkonce_odr, because every file that needs it will
generate a definition.  We don't actually care about the precise linkage
of the parent context.  I feel a bit silly that I didn't realize this before.

llvm-svn: 185381
2013-07-01 20:53:07 +00:00
Bill Schmidt 48fc20a034 Index: test/CodeGen/PowerPC/reloc-align.ll
===================================================================
--- test/CodeGen/PowerPC/reloc-align.ll	(revision 0)
+++ test/CodeGen/PowerPC/reloc-align.ll	(revision 0)
@@ -0,0 +1,34 @@
+; RUN: llc -mcpu=pwr7 -O1 < %s | FileCheck %s
+
+; This test verifies that the peephole optimization of address accesses
+; does not produce a load or store with a relocation that can't be
+; satisfied for a given instruction encoding.  Reduced from a test supplied
+; by Hal Finkel.
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+%struct.S1 = type { [8 x i8] }
+
+@main.l_1554 = internal global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 -1, i8 -6, i8 57, i8 62, i8 -48, i8 0, i8 58, i8 80 }, align 1
+
+; Function Attrs: nounwind readonly
+define signext i32 @main() #0 {
+entry:
+  %call = tail call fastcc signext i32 @func_90(%struct.S1* byval bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*))
+; CHECK-NOT: ld {{[0-9]+}}, main.l_1554@toc@l
+  ret i32 %call
+}
+
+; Function Attrs: nounwind readonly
+define internal fastcc signext i32 @func_90(%struct.S1* byval nocapture %p_91) #0 {
+entry:
+  %0 = bitcast %struct.S1* %p_91 to i64*
+  %bf.load = load i64* %0, align 1
+  %bf.shl = shl i64 %bf.load, 26
+  %bf.ashr = ashr i64 %bf.shl, 54
+  %bf.cast = trunc i64 %bf.ashr to i32
+  ret i32 %bf.cast
+}
+
+attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
Index: lib/Target/PowerPC/PPCAsmPrinter.cpp
===================================================================
--- lib/Target/PowerPC/PPCAsmPrinter.cpp	(revision 185327)
+++ lib/Target/PowerPC/PPCAsmPrinter.cpp	(working copy)
@@ -679,7 +679,26 @@ void PPCAsmPrinter::EmitInstruction(const MachineI
       OutStreamer.EmitRawText(StringRef("\tmsync"));
       return;
     }
+    break;
+  case PPC::LD:
+  case PPC::STD:
+  case PPC::LWA: {
+    // Verify alignment is legal, so we don't create relocations
+    // that can't be supported.
+    // FIXME:  This test is currently disabled for Darwin.  The test
+    // suite shows a handful of test cases that fail this check for
+    // Darwin.  Those need to be investigated before this sanity test
+    // can be enabled for those subtargets.
+    if (!Subtarget.isDarwin()) {
+      unsigned OpNum = (MI->getOpcode() == PPC::STD) ? 2 : 1;
+      const MachineOperand &MO = MI->getOperand(OpNum);
+      if (MO.isGlobal() && MO.getGlobal()->getAlignment() < 4)
+        llvm_unreachable("Global must be word-aligned for LD, STD, LWA!");
+    }
+    // Now process the instruction normally.
+    break;
   }
+  }
 
   LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
   OutStreamer.EmitInstruction(TmpInst);
Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelDAGToDAG.cpp	(revision 185327)
+++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp	(working copy)
@@ -1530,6 +1530,14 @@ void PPCDAGToDAGISel::PostprocessISelDAG() {
       if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
         SDLoc dl(GA);
         const GlobalValue *GV = GA->getGlobal();
+        // We can't perform this optimization for data whose alignment
+        // is insufficient for the instruction encoding.
+        if (GV->getAlignment() < 4 &&
+            (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD ||
+             StorageOpcode == PPC::LWA)) {
+          DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
+          continue;
+        }
         ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags);
       } else if (ConstantPoolSDNode *CP =
                  dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {

llvm-svn: 185380
2013-07-01 20:52:27 +00:00
Chad Rosier fa705ee36c [ARMAsmParser] Sort the ARM register lists based on the encoding value, not the
tablegen enum values.  This should be the last fix due to fallout from r185094.

llvm-svn: 185379
2013-07-01 20:49:23 +00:00
Lang Hames 7d99d7977c Make PBQP require/preserve MachineLoopInfo - the spiller requires it.
llvm-svn: 185378
2013-07-01 20:47:47 +00:00
Sean Silva d01eead98c [docs] Amend confusing title
"Writing an LLVM Compiler Backend" can be misinterpreted as meaning
"backend" in the sense of "using LLVM as a backend for your compiler for
your new language". This new name is less ambiguous.

As a bonus, this brings the title in line with the file name.

llvm-svn: 185377
2013-07-01 20:45:12 +00:00
Akira Hatanaka 1af66c9b8a [mips] Reverse the order of source operands of shift and rotate instructions that
have three register operands.

No intended functionality changes.

llvm-svn: 185376
2013-07-01 20:39:53 +00:00
Ulrich Weigand f7152a8596 [PowerPC] Also add "msync" alias
This adds an alias for "msync" (which is used on Book E
systems instead of "sync").

llvm-svn: 185375
2013-07-01 20:39:50 +00:00
Eli Friedman 4747c71427 Fix CMakeLists.txt.
Sorry about that.

llvm-svn: 185374
2013-07-01 20:34:51 +00:00