Commit Graph

87 Commits

Author SHA1 Message Date
Evan Cheng eba57e41b3 Do not form ldrd / strd if the two dests / srcs are the same. Code clean up.
llvm-svn: 73413
2009-06-15 20:54:56 +00:00
Evan Cheng 1cf0f193b0 Silence a warning.
llvm-svn: 73406
2009-06-15 19:36:32 +00:00
Evan Cheng 1283c6a066 Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.

llvm-svn: 73381
2009-06-15 08:28:29 +00:00
Evan Cheng 185c9ef0a2 Add a ARM specific pre-allocation pass that re-schedule loads / stores from
consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.

This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.

llvm-svn: 73291
2009-06-13 09:12:55 +00:00
Evan Cheng 3158790e32 Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.
llvm-svn: 72955
2009-06-05 19:08:58 +00:00
Evan Cheng 7fce2cf0ba When merging multiple load / store instructions. Use the DebugLoc of the first one.
llvm-svn: 72952
2009-06-05 18:19:23 +00:00
Evan Cheng c154c1185c Code clean up: return vector by reference rather than by value. No functionality changes.
llvm-svn: 72950
2009-06-05 17:56:14 +00:00
Evan Cheng 7f5976e11b Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface.
llvm-svn: 72826
2009-06-04 01:15:28 +00:00
Evan Cheng ab0c710fae Temporarily revert 72756 for now.
llvm-svn: 72757
2009-06-03 07:40:47 +00:00
Evan Cheng dfe6e689fd Fold preceding / trailing base inc / dec into the single load / store as well.
llvm-svn: 72756
2009-06-03 06:14:58 +00:00
Bill Wendling f7b83c7ae7 Change MachineInstrBuilder::addReg() to take a flag instead of a list of
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.

I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).

llvm-svn: 71722
2009-05-13 21:33:08 +00:00
Dale Johannesen 7647da67ea Remove refs to non-DebugLoc versions of BuildMI from ARM.
llvm-svn: 64429
2009-02-13 02:25:56 +00:00
Dan Gohman 0d1e9a8e04 Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.

llvm-svn: 57006
2008-10-03 15:45:36 +00:00
Dan Gohman a79db30d28 Tidy up several unbeseeming casts from pointer to intptr_t.
llvm-svn: 55779
2008-09-04 17:05:41 +00:00
Dan Gohman 3a4be0fdef Rename MRegisterInfo to TargetRegisterInfo.
llvm-svn: 46930
2008-02-10 18:45:23 +00:00
Chris Lattner 596875118c rename MachineInstr::setInstrDescriptor -> setDesc
llvm-svn: 45871
2008-01-11 18:10:50 +00:00
Chris Lattner 03ad885039 rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.

llvm-svn: 45695
2008-01-07 07:27:27 +00:00
Chris Lattner b0d06b4381 Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
llvm-svn: 45680
2008-01-07 03:13:06 +00:00
Chris Lattner a98c679de0 Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
that it is cheap and efficient to get.

Move a variety of predicates from TargetInstrInfo into 
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around.  Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.

Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.

llvm-svn: 45674
2008-01-07 01:56:04 +00:00
Chris Lattner 5c4637816e Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
llvm-svn: 45453
2007-12-30 20:49:49 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Evan Cheng d0e360e16e Avoid referencing deleted instruction.
llvm-svn: 42153
2007-09-19 21:48:07 +00:00
Evan Cheng 9d41b311fb Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
llvm-svn: 38501
2007-07-10 18:08:01 +00:00
Evan Cheng 94f04c6fc9 Reflects the chanegs made to PredicateOperand.
llvm-svn: 37898
2007-07-05 07:18:20 +00:00
Evan Cheng 2d91a4fd6a Add missing const qualifiers.
llvm-svn: 37342
2007-05-29 18:42:18 +00:00
Evan Cheng 0f7cbe8370 Add PredicateOperand to all ARM instructions that have the condition field.
llvm-svn: 37066
2007-05-15 01:29:07 +00:00
Devang Patel 8c78a0bff0 Drop 'const'
llvm-svn: 36662
2007-05-03 01:11:54 +00:00
Devang Patel e95c6ad802 Use 'static const char' instead of 'static const int'.
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.

llvm-svn: 36652
2007-05-02 21:39:20 +00:00
Devang Patel 09f162ca6a Do not use typeinfo to identify pass in pass manager.
llvm-svn: 36632
2007-05-01 21:15:47 +00:00
Evan Cheng 910c80851e Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.
llvm-svn: 36483
2007-04-26 19:00:32 +00:00
Evan Cheng 7dbbd00b06 findRegisterUseOperand() changed.
llvm-svn: 35366
2007-03-26 22:41:48 +00:00
Evan Cheng 977195e912 Bug fix. Not advancing the register scavenger iterator correctly.
llvm-svn: 35020
2007-03-08 02:55:08 +00:00
Evan Cheng f030f2d628 Only safe to use a call-clobbered or spilled callee-saved register as scratch register.
llvm-svn: 35010
2007-03-07 20:30:36 +00:00
Evan Cheng 2818fdd019 Fix some brittle code. Watch out for cases where register scavenger is pointing to deleted instructions.
llvm-svn: 34998
2007-03-07 02:38:05 +00:00
Evan Cheng 41bc2fd242 Make load / store optimizer use register scavenger.
llvm-svn: 34986
2007-03-06 21:59:20 +00:00
Evan Cheng d28de6700b Code clean up. Prepare to use register scavenger.
llvm-svn: 34976
2007-03-06 18:02:41 +00:00
Evan Cheng 10043e215b ARM backend contribution from Apple.
llvm-svn: 33353
2007-01-19 07:51:42 +00:00