Commit Graph

2312 Commits

Author SHA1 Message Date
Justin Bogner 7fa2eb9f49 Revert r193994 and part of r193995
Not long ago I made the CodeGen of for loops simplify the condition at
-O0 in the same way we do for if and conditionals. Unfortunately this
ties how loops and simple conditions work together too tightly, which
makes features such as instrumentation based PGO awkward.

Ultimately, we should find a more general way to simplify the logic in
a given condition, but for now we'll just avoid using EmitBranchOnBool
for loops, like we already do for while and do loops.

llvm-svn: 195438
2013-11-22 10:20:43 +00:00
Artyom Skrobov be36c42df6 Deleting three tests that are redundant with test/Preprocessor/arm-target-features.c and test/Driver/arm-cortex-cpus.c
llvm-svn: 195430
2013-11-22 09:21:51 +00:00
Jiangning Liu 72b624ac16 For AArch64, intrinsic vget_low_xxx can be optimized away.
llvm-svn: 195409
2013-11-22 02:46:20 +00:00
Ana Pazos dbd1a22496 Implemented Neon scalar vdup_lane intrinsics.
Fixed scalar dup alias and added test case.

llvm-svn: 195329
2013-11-21 08:15:01 +00:00
Ana Pazos 2b02688fd9 Implemented Neon scalar by element intrinsics.
Intrinsics implemented: vqdmull_lane, vqdmulh_lane, vqrdmulh_lane,
vqdmlal_lane, vqdmlsl_lane scalar Neon intrinsics.

llvm-svn: 195326
2013-11-21 07:36:33 +00:00
Justin Holewinski f9329ff650 [NVPTX] Update ABI handling
For PTX, we want the target to handle struct returns directly.

llvm-svn: 195268
2013-11-20 20:35:34 +00:00
Reid Kleckner cc99e26475 Add a mangler entry point for TBAA rather than using RTTI directly
Summary:
RTTI is not yet implemented for the Microsoft C++ ABI and isn't expected
soon.  We could easily add the mangling, but the error is what prevents
us from silently miscompiling code that expects RTTI.

Instead, add a new mangleTypeName entry point that simply forwards to
mangleName or mangleType to produce a string that isn't part of the ABI.
Itanium can continue to use RTTI names to avoid unecessary test
breakage.

This also seems like the right design.  The fact that TBAA names happen
to be RTTI names is now an implementation detail of the mangler, rather
than part of TBAA.

Differential Revision: http://llvm-reviews.chandlerc.com/D2153

llvm-svn: 195168
2013-11-19 23:23:00 +00:00
Hao Liu 171cedf61e Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.
llvm-svn: 195079
2013-11-19 02:17:31 +00:00
Jiangning Liu fe916e20f2 Implement AArch64 SISD intrinsics for vget_high and vget_low.
llvm-svn: 195073
2013-11-19 01:46:34 +00:00
Jiangning Liu 3311f374a8 Add predicate for AArch64 crypto instructions.
llvm-svn: 195069
2013-11-19 01:38:19 +00:00
Hao Liu 5e4ce1ae9d Implement the newly added AArch64 ACLE functions for ld1/st1 with 2/3/4 vectors.
The functions are like: vst1_s8_x2 ...

llvm-svn: 194991
2013-11-18 06:33:43 +00:00
Hao Liu 9e49704f59 Implement vreinterpret ACLE functions in Clang.
llvm-svn: 194954
2013-11-17 09:32:59 +00:00
Ana Pazos 6f2a47a9e5 Implemented aarch64 Neon scalar vmulx_lane intrinsics
Implemented aarch64 Neon scalar vfma_lane intrinsics
Implemented aarch64 Neon scalar vfms_lane intrinsics

Implemented legacy vmul_n_f64, vmul_lane_f64, vmul_laneq_f64
intrinsics (v1f64 parameter type) using Neon scalar instructions.

Implemented legacy vfma_lane_f64, vfms_lane_f64,
vfma_laneq_f64, vfms_laneq_f64 intrinsics (v1f64 parameter type)
using Neon scalar instructions.

llvm-svn: 194889
2013-11-15 23:33:31 +00:00
Chad Rosier 7fa60db4a9 These ACLE tests no longer need to cast the return value.
llvm-svn: 194854
2013-11-15 21:28:24 +00:00
Chad Rosier 7aaee48bf0 [AArch64] Add support for legacy AArch32 NEON scalar shift right by immediate
and accumulate instructions.

llvm-svn: 194732
2013-11-14 22:02:24 +00:00
Kevin Qin 3058bf4533 Remove a test failure.
llvm-svn: 194678
2013-11-14 07:00:00 +00:00
Kevin Qin 91ac11387c Add test case for AArch64 NEON poly64 intrinsic.
llvm-svn: 194674
2013-11-14 06:49:00 +00:00
Kevin Qin 9e255dd532 Add test cases for AArch64 NEON instruction set misc.
llvm-svn: 194672
2013-11-14 06:44:42 +00:00
Jiangning Liu 18b707cb3f Implement AArch64 NEON instruction set AdvSIMD (table).
llvm-svn: 194649
2013-11-14 01:57:55 +00:00
Reid Kleckner 59e4a6f5e2 -fms-extensions: Recognize _alloca as an alias for the alloca builtin
Differential Revision: http://llvm-reviews.chandlerc.com/D1989

llvm-svn: 194617
2013-11-13 22:58:53 +00:00
Reid Kleckner cf8933d1b7 Only provide MS builtins when -fms-extensions is on
We already have builtins that are only available in GNU mode, so this
mirrors that.

Reviewers: rsmith

Differential Revision: http://llvm-reviews.chandlerc.com/D2128

llvm-svn: 194615
2013-11-13 22:47:22 +00:00
Chad Rosier e714a962b5 [AArch64] Tests for legacy AArch32 NEON scalar shift by immediate instructions.
A number of non-overloaded intrinsics have been replaced by thier overloaded
counterparts.

llvm-svn: 194599
2013-11-13 20:05:44 +00:00
Weiming Zhao 87bb4920e9 add intrinsics: __builtin_arm_{dmb,dsb} for ARM
llvm-svn: 194513
2013-11-12 21:42:50 +00:00
Daniel Sanders 8b59af15ed [mips][msa] Enable inlinse assembly for MSA.
Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier:
  asm ("ldi.w %w0, 1", "=f"(result));

Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended
output. This is a consequence of differences in the internal handling of
the registers in each compiler. To be source-compatible between the
compilers, users must use the 'w' print-modifier.

MSA registers (including control registers) are supported in clobber lists.

llvm-svn: 194476
2013-11-12 12:56:01 +00:00
Daniel Sanders 9626df1eb2 [mips] Added fpu register tests to tests/CodeGen/mips-clobber-reg.c
llvm-svn: 194474
2013-11-12 11:38:20 +00:00
Daniel Sanders 923af19f29 [mips] Small fixes to test/CodeGen/mips-clobber-reg.c
Fixed the following:
- Whitespace at end of most lines
- $11 test actually testing $10

llvm-svn: 194473
2013-11-12 11:15:48 +00:00
Robert Lytton eaf6f36e6d XCore target requires preferred alignment.
The xcore llvm backend does not handle 8 byte alignment viz:
  "%BadAlignment = alloca i64, align 8"
So getPreferredTypeAlign() must never overalign.

llvm-svn: 194462
2013-11-12 10:09:34 +00:00
Akira Hatanaka c4baedd71d [mips] Partially revert r193640. Stack alignment should not be determined by
the floating point register mode.

llvm-svn: 194426
2013-11-11 22:10:46 +00:00
Chad Rosier 09f5251c4d [AArch64] The shift right/left and insert immediate builtins expect 3
source operands, a vector, an element to insert, and a shift amount.

llvm-svn: 194407
2013-11-11 19:11:19 +00:00
Chad Rosier 249c714bb4 [AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions.
llvm-svn: 194395
2013-11-11 18:04:22 +00:00
Will Dietz 949ec546c4 ubsan: Only emit constants for filenames and type descriptors once.
Produces neater IR in significantly less time.

(~18% faster -O0 compile time for sqlite3 with -fsanitize=undefined)

llvm-svn: 194231
2013-11-08 01:09:22 +00:00
Jiangning Liu c628af66c7 Implement AArch64 Neon instruction set Perm.
llvm-svn: 194124
2013-11-06 03:35:53 +00:00
Jiangning Liu 37f5bb1b28 Implement AArch64 Neon instruction set Bitwise Extract.
llvm-svn: 194119
2013-11-06 02:26:12 +00:00
Jiangning Liu 34a7109b47 Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA.
llvm-svn: 194086
2013-11-05 17:42:24 +00:00
Kevin Qin 9eece7b5e0 Implemented aarch64 neon intrinsic vcopy_lane with float type.
llvm-svn: 194042
2013-11-05 02:05:44 +00:00
Justin Bogner e0ccdb1a28 CodeGen: Test that simple expressions are simplified at -O0
llvm-svn: 193995
2013-11-04 16:13:23 +00:00
Bob Wilson 2c82c3d033 OS X 10.9+ and iOS 7+ support load/store of big atomic objects.
rdar://13973577

Patch by Fariborz Jahanian.

llvm-svn: 193935
2013-11-02 23:27:49 +00:00
Chad Rosier 74329d6cff [AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions.
llvm-svn: 193817
2013-10-31 22:37:08 +00:00
Chad Rosier bdca387884 [AArch64] Add support for NEON scalar shift immediate instructions.
llvm-svn: 193791
2013-10-31 19:29:05 +00:00
Daniel Sanders d5f554f0bb [mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related tests
llvm-svn: 193695
2013-10-30 15:45:42 +00:00
Daniel Sanders ab94b537d7 [mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from normal IR (i.e. not intrinsics)
Also corrected the definition of the intrinsics for these instructions (the
result register is also the first operand), and added intrinsics for bsel and
bseli to clang (they already existed in the backend).

These four operations are mostly equivalent to bsel, and bseli (the difference
is which operand is tied to the result). As a result some of the tests changed
as described below.

bitwise.ll:
- bsel.v test adapted so that the mask is unknown at compile-time. This stops
  it emitting bmnzi.b instead of the intended bsel.v.
- The bseli.b test now tests the right thing. Namely the case when one of the
  values is an uimm8, rather than when the condition is a uimm8 (which is
  covered by bmnzi.b)

compare.ll:
- bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this
  is the same operation (see MSA.txt).

i8.ll
- CHECK-DAG-ized test.
- bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands
  because this is the same operation (see MSA.txt).
- bseli.b still emits bseli.b though because the immediate makes it
  distinguishable from bmnzi.b.

vec.ll:
- CHECK-DAG-ized test.
- bmz.v tests now (correctly) emits bmnz.v with swapped operands (see
  MSA.txt).
- bsel.v tests now (correctly) emits bmnz.v with swapped operands (see
  MSA.txt).

llvm-svn: 193693
2013-10-30 15:20:38 +00:00
Chad Rosier 4d55e6e0a4 [AArch64] Add support for NEON scalar floating-point compare instructions.
llvm-svn: 193692
2013-10-30 15:20:07 +00:00
Daniel Sanders d74b130cc9 [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics)
This required correcting the definition of the bins[lr]i intrinsics because
the result is also the first operand.

It also required removing the (arbitrary) check for 32-bit immediates in
MipsSEDAGToDAGISel::selectVSplat().

Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d
because the constant is legalized into a ConstantPool. Similar things can
happen with binsri.d with more than 10 bits set in the mask. The resulting
code when this happens is correct but not optimal.

llvm-svn: 193687
2013-10-30 14:45:14 +00:00
Akira Hatanaka 618b29813a [mips] Align the stack to 16-bytes for -mfp64.
llvm-svn: 193640
2013-10-29 19:00:35 +00:00
Richard Smith 426a47bddb Fix a parser crash when there are #pragmas in a context which requires a single
statement (after a case label, if, etc). Patch by Olivier Goffart!

llvm-svn: 193545
2013-10-28 22:04:30 +00:00
Alp Toker a933f94c92 FileCheckize
llvm-svn: 193474
2013-10-26 15:43:55 +00:00
Alp Toker 1774954274 Quote wildcard in test's grep argument
The * could otherwise cause shell pathname expansion.

llvm-svn: 193473
2013-10-26 14:52:48 +00:00
Manman Ren c94122e05b Intrinsics: fix extract & insert when index is out of bound.
Now, all extract & insert intrinsics should have the correct and operation
to ignore higher bits.

rdar://15250497

llvm-svn: 193267
2013-10-23 20:33:14 +00:00
Daniel Sanders ffd8df29b6 [mips][msa] Add intrinsics that map to pseudo-instructions.
Unlike the previously added intrinsics, these do not map to a single instruction
on MIPS32. They are provided for regularity (to round out the .[bhw] variants
of the same operation) and compatibility with GCC.

Includes:
  copy_[us].d, fill.d, insert.d, insve.d

llvm-svn: 193237
2013-10-23 10:12:44 +00:00
Richard Smith 6b53e224eb Split -fsanitize=bounds to -fsanitize=array-bounds (for the frontend-inserted
check using the ubsan runtime) and -fsanitize=local-bounds (for the middle-end
check which inserts traps).

Remove -fsanitize=local-bounds from -fsanitize=undefined. It does not produce
useful diagnostics and has false positives (PR17635), and is not a good
compromise position between UBSan's checks and ASan's checks.

Map -fbounds-checking to -fsanitize=local-bounds to restore Clang's historical
behavior for that flag.

llvm-svn: 193205
2013-10-22 22:51:04 +00:00
Rafael Espindola d53ffa0a70 Treat aliases as definitions.
This fixes pr17639.

Before this patch clang would consider

void foo(void) __attribute((alias("__foo")));

a declaration. It now correctly handles it as a definition.

Initial patch by Alp Toker. I added support for variables.

llvm-svn: 193200
2013-10-22 21:39:03 +00:00
Manman Ren be38b9e15f _mm_extract_epi16: use "& 7" when index is out of bound.
This is in line with implementation of _mm_extract_pi16.
rdar://15250497

llvm-svn: 193187
2013-10-22 19:24:42 +00:00
Chad Rosier c2a0b13c25 [AArch64] Add the constraint to NEON scalar mla/mls instructions.
llvm-svn: 193118
2013-10-21 20:12:01 +00:00
Rafael Espindola 156f634aa1 Make this test pass -verify.
Instead of using not, just drop the fastcall attribute which was causing
an warning:

calling convention 'fastcall' ignored for this target

llvm-svn: 193110
2013-10-21 19:48:28 +00:00
Matheus Almeida 70fbf77546 [mips][msa] Fix definition of SLD instruction.
The second parameter of the SLD intrinsic is the number of columns (GPR) to 
slide left the source array.

llvm-svn: 193076
2013-10-21 11:47:56 +00:00
Chad Rosier 3c03dee1d1 [AArch64] Add support for NEON scalar extract narrow instructions.
llvm-svn: 192971
2013-10-18 14:03:36 +00:00
Chad Rosier e7465644c6 [AArch64] Add support for NEON scalar three register different instruction
class.  The instruction class includes the signed saturating doubling
multiply-add long, signed saturating doubling multiply-subtract long, and
the signed saturating doubling multiply long instructions.

llvm-svn: 192909
2013-10-17 18:12:50 +00:00
Daniel Sanders c835a9fe80 [mips][msa] Added most of the remaining builtins
Includes:
and.v, bmnz.v, bmz.v, bnz.[bhwdv], bz.[bhwdv], cfcmsa, ctcmsa, fcaf,
fcor, fcueq, fcul[et], fcun, fcune, fsaf, fsueq, fsul[et], fsun, fsune, ftrunc
hadd_[su].[hwd], hsub_[su].[hwd], insert.[bhw], insve.[bhw], ld.[bhwd],
move.v, nor.v, or.v, srar.[bhwd], srari.[bhwd], srlr.[bhwd], srlri.[bhwd],
st.[bhwd], subsus_u.[bhwd], subsuu_s.[bhwd], vshf.[bhwd], xor.v

llvm-svn: 192896
2013-10-17 13:57:25 +00:00
Chad Rosier 00eef17dbe [AArch64] Add support for NEON scalar negate instruction.
llvm-svn: 192845
2013-10-16 21:04:53 +00:00
Chad Rosier e904137c01 [AArch64] Add support for NEON scalar absolute value instruction.
llvm-svn: 192844
2013-10-16 21:04:49 +00:00
Chad Rosier 069b90463d [AArch64] Add support for NEON scalar signed saturating accumulated of unsigned
value and unsigned saturating accumulate of signed value instructions.

llvm-svn: 192801
2013-10-16 16:09:16 +00:00
Rafael Espindola 002667c32b On 32 bit windows, mangle stdcall and fastcall decls in clang.
This removes the dependency on the llvm mangler doing it for us. In isolation,
the benefit is that the testing of what mangling is applied is all in one place:
(C, C++) X (Itanium, Microsoft) are all handled by clang.

This also gives me hope that in the future the llvm mangler (and llvm-ar) will
not depend on TargetMachine.

llvm-svn: 192762
2013-10-16 01:40:34 +00:00
Chad Rosier a70fb7b716 [AArch64] Add support for NEON scalar signed saturating absolute value and
scalar signed saturating negate instructions.

llvm-svn: 192734
2013-10-15 21:19:02 +00:00
Rafael Espindola 3efc492092 Also don't hardcode the order on this test.
llvm-svn: 192603
2013-10-14 16:18:39 +00:00
Rafael Espindola e8d060dba9 Don't hardcode the order of the aliases.
llvm-svn: 192601
2013-10-14 16:05:12 +00:00
Chad Rosier 193573ec89 [AArch64] Add support for NEON scalar integer compare instructions.
llvm-svn: 192597
2013-10-14 14:37:40 +00:00
Manman Ren f5d9d348f7 Turn struct-path aware TBAA on by default.
Use -no-struct-path-tbaa to turn it off.
This is the same as r191695, which was reverted because it depends on a
commit that has issues.

llvm-svn: 192497
2013-10-11 20:48:38 +00:00
Warren Hunt 8f8bad723d Adds Microsoft compatiable C++ record layout code to clang.
llvm-svn: 192494
2013-10-11 20:19:00 +00:00
Robert Lytton 2d1969584a XCore : Fix bug in XCoreABIInfo::EmitVAArg()
Incorrect handling of 'double' and 'long long int'

llvm-svn: 192436
2013-10-11 10:29:34 +00:00
Nick Lewycky ce6a4aacb4 The emitted IR is the same, we need these flags to actually use the LLVM target.
Mark it as requiring the x86 target.

llvm-svn: 192417
2013-10-11 03:52:43 +00:00
Nick Lewycky 3a410fe085 Add -fno-function-sections and -fno-data-sections. Since
-f{function,data}-sections had no tests at all, add some, and verify that the
-fno variants work as well.

llvm-svn: 192413
2013-10-11 03:35:10 +00:00
Kevin Qin f22bf50443 Implemented aarch64 SIMD copy related ACLE intrinsic :
vget_lane, vset_lane, vcopy_lane, vcreate, vdup_n, vdup_lane, vmov_n.

llvm-svn: 192411
2013-10-11 02:34:30 +00:00
Hao Liu 1eade6d927 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 192362
2013-10-10 17:01:49 +00:00
Tim Northover 72ace5cf12 Revert "Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). "
This reverts commit r192351. The LLVM side broke the build and the Clang tests
will inevitably fail without it.

llvm-svn: 192356
2013-10-10 16:00:08 +00:00
Hao Liu c319193636 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).

E.g. ld1(3 registers version) will load 32-bit elements {A, B, C, D, E, F} sequentially into the three 64-bit vectors list {BA, DC, FE}.
E.g. ld3 will load 32-bit elements {A, B, C, D, E, F} into the three 64-bit vectors list {DA, EB, FC}.

llvm-svn: 192351
2013-10-10 14:59:36 +00:00
Hans Wennborg 1e109804f5 Tighten diagnostics for calling conventions on variadic functions
Follow-up from r192240.

This makes it an error to use callee-cleanup conventions on variadic
functions, except for __fastcall and __stdcall, which we ignore with
a warning for GCC and MSVC compatibility.

Differential Revision: http://llvm-reviews.chandlerc.com/D1870

llvm-svn: 192308
2013-10-09 18:10:25 +00:00
Chad Rosier 0a903478c6 [AArch64] Add support for NEON scalar floating-point reciprocal estimate,
reciprocal exponent, and reciprocal square root estimate instructions.

llvm-svn: 192243
2013-10-08 22:09:29 +00:00
Hans Wennborg 9112ac2136 Turn error about fastcall variadic function into warning in MS mode (PR12535)
MSVC allows this and silently falls back to __cdecl for variadic functions.
This patch turns Clang's error into a warning in MS mode and adds a test
to make sure we generate correct code.

Differential Revision: http://llvm-reviews.chandlerc.com/D1861

llvm-svn: 192240
2013-10-08 21:52:56 +00:00
Chad Rosier 0babda4b9c [AArch64] Add support for NEON scalar signed/unsigned integer to floating-point
convert instructions.

llvm-svn: 192232
2013-10-08 20:43:46 +00:00
Akira Hatanaka 71cd285dc8 [mips] Remove XFAIL.
Triple x86_64 has been added to the command line, so this test doesn't fail
on mips anymore.

llvm-svn: 192219
2013-10-08 19:08:54 +00:00
Manman Ren 4f755deaf6 TBAA: use the same format for scalar TBAA and struct-path aware TBAA.
An updated version of r191586 with bug fix.

Struct-path aware TBAA generates tags to specify the access path,
while scalar TBAA only generates tags to scalar types.

We should not generate a TBAA tag with null being the first field. When
a TBAA type node is null, the tag should be null too. Make sure we
don't decorate an instruction with a null TBAA tag.

Added a testing case for the bug reported by Richard with -relaxed-aliasing
and -fsanitizer=thread.

llvm-svn: 192145
2013-10-08 00:08:49 +00:00
Matt Arsenault 2f15263807 Fix objectsize tests after r192117
llvm-svn: 192120
2013-10-07 19:00:18 +00:00
Chad Rosier 027dfade54 [AArch64] Add support for NEON scalar arithmetic instructions:
SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS.

llvm-svn: 192112
2013-10-07 17:07:17 +00:00
Craig Topper d335c9da22 Use logical/arithmetic operations instead of builtins in tbmintrin.h. This way we can remove the intrinsic support from the backend.
llvm-svn: 192036
2013-10-05 17:08:42 +00:00
Jiangning Liu b96ebac02b Implement aarch64 neon instruction set AdvSIMD (Across).
llvm-svn: 192029
2013-10-05 08:22:55 +00:00
Rafael Espindola aa2976f388 Don't assume instruction names in the output.
llvm-svn: 191957
2013-10-04 14:42:00 +00:00
Amaury de la Vieuville 21bf6ed730 Do not emit undefined lsrh/ashr for NEON shifts
These IR instructions are undefined when the amount is equal to operand
size, but NEON right shifts support such shifts. Work around that by
emitting a different IR in these cases.

llvm-svn: 191953
2013-10-04 13:13:15 +00:00
Jiangning Liu 4617e9dc85 Implement aarch64 neon instruction set AdvSIMD (3V elem).
llvm-svn: 191945
2013-10-04 09:21:17 +00:00
Matthew Curtis 274a9cc84b Gracefully (and correctly) handle init of multiple union members
We now emit warnings when doing so and code generation is consistent
with GCC. Note that the C99 spec is unclear as to the precise
behavior.

See also ...
Bug:
  http://llvm.org/bugs/show_bug.cgi?id=16644 and

cfe-dev discussion:
  http://lists.cs.uiuc.edu/pipermail/cfe-dev/2013-September/031918.html

llvm-svn: 191890
2013-10-03 12:14:24 +00:00
Craig Topper d867805739 Change __builtin_ia32_bextri_u64 to take an i64imm to match up with LLVM backend changes.
An explicit cast is still needed in tbmintrin.h to convert any big integer down to i32imm.

Patch from Yunzhong Gao.

llvm-svn: 191872
2013-10-03 04:21:19 +00:00
Joey Gouly 75987a65f3 [ARM] Add a builtin to allow you to use the 'sevl' instruction.
llvm-svn: 191816
2013-10-02 10:00:18 +00:00
Tim Northover a484bc00ff Implement ARM GNU-style interrupt attribute
This attribute allows users to use a modified C or C++ function as an ARM
exception-handling function and, with care, to successfully return control to
user-space after the issue has been dealt with.

rdar://problem/14207019

llvm-svn: 191769
2013-10-01 14:34:25 +00:00
Richard Smith e4aaac506c Revert r191586 and r191695. They cause crashes when building with
-relaxed-aliasing.

llvm-svn: 191725
2013-10-01 02:20:23 +00:00
Manman Ren e5c2d919b6 Turn struct-path aware TBAA on by default.
Use -no-struct-path-tbaa to turn it off.

llvm-svn: 191695
2013-09-30 19:35:19 +00:00
Yunzhong Gao f4e0b1047a Adding intrinsics to the clang front end for the x86 TBM instruction set.
Differential Revision: http://llvm-reviews.chandlerc.com/D1751

llvm-svn: 191681
2013-09-30 17:25:14 +00:00
Benjamin Kramer 5352717508 The second parameter of nexttoward is always long double.
llvm-svn: 191623
2013-09-28 17:41:03 +00:00
Manman Ren 4f04263347 TBAA: use the same format for scalar TBAA and struct-path aware TBAA.
Struct-path aware TBAA generates tags to specify the access path,
while scalar TBAA only generates tags to scalar types.

llvm-svn: 191586
2013-09-27 23:06:41 +00:00
Jiangning Liu 036f16dc8c Initial support for Neon scalar instructions.
Patch by Ana Pazos.

1.Added support for v1ix and v1fx types.
2.Added Scalar Pairwise Reduce instructions.
3.Added initial implementation of Scalar Arithmetic instructions.

llvm-svn: 191264
2013-09-24 02:48:06 +00:00
Eli Friedman 3cd55f49ab Fix argument types of some AVX2 intrinsics.
This fix makes our headers consistent with gcc.

PR17312.

llvm-svn: 191248
2013-09-23 23:52:04 +00:00
Eli Friedman f9d8c6cebb Add _mm_stream_si64 intrinsic.
While I'm here, also fix the alignment computation for the whole family of
intrinsics.

PR17298.

llvm-svn: 191243
2013-09-23 23:38:39 +00:00
Eli Friedman 9b04f41899 Fix return type of _mm_extract_epi8 etc.
PR17300.

llvm-svn: 191120
2013-09-21 00:05:25 +00:00
Ben Langmuir ed6e97d2c3 Fix ifdef macro missed in previous commit
llvm-svn: 191003
2013-09-19 14:07:14 +00:00
Ben Langmuir 58078d0103 Add C intrinsics for Intel SHA Extensions
Intrinsics added shaintrin.h, which is included from x86intrin.h if __SHA__ is
enabled. SHA implies SSE2, which is needed for the __m128i type.

Also add the -msha/-mno-sha option.

llvm-svn: 190999
2013-09-19 13:22:04 +00:00
Adrian Prantl 0315f38a92 Debug info: Explicitly set the DIVariable::isIndirect() flag for VLAs.
This allows us to get rid of an ugly hack in the backend.
Paired commit with LLVM.

llvm-svn: 190960
2013-09-18 22:08:57 +00:00
Joey Gouly 1e8637b259 [ARMv8] Add builtins for CRC instructions.
Patch by Bradley Smith!

llvm-svn: 190931
2013-09-18 10:07:09 +00:00
Amaury de la Vieuville 718ce62b3c Add support for poly16 vtst and vtstq
vtst and vtstq currently support poly8 types, but they should also work on
poly16.

llvm-svn: 190925
2013-09-18 08:33:53 +00:00
Hal Finkel 33be5e0e5c Add new libm LIBBUILTIN definitions, synchronizing with __builtin_*
For all libm __builtin_* functions that are defined, this adds the
corresponding LIBBUILTIN definitions (tagged, as necessary, with "e" instead of
"c" when the function may set errno).

Note that this changes the current definitions for lrint and fma
(unfortunately). The Linux man page documents that these don't set errno, but
the POSIX standard says that they should.

llvm-svn: 190922
2013-09-18 06:19:40 +00:00
Hal Finkel c4d7c82c7f Add the intrinsic __builtin_convertvector
LLVM supports applying conversion instructions to vectors of the same number of
elements (fptrunc, fptosi, etc.) but there had been no way for a Clang user to
cause such instructions to be generated when using builtin vector types.

C-style casting on vectors is already defined in terms of bitcasts, and so
cannot be used for these conversions as well (without leading to a very
confusing set of semantics). As a result, this adds a __builtin_convertvector
intrinsic (patterned after the OpenCL __builtin_astype intrinsic). This is
intended to aid the creation of vector intrinsic headers that create generic IR
instead of target-dependent intrinsics (in other words, this is a generic
_mm_cvtepi32_ps). As noted in the documentation, the action of
__builtin_convertvector is defined in terms of the action of a C-style cast on
each vector element.

llvm-svn: 190915
2013-09-18 03:29:45 +00:00
Reid Kleckner 543a16c06b Emit an error when attempting to generate IR for SEH __try
Currently we silently omit the code in the try and finally bodies, which
is pretty bad.  This way we fail loudly.

llvm-svn: 190809
2013-09-16 21:46:30 +00:00
Amara Emerson 8c3de546d6 Add error checking to reject neon_vector_type attribute on targets without NEON.
Patch by Artyom Skrobov.

llvm-svn: 190801
2013-09-16 18:07:35 +00:00
Hal Finkel 28b2ae3692 Restore the sqrt -> llvm.sqrt mapping in fast-math mode
This restores the sqrt -> llvm.sqrt mapping, but only in fast-math mode
(specifically, when the UnsafeFPMath or NoNaNsFPMath CodeGen options are
enabled). The @llvm.sqrt* intrinsics have slightly different semantics from the
libm call, specifically, they are undefined when given a non-zero negative
number (the libm calls will always return NaN for any negative number).

This mapping was removed in r100613, and replaced with a TODO, but at that time
the fast-math flags were not yet implemented. Now that we have these, restoring
this mapping is important because it will enable autovectorization of sqrt
calls in loops (at least in fast-math mode).

llvm-svn: 190646
2013-09-12 23:57:55 +00:00
Daniel Sanders cb2929c239 [mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsics
The elements of the operands should be half the width of the elements of
the result.

llvm-svn: 190505
2013-09-11 09:59:17 +00:00
Daniel Sanders 3615c45d76 [mips][msa] Removed unsupported dot product instructions (dotp_[su].b).
The dotp_[su].b instructions never existed in any revision of the MSA spec.

llvm-svn: 190399
2013-09-10 10:10:39 +00:00
Jiangning Liu 1bda93a252 Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the following 26 instructions,
SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL

llvm-svn: 190289
2013-09-09 02:21:08 +00:00
Hal Finkel 746b530a7d Add the missing "n" to libm LIBBUILTIN definitions
The libm math functions should be marked with the "n" (nothrow) flag so that
the corresponding IR function declarations are tagged with the nounwind
attribute (this has been true in C mode, but not in C++ mode).

The test case has been updated to run in C++ mode in addition to in C mode.

llvm-svn: 190217
2013-09-06 23:23:32 +00:00
Hao Liu b1852eed38 Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:
sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshr$
 and 4 convert instructions:
      scvtf,ucvtf,fcvtzs,fcvtzu

llvm-svn: 189926
2013-09-04 09:29:13 +00:00
Rafael Espindola d120b89a77 Disable llvm optimizations, but keep -O1 to test available_externally.
llvm-svn: 189918
2013-09-04 04:55:03 +00:00
Rafael Espindola 01caeb80cd Use %clang_cc1.
llvm-svn: 189917
2013-09-04 04:51:39 +00:00
Rafael Espindola ff7cea8c1a Don't pass -O0 to clang_cc1, it is the default.
llvm-svn: 189910
2013-09-04 04:12:25 +00:00
Jim Grosbach 362bf98ec6 ARM: Update testcases for improved codegen.
From llvm r189841.

llvm-svn: 189842
2013-09-03 20:08:30 +00:00
Eric Christopher 0819816887 Attempt to migrate default dwarf version to 4 for linux.
llvm-svn: 189823
2013-09-03 16:10:12 +00:00
Jin-Gu Kang 09c2213ce6 the call to UsualArithmeticConversions should come after the call to CheckVectorOperands on CheckConditionalOperands function. This problem caused compilation error with test17 on "test/CodeGen/ext-vector.c".
llvm-svn: 189773
2013-09-02 20:32:37 +00:00
Yunzhong Gao 0ebf1bb150 Revert r189649 because it was breaking sanitizer bots.
llvm-svn: 189660
2013-08-30 08:53:09 +00:00
Yunzhong Gao be8d7ba93a Fixing a bug where debug info for a local variable gets emitted at file scope.
The patch was discussed in Phabricator. See:
http://llvm-reviews.chandlerc.com/D1281

llvm-svn: 189649
2013-08-30 05:37:02 +00:00
Charles Davis b5a214e4f3 Add ms_abi and sysv_abi attribute handling.
Based on a patch by Benno Rice!

llvm-svn: 189644
2013-08-30 04:39:01 +00:00
Reid Kleckner 78af0708b7 Delete CC_Default and use the target default CC everywhere
Summary:
Makes functions with implicit calling convention compatible with
function types with a matching explicit calling convention.  This fixes
things like calls to qsort(), which has an explicit __cdecl attribute on
the comparator in Windows headers.

Clang will now infer the calling convention from the declarator.  There
are two cases when the CC must be adjusted during redeclaration:
1. When defining a non-inline static method.
2. When redeclaring a function with an implicit or mismatched
convention.

Fixes PR13457, and allows clang to compile CommandLine.cpp for the
Microsoft C++ ABI.

Excellent test cases provided by Alexander Zinenko!

Reviewers: rsmith

Differential Revision: http://llvm-reviews.chandlerc.com/D1231

llvm-svn: 189412
2013-08-27 23:08:25 +00:00
Manman Ren 4ae7ea6745 Debug Info: follow-up patch to r189283.
Thanks David for his suggestion. This commit updates testing cases
to have more specific CHECKs.

llvm-svn: 189286
2013-08-26 23:19:37 +00:00
Manman Ren c4ca9b0d3a Debug Info: add an identifier field to DICompositeType.
Paired with llvm r189282.
Update testing cases to handle an extra field for DICompositeType.

llvm-svn: 189283
2013-08-26 22:40:31 +00:00
Wei Pan 8d6b19a518 Handle predefined expression for a captured statement
- __func__ or __FUNCTION__ returns captured statement's parent
  function name, not the one compiler generated.

Differential Revision: http://llvm-reviews.chandlerc.com/D1491

Reviewed by bkramer

llvm-svn: 189219
2013-08-26 14:27:34 +00:00
Robert Lytton bff06ce221 correct test RUN parameters
llvm-svn: 189093
2013-08-23 09:27:44 +00:00
Bill Wendling a74e82aad8 Check for absence of the flag.
llvm-svn: 189069
2013-08-22 21:30:21 +00:00
Manman Ren 2470d87adc TBAA: add testing case to check typedef can alias.
llvm-svn: 188931
2013-08-21 21:00:10 +00:00
Manman Ren 879ce8841d Don't use mangleCXXRTTIName in TBAA for C code.
With r185721, calling mangleCXXRTTIName on C code will cause crashes.
This commit fixes crashes on C testing cases when turning on struct-path TBAA.

For C code, we simply use the Decl name without the context. This can
cause two different structs having the same name, and may cause inaccurate but
conservative alias results.

llvm-svn: 188930
2013-08-21 20:58:45 +00:00
Manman Ren 3380ee5e60 Update testing case to use FileCheck instead of grep.
llvm-svn: 188929
2013-08-21 20:53:05 +00:00
Daniel Sanders b545c253d6 [mips][msa] Added fexdo, fexup[lr] builtins
llvm-svn: 188784
2013-08-20 09:47:12 +00:00
Robert Lytton 7d1db15ae1 XCore target: Add target specific EmitVAArg
This is so aggregates can be passed as var args too.

llvm-svn: 188664
2013-08-19 09:46:39 +00:00
Robert Lytton a7d1d865e5 XCore target: correct test layout
llvm-svn: 188663
2013-08-19 09:46:32 +00:00
Juergen Ributzka 2c2dbf4542 Fix the name and the type of the argument for intrinisc
_mm256_broadcastsi128_si256 to align with the Intel documentation.

This fixes bug PR 16581 and rdar:14747994.

llvm-svn: 188609
2013-08-17 16:40:09 +00:00
Jack Carter 77dce2f905 [Mips][msa] Added most builtins from add.a to xori
Includes:
add.a, adds_a, adds_s, adds_u, addv, addvi, andi.b, asub_[su], ave_[su],
aver_[su], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bset,
bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw],
div_[su], dotp_[su], dpadd_[su], dpsub_[su], fadd, fceq, fclass, fcl[et], fcne,
fdiv, fexp2, ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin,
fmin_a, fmsub, fmul, frint, fseq, fsle, fslt, fsne, fsqr, fsub, ftint_[su],
ftq, ilvev, ilvl, ilvod, ilvr, ldi, frcp, frsqrt, madd_q, maddr_q, maddv,
max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv,
mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf,
sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subv, subvi,
xori


Patch by Daniel Sanders

llvm-svn: 188461
2013-08-15 14:47:02 +00:00
Hao Liu 4efa1402fe Clang and AArch64 backend patches to support shll/shl and vmovl instructions and ACLE functions
llvm-svn: 188452
2013-08-15 08:26:30 +00:00
Stephen Lin 4362261b00 CHECK-LABEL-ify some code gen tests to improve diagnostic experience when tests fail.
llvm-svn: 188447
2013-08-15 06:47:53 +00:00
Arnold Schwaighofer 68443b0a14 Fix xcore tests to use regex.
llvm-svn: 188271
2013-08-13 14:51:38 +00:00
Robert Lytton 0e07649ae5 Add XCore target
llvm-svn: 188258
2013-08-13 09:43:10 +00:00
Tim Northover 19ae1175ae Fix FileCheck --check-prefix lines.
Various tests had sprung up over the years which had --check-prefix=ABC on the
RUN line, but "CHECK-ABC:" later on. This happened to work before, but was
strictly incorrect. FileCheck is getting stricter soon though.

Patch by Ron Ofir.

llvm-svn: 188174
2013-08-12 12:51:05 +00:00
Benjamin Kramer 588b35ed8f Add lrint to the list of math builtins. It never sets errno so we can mark it as readnone.
llvm-svn: 188065
2013-08-09 10:12:30 +00:00
Rafael Espindola 71eccb39b8 Fix alignof computation of large arrays on x86_64.
We were exposing the extra alignment given to large arrays. The new behavior
matches gcc, which is a good thing since this is a gcc extension.

Thanks to Joerg Sonnenberger for noticing it.

While at it, centralize the method description in the .h file.

llvm-svn: 187999
2013-08-08 19:53:46 +00:00
Hans Wennborg 75958c41e2 clang-cl: Support the run-time selection options (/MD, /MT et al.)
These flags set some preprocessor macros and injects a dependency
on the runtime library into the object file, which later is picked up
by the linker.

This also adds a new CC1 flag for adding a dependent library.

Differential Revision: http://llvm-reviews.chandlerc.com/D1315

llvm-svn: 187945
2013-08-08 00:17:41 +00:00
Rafael Espindola 885727581c Correctly allign arrays on 32 bit systems.
Before this patch we would align

long long int big[1024];

to 4 bytes on 32 bit systems. The problem is that we were only looking
at the element type when getLargeArrayMinWidth returned non zero.

llvm-svn: 187897
2013-08-07 18:08:19 +00:00
Craig Topper 50ad5b7354 Add support for passing -1 to __builtin_shufflevector to signify an undefined element value to match IR capabilities.
llvm-svn: 187694
2013-08-03 17:40:38 +00:00
David Blaikie 79af384d72 DebugInfo: Don't prefer declarations over definitions in -flimit-debug-info in C
Without an ODR, the -flimit-debug-info debug info size optimization of
emitting declarations for fully defined types when only a declaration is
needed by the TU, is incorrect. Emit the full definition whenever it's
available in non-C++.

llvm-svn: 187611
2013-08-01 20:57:40 +00:00