Commit Graph

49868 Commits

Author SHA1 Message Date
Simon Pilgrim 3bf2d64589 [InstCombine] Check for out of range shift values using APInt before calling getZExtValue
Reduced from oss-fuzz #4871 test case

llvm-svn: 321748
2018-01-03 18:28:20 +00:00
Craig Topper cc6637b707 [X86] Use ANY_EXTEND instead of SIGN_EXTEND in lowerMasksToReg
Currently we use SIGN_EXTEND in lowerMasksToReg as part of calling convention setup, but we don't require a specific value for the upper bits.

This patch changes it to ANY_EXTEND which will be lowered as SIGN_EXTEND if it ends up sticking around.

llvm-svn: 321746
2018-01-03 18:11:01 +00:00
Dmitry Venikov 3d8cd34a5d [InstSimplify] Missed optimization in math expression: squashing exp(log), log(exp)
Summary: This patch enables folding following expressions under -ffast-math flag: exp(log(x)) -> x, exp2(log2(x)) -> x, log(exp(x)) -> x, log2(exp2(x)) -> x

Reviewers: spatel, hfinkel, davide

Reviewed By: spatel, hfinkel, davide

Subscribers: scanon, llvm-commits

Differential Revision: https://reviews.llvm.org/D41381

llvm-svn: 321710
2018-01-03 14:37:42 +00:00
Florian Hahn dcc0ba9bbb [InstCombine] Add test to remove VarArg casts (NFC)
llvm-svn: 321706
2018-01-03 13:35:43 +00:00
Amara Emerson 9de62130fd [GlobalISel][Legalizer] Fix legalization of llvm.smul.with.overflow
Previously the code for handling G_SMULO didn't properly check for the signed
multiply overflow, instead treating it the same as the unsigned G_UMULO.

Fixes PR35800.

llvm-svn: 321690
2018-01-03 04:56:56 +00:00
Jake Ehrlich 30d927a128 [llvm-objcopy] Add support for visibility
I have no clue how this was missed when symbol table support was added. This
change ensures that the visibility of symbols is preserved by default.

llvm-svn: 321681
2018-01-02 23:01:24 +00:00
Andrew Kaylor e12e08c680 Handle the case of live 16-bit subregisters in X86FixupBWInsts
Differential Revision: https://reviews.llvm.org/D40524

Change-Id: Ie3a405b28503ceae999f5f3ba07a68fa733a2400
llvm-svn: 321674
2018-01-02 21:04:38 +00:00
Sanjay Patel 24e6a8bde0 [AArch64] fix typos in comments; NFC
llvm-svn: 321673
2018-01-02 21:04:08 +00:00
Sanjay Patel 7811430588 [ValueTracking] recognize min/max of min/max patterns
This is part of solving PR35717:
https://bugs.llvm.org/show_bug.cgi?id=35717

The larger IR optimization is proposed in D41603, but we can show 
the improvement in ValueTracking using codegen tests because 
SelectionDAG creates min/max nodes based on ValueTracking. 

Any target with min/max ops should show wins here. I chose AArch64
vector ops because they're clean and uniform.

Some Alive proofs for the tests (can't put more than 2 tests in 1 
page currently because the web app says it's too long):
https://rise4fun.com/Alive/WRN
https://rise4fun.com/Alive/iPm
https://rise4fun.com/Alive/HmY
https://rise4fun.com/Alive/CNm
https://rise4fun.com/Alive/LYf

llvm-svn: 321672
2018-01-02 20:56:45 +00:00
Sanjay Patel 35a6ee86af [AArch64] add tests for min/max of min/max (PR35717); NFC
llvm-svn: 321668
2018-01-02 20:16:45 +00:00
Amara Emerson 913918cbef [AArch64][GlobalISel] Fix assert fail with unknown intrinsic.
A call may have an intrinsic name but not have a valid intrinsic ID,
for example with llvm.invariant.group.barrier. If so, treat it as a
normal call like FastISel does.

llvm-svn: 321662
2018-01-02 18:56:39 +00:00
Sanjay Patel 9a80871ffe [x86] allow pairs of PCMPEQ for vector-sized integer equality comparisons (PR33325)
This is an extension of D31156 with the goal that we'll allow memcmp() == 0 expansion 
for x86 to use 2 pairs of loads per block.

The memcmp expansion pass (formerly part of CGP) will generate this kind of pattern 
with oversized integer compares, so we want to transform these into x86-specific vector
nodes before legalization splits things into scalar chunks.

See PR33325 for more details:
https://bugs.llvm.org/show_bug.cgi?id=33325

Differential Revision: https://reviews.llvm.org/D41618

llvm-svn: 321656
2018-01-02 16:38:29 +00:00
Amara Emerson 854d10d10b [AArch64][GlobalISel] Enable GlobalISel at -O0 by default
Tests updated to explicitly use fast-isel at -O0 instead of implicitly.

This change also allows an explicit -fast-isel option to override an
implicitly enabled global-isel. Otherwise -fast-isel would have no effect at -O0.

Differential Revision: https://reviews.llvm.org/D41362

llvm-svn: 321655
2018-01-02 16:30:47 +00:00
Anna Thomas bdb9430917 [BasicBlockUtils] Check for unreachable preds before updating LI in UpdateAnalysisInformation
Summary:
We are incorrectly updating the LI when loop-simplify generates
dedicated exit blocks for a loop. The issue is that there's an implicit
assumption that the Preds passed into UpdateAnalysisInformation are
reachable. However, this is not true and breaks LI by incorrectly
updating the header of a loop.

One such case is when we generate dedicated exits when the exit block is
a landing pad (through SplitLandingPadPredecessors). There maybe other
cases as well, since we do not guarantee that Preds passed in are
reachable basic blocks.

The added test case shows how loop-simplify breaks LI for the outer loop (and DT in turn)
after we try to generate the LoopSimplifyForm.

Reviewers: davide, chandlerc, sanjoy

Reviewed By: davide

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41519

llvm-svn: 321653
2018-01-02 16:25:50 +00:00
Krzysztof Parzyszek cfe4a3616f [Hexagon] Fix generation of vector sign extensions
llvm-svn: 321650
2018-01-02 15:28:49 +00:00
Daniel Jasper cc4903e2ba Revert r321089: "[DAG] Elide overlapping store" (and subsequent fix in r321204)
Our internal testing has revealed has discovered bugs in PPC builds.
I have forward reproduction instructions to the original author (Nirav).

llvm-svn: 321649
2018-01-02 14:38:52 +00:00
Sam Parker 3570c554b5 [DAGCombine] Fix for PR35765
Remove the acceptance of ANY_EXTEND nodes while trying to move and
nodes back to loads.

Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=35765

Differential Revision: https://reviews.llvm.org/D41625

llvm-svn: 321641
2018-01-02 10:19:01 +00:00
Sam Parker 2dea5e0f3c [X86] Codegen test for pr35765
Committing reproducer test for pr35765, fix to follow.

llvm-svn: 321640
2018-01-02 10:14:00 +00:00
Craig Topper e3b6bd337a [SelectionDAG] Teach WidenVecOp_Convert to widen the operation if a widened result type would still be legal.
llvm-svn: 321638
2018-01-02 07:30:53 +00:00
Dmitry Venikov a58d8deb3a [InstCombine] Missed optimization in math expression: squashing sqrt functions
Summary: This patch enables folding under -ffast-math flag sqrt(a) * sqrt(b) -> sqrt(a*b)

Reviewers: hfinkel, spatel, davide

Reviewed By: spatel, davide

Subscribers: davide, llvm-commits

Differential Revision: https://reviews.llvm.org/D41322

llvm-svn: 321637
2018-01-02 05:58:11 +00:00
Simon Pilgrim 6720726d27 [ValueTracking] Don't assume shift values are in range
Reduced (as best I could...) from oss-fuzz #4857 test case

llvm-svn: 321634
2018-01-01 22:44:59 +00:00
Simon Pilgrim af35f5ec1d [InstCombine] Regenerate udiv tests.
llvm-svn: 321633
2018-01-01 22:27:49 +00:00
Craig Topper c8898b3640 [X86] Promote vXi1 fp_to_uint/fp_to_sint to vXi32 to avoid scalarization.
llvm-svn: 321632
2018-01-01 21:12:18 +00:00
Craig Topper bb8b79b0a0 [X86] Add test cases for vXi1 fptosi/fptoui.
Currently we do a lot of scalarization in these test cases.

llvm-svn: 321631
2018-01-01 21:12:10 +00:00
Sanjay Patel 18962dabb7 [x86] add runs for more vector variants; NFC
Preliminary step to see what the effects of D41618 look like.

llvm-svn: 321624
2018-01-01 16:36:47 +00:00
Simon Pilgrim e337268df7 [X86][SSE] Add test case from PR32160
llvm-svn: 321620
2018-01-01 13:04:04 +00:00
Uriel Korach c06596ced4 [X86] Regenerate test checks in sse-intrinsics-x86-upgrade with update-llc
Removing outdated checks.
NFC

llvm-svn: 321619
2018-01-01 09:00:13 +00:00
Uriel Korach e87d240699 [X86] Regenerate test checks in sse2-intrinsics-x86-upgrade with update-llc
Removing outdated checks.
NFC

llvm-svn: 321618
2018-01-01 08:47:50 +00:00
Craig Topper 0d35edda90 [X86] In LowerTruncateVecI1, don't add SHL if the input is known to be all sign bits.
If the input is all sign bits then the LSB through MSB are all the same so we don't need to be move the LSB to the MSB.

llvm-svn: 321617
2018-01-01 04:52:58 +00:00
Craig Topper fc3ce4993c [X86] Add patterns for using zmm registers for v8i32/v8f32 vselect with the false input being zero.
We can use zmm move with zero masking for this. We already had patterns for using a masked move, but we didn't check for the zero masking case separately.

llvm-svn: 321612
2018-01-01 01:11:29 +00:00
Craig Topper f78b75fb59 [X86] Use CONCAT_VECTORS instead of INSERT_SUBVECTOR for padding v4i1/v2i1 vector to v8i1 pre-legalize.
The CONCAT_VECTORS will be lowered to INSERT_SUBVECTOR later. In the modified cases this seems to be enough to trick a later DAG combine into running in a different order than allows the ANDs to be removed.

I'll admit this is a bit of a hack that happens to work, but using CONCAT_VECTORS is more consistent with other legalization code anyway.

llvm-svn: 321611
2017-12-31 19:17:52 +00:00
Simon Pilgrim b000675374 [X86][AVX2] Combine extract(broadcast(scalar_value)) --> scalar_value
As it has a scalar source we don't treat it as a target shuffle so needs special handling.

llvm-svn: 321610
2017-12-31 18:59:30 +00:00
Simon Pilgrim e940b86c5f [X86][AVX] Add test case from PR33740
llvm-svn: 321608
2017-12-31 17:16:48 +00:00
Simon Pilgrim f205ec716b [X86][SSE] Don't vectorize splat buildvector of binops (PR30780)
Don't combine buildvector(binop(),binop(),binop(),binop()) -> binop(buildvector(), buildvector()) if its a splat - keep the binop scalar and just splat the result to avoid large vector constants.

llvm-svn: 321607
2017-12-31 17:07:47 +00:00
Davide Italiano 9f074fe915 [SimplifyCFG] Stop hoisting musttail calls incorrectly.
PR35774.

llvm-svn: 321603
2017-12-31 16:47:16 +00:00
Craig Topper f0f6eefb49 [X86] Add a DAG combine to widen (i4 (bitcast (v4i1))) before type legalization sees the i4 and changes to load/store.
Same for v2i1 and i2.

llvm-svn: 321602
2017-12-31 09:50:38 +00:00
Craig Topper 7f39623533 [X86] Add a DAG combine to fix (v4i1 (bitcast (i4))) before type legalization sees the i4 and changes to load/store.
Same for i2 and v2i1.

llvm-svn: 321601
2017-12-31 08:25:50 +00:00
George Rimar 7672eb84af [MC] - Stop ignoring invalid meta data symbols.
Previously llvm-mc would silently accept code from testcase,
that contains invalid metadata symbol in section declaration.

Patch fixes the issue.

Differential revision: https://reviews.llvm.org/D41641

llvm-svn: 321599
2017-12-31 07:41:02 +00:00
Craig Topper 876ec0b558 [X86] Prevent combining (v8i1 (bitconvert (i8 load)))->(v8i1 load) if we don't have DQI.
We end up using an i8 load via an isel pattern from v8i1 anyway. This just makes it more explicit. This seems to improve codgen in some cases and I'd like to kill off some of the load patterns.

llvm-svn: 321598
2017-12-31 07:38:41 +00:00
Craig Topper a362dee774 [X86] Remove AND32ri8 from pattern for v1i1 load.
I don't think anything would actually expect the other bits to be zero.

llvm-svn: 321596
2017-12-31 07:38:33 +00:00
Craig Topper 7ba1b76854 [X86] Fix a crash when returning a <1 x i1> value>
llvm-svn: 321595
2017-12-31 07:38:30 +00:00
Philip Reames 232951dfb2 2nd attempt at "fixing" amdgpu tests after r321575​
The test needs to be changed; it was exercising UB and that likely wasn't the intent of the test author.  I simply removed the checks because I have absolutely no idea what this test was trying to accomplish.  With multiple check patterns, no explanation, and no familiarity on my part with the ISA a true fix is going to have to come from someone familiar with the target.  

llvm-svn: 321591
2017-12-31 03:34:36 +00:00
Philip Reames 3580c90458 Test fix after r321575
The test in question was checking for a particular intepretation of undefined behavior.  Relax the test to check that we simply don't crash.

Sorry for the breakage, I don't generally build AMDGPU locally and just saw the failure this morning.  

llvm-svn: 321589
2017-12-30 18:42:37 +00:00
Simon Pilgrim 06f6d262f9 [X86][SSE] Add PR30780 test cases
Broadcast of sign/zero extended scalars resulting in unnecessary vector constants

llvm-svn: 321584
2017-12-30 11:51:45 +00:00
Simon Pilgrim fa0f793c8d [X86][SSE] Add test for (v2f32 uitofp(build_vector(i32, i32))) (PR35732)
To compare against (v2f32 build_vector(f32 uitofp(i32), f32 uitofp(i32)))

llvm-svn: 321583
2017-12-30 11:20:56 +00:00
Hiroshi Inoue ca3cdd7f27 [PowerPC] fix a bug in TCO eligibility check
If the callee and caller use different calling convensions, we cannot apply TCO if the callee requires arguments on stack; e.g. C calling convention and Fast CC use the same registers for parameter passing, but the stack offset is not necessarily same.

This patch also recommit r319218 "[PowerPC] Allow tail calls of fastcc functions from C CallingConv functions." by @sfertile since the problem reported in r320106 should be fixed.

Differential Revision: https://reviews.llvm.org/D40893

llvm-svn: 321579
2017-12-30 08:09:04 +00:00
Craig Topper c5fd31a802 [X86] Custom legalize vXi1 extract_subvector with KSHIFTR.
This allows us to remove some isel patterns.

This is mostly NFC, but we now use KSHIFTB instead of KSHIFTW with DQI.

llvm-svn: 321576
2017-12-30 06:45:43 +00:00
Philip Reames e499bc3042 [instsimplify] consistently handle undef and out of bound indices for insertelement and extractelement
In one case, we were handling out of bounds, but not undef indices.  In the other, we were handling undef (with the comment making the analogy to out of bounds), but not out of bounds.  Be consistent and treat both undef and constant out of bounds indices as producing undefined results.

As a side effect, this also protects instcombine from having to handle large constant indices as we always simplify first.

llvm-svn: 321575
2017-12-30 05:54:22 +00:00
Philip Reames 8e1abe4a7d Add another test case for r321489
Went to reduce another fuzzer failure to find it's already been fixed, but the test case is slightly different so it's worth adding anyways.

Reduced from oss-fuzz #4768 test case

llvm-svn: 321573
2017-12-30 04:10:48 +00:00
Philip Reames 3e9c671923 Move tests associated with transforms moved in r321467
llvm-svn: 321572
2017-12-30 03:13:00 +00:00