3 Commits

Author	SHA1	Message	Date
Matt Arsenault	ea03cf2fa1	AMDGPU: Don't reserve SCRATCH_PTR input register ... This hasn't been doing anything since using relocations was added. llvm-svn: 254304	2015-11-30 15:46:47 +00:00
Matt Arsenault	e8c0891e42	AMDGPU: Fix verifier error in SIFoldOperands ... There may be other use operands that also need their kill flags cleared. This happens in a few tests when SIFoldOperands is moved after PeepholeOptimizer. PeepholeOptimizer rewrites cases that look like: %vreg0 = ... %vreg1 = COPY %vreg0 use %vreg1<kill> %vreg2 = COPY %vreg0 use %vreg2<kill> to use the earlier source to %vreg0 = ... use %vreg0 use %vreg0 Currently SIFoldOperands sees the copied registers, so there is only one use. So far I haven't managed to come up with a test that currently has multiple uses of a foldable VGPR -> VGPR copy. llvm-svn: 250960	2015-10-21 22:37:50 +00:00
Alex Lorenz	b4d0d6a345	AMDGPU/SI: Add implicit register operands in the correct order. ... This commit fixes a bug in the class 'SIInstrInfo' where the implicit register machine operands were added to a machine instruction in an incorrect order - the implicit uses were added before the implicit defs. I found this bug while working on moving the implicit register operand verification code from the MIR parser to the machine verifier. This commit also makes the method 'addImplicitDefUseOperands' in the machine instruction class public so that it can be reused in the 'SIInstrInfo' class. Reviewers: Matt Arsenault Differential Revision: http://reviews.llvm.org/D11689 llvm-svn: 243799	2015-07-31 23:30:09 +00:00