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Author SHA1 Message Date
Jim Grosbach 1b0f79573e Tidy up. 
llvm-svn: 137339
 2011-08-11 20:13:35 +00:00
Jim Grosbach 2a50260f2f ARM STRBT assembly parsing and encoding. 
llvm-svn: 137337
 2011-08-11 20:04:56 +00:00
Jim Grosbach d564bf3181 ARM STR(immediate) assembly parsing and encoding. 
llvm-svn: 137331
 2011-08-11 19:22:40 +00:00
Owen Anderson 3477f2cea5 Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases. 
llvm-svn: 137325
 2011-08-11 19:00:18 +00:00
Bruno Cardoso Lopes 043c820800 Fix PR10492 by teaching MOVHLPS and MOVLPS mask matching to be more strict. 
llvm-svn: 137324
 2011-08-11 18:59:13 +00:00
Owen Anderson 0e15b48f3c Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. 
llvm-svn: 137323
 2011-08-11 18:55:42 +00:00
Owen Anderson e33c95d39b Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me. 
llvm-svn: 137322
 2011-08-11 18:41:59 +00:00
Benjamin Kramer fa7e6a54b1 Plug a memory leak. 
llvm-svn: 137321
 2011-08-11 18:39:28 +00:00
Owen Anderson ed25385227 Improve error checking in the new ARM disassembler. Patch by James Molloy. 
llvm-svn: 137320
 2011-08-11 18:24:51 +00:00
Jim Grosbach 27ad83d8a9 ARM push of a single register encodes as pre-indexed STR. 
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

llvm-svn: 137318
 2011-08-11 18:07:11 +00:00
Andrew Trick 266ab10012 Cleanup. Another thorough review by Nick! 
llvm-svn: 137317
 2011-08-11 17:54:58 +00:00
Jim Grosbach 8ba76c6d5c ARM pop of a single register encodes as post-indexed LDR. 
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.

llvm-svn: 137316
 2011-08-11 17:35:48 +00:00
Nadav Rotem efdd183f52 Add a comment, per Bruno's CR. 
llvm-svn: 137313
 2011-08-11 17:05:47 +00:00
Nadav Rotem 61140e1028 [AVX] When joining two XMM registers into a YMM register, make sure that the 
lower XMM register gets in first. This will allow the SUBREG pattern to
elliminate the first vector insertion. 

llvm-svn: 137310
 2011-08-11 16:49:36 +00:00
Nadav Rotem 1542d5a00a [AVX] If the data which is going to be saved is already in two XMM registers 
(for example, after integer operation), do not pack the registers into a YMM
before saving. Its better to save as two XMM registers.

Before:
                vinsertf128         $1, %xmm3, %ymm0, %ymm3
                vinsertf128         $0, %xmm1, %ymm3, %ymm1
                vmovaps              %ymm1, 416(%rsp)

After:
                vmovaps              %xmm3, 416+16(%rsp)
                vmovaps              %xmm1, 416(%rsp)

llvm-svn: 137308
 2011-08-11 16:41:21 +00:00
Chris Lattner 96710b4308 fix PR10605 / rdar://9930964 by adding a pretty scary missed check. 
It's somewhat surprising anything works without this.  Before we would
compile the testcase into:

test:                                   # @test
	movl	$4, 8(%rdi)
	movl	8(%rdi), %eax
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2

now we produce:

test:                                   # @test
	movl	8(%rdi), %eax
	movl	$4, 8(%rdi)
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2
llvm-svn: 137303
 2011-08-11 06:26:54 +00:00
Bruno Cardoso Lopes dbd1352c80 Cleanup: Remove Int_ CVTSS2SI* forms 
llvm-svn: 137297
 2011-08-11 02:52:36 +00:00
Bruno Cardoso Lopes a2d8bb97b9 Splats for v8i32/v8f32 can be handled by VPERMILPSY. This was causing 
infinite recursive calls in legalize. Fix PR10562

llvm-svn: 137296
 2011-08-11 02:49:44 +00:00
Bruno Cardoso Lopes 572c9aaf53 Use the splat index to generate the desired shuffle. Otherwise we 
could only get undefs and the vector shuffle becomes an undef,
generating wrong code.

llvm-svn: 137295
 2011-08-11 02:49:41 +00:00
Eli Friedman 3ae39f8ad1 Fix X86TargetLowering::LowerExternalSymbol so that it actually works in non-trivial cases. This hasn't been an issue before because the function isn't normally called (but apparently is used to generate a tail-call to sin() on ELF x86-32 with PIC and SSE2). 
Fixes PR9693.

llvm-svn: 137292
 2011-08-11 01:48:05 +00:00
Devang Patel 784077eb57 Stay within 80 columns. 
llvm-svn: 137283
 2011-08-10 23:58:09 +00:00
Jim Grosbach d5d6359785 ARM LDRT assembly parsing and encoding. 
llvm-svn: 137282
 2011-08-10 23:43:54 +00:00
Jim Grosbach d3f7bcd43c Tidy up. 80 columns. 
llvm-svn: 137277
 2011-08-10 23:23:47 +00:00
Andrew Trick d3530b9117 Reapplying r136844. 
An algorithm for incrementally updating LoopInfo within a
LoopPassManager. The incremental update should be extremely cheap in
most cases and can be used in places where it's not feasible to
regenerate the entire loop forest.

- "Unloop" is a node in the loop tree whose last backedge has been removed.
- Perform reverse dataflow on the block inside Unloop to propagate the
  nearest loop from the block's successors.
- For reducible CFG, each block in unloop is visited exactly
  once. This is because unloop no longer has a backedge and blocks
  within subloops don't change parents.
- Immediate subloops are summarized by the nearest loop reachable from
  their exits or exits within nested subloops.
- At completion the unloop blocks each have a new parent loop, and
  each immediate subloop has a new parent.

llvm-svn: 137276
 2011-08-10 23:22:57 +00:00
Jim Grosbach cd4dd255c0 ARM LDRH(immediate) assembly parsing and encoding support. 
llvm-svn: 137260
 2011-08-10 22:42:16 +00:00
Jim Grosbach 1d9d5e93d1 ARM LDRD(register) assembly parsing and encoding. 
Add support for literal encoding of #-0 along the way.

llvm-svn: 137254
 2011-08-10 21:56:18 +00:00
Devang Patel bb23a4a9a5 Distinguish between two copies of one inlined variable. Take 2. 
llvm-svn: 137253
 2011-08-10 21:50:54 +00:00
Devang Patel 37a62058fe While extending definition range of a debug variable, consult lexical scopes also. There is no point extending debug variable out side its lexical block. This provides 6x compile time speedup in some cases. 
llvm-svn: 137250
 2011-08-10 21:25:34 +00:00
Devang Patel e30746c844 Revert unintentional parts of previous check-in. 
llvm-svn: 137249
 2011-08-10 21:16:49 +00:00
Devang Patel 7e62302fae Start using LexicalScopes utility. No intetional functionality change. 
llvm-svn: 137246
 2011-08-10 20:55:27 +00:00
Jim Grosbach f7164b2cfd Fix typo. Not quite sure how that slipped in there. 
llvm-svn: 137245
 2011-08-10 20:49:18 +00:00
Jim Grosbach 5b96b80644 ARM LDRD(immediate) assembly parsing and encoding support. 
llvm-svn: 137244
 2011-08-10 20:29:19 +00:00
Nadav Rotem 410a11fe82 When performing a truncating store, it is sometimes possible to rearrange the 
data in-register prior to saving to memory.  When we reorder the data in memory
we prevent the need to save multiple scalars to memory, making a single regular
store.

llvm-svn: 137238
 2011-08-10 19:30:14 +00:00
Devang Patel e1649c31cb Provide utility to extract and use lexical scoping information from machine instructions. 
llvm-svn: 137237
 2011-08-10 19:04:06 +00:00
Owen Anderson c86a5bd219 Add initial support for decoding NEON instructions in Thumb2 mode. 
llvm-svn: 137236
 2011-08-10 19:01:10 +00:00
Andrew Trick 6dbb060778 Comments. Thanks for the spell check Nick! 
Also, my apologies for spoiling the autocomplete on SimplifyInstructions.cpp. I couldn't think of a better filename.

llvm-svn: 137229
 2011-08-10 18:07:05 +00:00
Bruno Cardoso Lopes 3ff111c12d The following X86 pattern is incorrect: 
def : Pat<(X86Movss VR128:$src1,
                   (bc_v4i32 (v2i64 (load addr:$src2)))),
          (MOVLPSrm VR128:$src1, addr:$src2)>;
This matches a MOVSS dag with a MOVLPS instruction. However, MOVSS will replace only the low 32 bits of the register, while the MOVLPS instruction will replace the low 64 bits. A testcase is added and illustrates the bug and also modified the one that was already present. Patch by Tanya Lattner.

llvm-svn: 137227
 2011-08-10 17:45:17 +00:00
Eli Friedman cad9f2af44 Whitespace. 
llvm-svn: 137226
 2011-08-10 17:39:11 +00:00
Owen Anderson 1531e5cd2b Tabs --> spaces. 
llvm-svn: 137225
 2011-08-10 17:38:05 +00:00
Owen Anderson 5d69f63bbb Cleanups based on Nick Lewycky's feedback. 
llvm-svn: 137224
 2011-08-10 17:36:48 +00:00
Owen Anderson 732f82c463 Rewrite some ARM InstrInfo functions to be most accepting of arbitrary register subclasses. Hopefully this fixes some buildbots. 
llvm-svn: 137223
 2011-08-10 17:21:20 +00:00
Rafael Espindola 36a3abc671 Add support for the R and Q constraints. 
llvm-svn: 137217
 2011-08-10 16:26:42 +00:00
Bob Wilson 527bd07934 Clarify a comment. 
llvm-svn: 137204
 2011-08-10 05:02:22 +00:00
Andrew Trick 4d0040baf8 Invoke SimplifyIndVar when we partially unroll a loop. Fixes PR10534. 
llvm-svn: 137203
 2011-08-10 04:29:49 +00:00
Andrew Trick e629d008fb Cleanup. Make ScalarEvolution an explicit argument of the 
SimplifyIndVar utility since it is required.

llvm-svn: 137202
 2011-08-10 04:22:26 +00:00
Andrew Trick 74664d5ec6 SimplifyIndVar: make foldIVUser iterative to fold a chain of operands. 
llvm-svn: 137199
 2011-08-10 04:01:31 +00:00
Benjamin Kramer 0b0e47d6ad Update CMake build. 
llvm-svn: 137198
 2011-08-10 03:51:58 +00:00
Andrew Trick 3ec331eaf4 Added a SimplifyIndVar utility to simplify induction variable users 
based on ScalarEvolution without changing the induction variable phis.

This utility is the main tool of IndVarSimplifyPass, but the pass also
restructures induction variables in strange ways that are sensitive to
pass ordering. This provides a way for other loop passes to simplify
new uses of induction variables created during transformation. The
utility may be used by any pass that preserves ScalarEvolution. Soon
LoopUnroll will use it.

The net effect in this checkin is to cleanup the IndVarSimplify pass
by factoring out the SimplifyIndVar algorithm into a standalone utility.

llvm-svn: 137197
 2011-08-10 03:46:27 +00:00
Andrew Trick 78b40c3f3a Cleanup. Added LoopBlocksDFS::perform for simple clients. 
llvm-svn: 137195
 2011-08-10 01:59:05 +00:00
Bruno Cardoso Lopes 278ffd7d8e Fix a bug in vpermilps mask checking. Fix PR10560 
llvm-svn: 137194
 2011-08-10 01:54:17 +00:00