Commit Graph

74715 Commits

Author SHA1 Message Date
Jim Grosbach 1b0f79573e Tidy up.
llvm-svn: 137339
2011-08-11 20:13:35 +00:00
Jim Grosbach 2a50260f2f ARM STRBT assembly parsing and encoding.
llvm-svn: 137337
2011-08-11 20:04:56 +00:00
Jim Grosbach d0767f37c1 Add FIXME.
llvm-svn: 137336
2011-08-11 19:43:42 +00:00
Jim Grosbach 295788756d ARM STRB assembly parsing and encoding tests.
llvm-svn: 137335
2011-08-11 19:42:58 +00:00
Jim Grosbach 14a4164206 Fix a copy/paste error so that LDRB(register) actually gets tested.
llvm-svn: 137333
2011-08-11 19:34:23 +00:00
Jim Grosbach 06b7f0c901 ARM STR(register) assembly parsing and encoding tests.
llvm-svn: 137332
2011-08-11 19:26:17 +00:00
Jim Grosbach d564bf3181 ARM STR(immediate) assembly parsing and encoding.
llvm-svn: 137331
2011-08-11 19:22:40 +00:00
Owen Anderson 3477f2cea5 Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
llvm-svn: 137325
2011-08-11 19:00:18 +00:00
Bruno Cardoso Lopes 043c820800 Fix PR10492 by teaching MOVHLPS and MOVLPS mask matching to be more strict.
llvm-svn: 137324
2011-08-11 18:59:13 +00:00
Owen Anderson 0e15b48f3c Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
llvm-svn: 137323
2011-08-11 18:55:42 +00:00
Owen Anderson e33c95d39b Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
llvm-svn: 137322
2011-08-11 18:41:59 +00:00
Benjamin Kramer fa7e6a54b1 Plug a memory leak.
llvm-svn: 137321
2011-08-11 18:39:28 +00:00
Owen Anderson ed25385227 Improve error checking in the new ARM disassembler. Patch by James Molloy.
llvm-svn: 137320
2011-08-11 18:24:51 +00:00
Jim Grosbach 27ad83d8a9 ARM push of a single register encodes as pre-indexed STR.
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

llvm-svn: 137318
2011-08-11 18:07:11 +00:00
Andrew Trick 266ab10012 Cleanup. Another thorough review by Nick!
llvm-svn: 137317
2011-08-11 17:54:58 +00:00
Jim Grosbach 8ba76c6d5c ARM pop of a single register encodes as post-indexed LDR.
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.

llvm-svn: 137316
2011-08-11 17:35:48 +00:00
Justin Holewinski 6c6a7fd692 PTX: Add basic documentation to CodeGenerator.html
llvm-svn: 137315
2011-08-11 17:34:16 +00:00
Nadav Rotem efdd183f52 Add a comment, per Bruno's CR.
llvm-svn: 137313
2011-08-11 17:05:47 +00:00
Nadav Rotem 61140e1028 [AVX] When joining two XMM registers into a YMM register, make sure that the
lower XMM register gets in first. This will allow the SUBREG pattern to
elliminate the first vector insertion. 

llvm-svn: 137310
2011-08-11 16:49:36 +00:00
Nadav Rotem 1542d5a00a [AVX] If the data which is going to be saved is already in two XMM registers
(for example, after integer operation), do not pack the registers into a YMM
before saving. Its better to save as two XMM registers.

Before:
                vinsertf128         $1, %xmm3, %ymm0, %ymm3
                vinsertf128         $0, %xmm1, %ymm3, %ymm1
                vmovaps              %ymm1, 416(%rsp)

After:
                vmovaps              %xmm3, 416+16(%rsp)
                vmovaps              %xmm1, 416(%rsp)

llvm-svn: 137308
2011-08-11 16:41:21 +00:00
Chris Lattner 5a2c70cc8f add missing colon, thanks peter.
llvm-svn: 137306
2011-08-11 16:15:10 +00:00
Chris Lattner 96710b4308 fix PR10605 / rdar://9930964 by adding a pretty scary missed check.
It's somewhat surprising anything works without this.  Before we would
compile the testcase into:

test:                                   # @test
	movl	$4, 8(%rdi)
	movl	8(%rdi), %eax
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2

now we produce:

test:                                   # @test
	movl	8(%rdi), %eax
	movl	$4, 8(%rdi)
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2
llvm-svn: 137303
2011-08-11 06:26:54 +00:00
Bruno Cardoso Lopes dbd1352c80 Cleanup: Remove Int_ CVTSS2SI* forms
llvm-svn: 137297
2011-08-11 02:52:36 +00:00
Bruno Cardoso Lopes a2d8bb97b9 Splats for v8i32/v8f32 can be handled by VPERMILPSY. This was causing
infinite recursive calls in legalize. Fix PR10562

llvm-svn: 137296
2011-08-11 02:49:44 +00:00
Bruno Cardoso Lopes 572c9aaf53 Use the splat index to generate the desired shuffle. Otherwise we
could only get undefs and the vector shuffle becomes an undef,
generating wrong code.

llvm-svn: 137295
2011-08-11 02:49:41 +00:00
Eli Friedman 3ae39f8ad1 Fix X86TargetLowering::LowerExternalSymbol so that it actually works in non-trivial cases. This hasn't been an issue before because the function isn't normally called (but apparently is used to generate a tail-call to sin() on ELF x86-32 with PIC and SSE2).
Fixes PR9693.

llvm-svn: 137292
2011-08-11 01:48:05 +00:00
Chad Rosier 9019fd3813 Typo.
llvm-svn: 137286
2011-08-11 00:22:48 +00:00
Devang Patel 784077eb57 Stay within 80 columns.
llvm-svn: 137283
2011-08-10 23:58:09 +00:00
Jim Grosbach d5d6359785 ARM LDRT assembly parsing and encoding.
llvm-svn: 137282
2011-08-10 23:43:54 +00:00
Jim Grosbach d3f7bcd43c Tidy up. 80 columns.
llvm-svn: 137277
2011-08-10 23:23:47 +00:00
Andrew Trick d3530b9117 Reapplying r136844.
An algorithm for incrementally updating LoopInfo within a
LoopPassManager. The incremental update should be extremely cheap in
most cases and can be used in places where it's not feasible to
regenerate the entire loop forest.

- "Unloop" is a node in the loop tree whose last backedge has been removed.
- Perform reverse dataflow on the block inside Unloop to propagate the
  nearest loop from the block's successors.
- For reducible CFG, each block in unloop is visited exactly
  once. This is because unloop no longer has a backedge and blocks
  within subloops don't change parents.
- Immediate subloops are summarized by the nearest loop reachable from
  their exits or exits within nested subloops.
- At completion the unloop blocks each have a new parent loop, and
  each immediate subloop has a new parent.

llvm-svn: 137276
2011-08-10 23:22:57 +00:00
Jim Grosbach 94ba2cba6e ARM tests for LDRSHT assembly parsing and encoding.
llvm-svn: 137274
2011-08-10 23:18:30 +00:00
Jim Grosbach a6ab52bf9f ARM tests for LDRSH assembly parsing and encoding.
llvm-svn: 137272
2011-08-10 23:12:25 +00:00
Jim Grosbach 2953404723 ARM tests for LDRSBT assembly parsing and encoding.
llvm-svn: 137271
2011-08-10 23:08:56 +00:00
Jim Grosbach c11bbf3bda ARM tests for LDRSB assembly parsing and encoding.
llvm-svn: 137270
2011-08-10 23:06:44 +00:00
Jim Grosbach 35cdf36c32 Add FIXME.
llvm-svn: 137265
2011-08-10 22:56:43 +00:00
Andrew Trick 57544c8d9b Cleanup. Remove an extraneous GraphTraits specialization.
llvm-svn: 137264
2011-08-10 22:55:39 +00:00
Jim Grosbach 5e0c9711f2 ARM tests for LDRHT assembly parsing and encoding.
llvm-svn: 137263
2011-08-10 22:55:38 +00:00
NAKAMURA Takumi 504769fc2f test/CodeGen/X86/opt-shuff-tstore.ll: Add explicit -mtriple=x86_64-linux.
llvm-svn: 137262
2011-08-10 22:52:48 +00:00
Jim Grosbach 7cd4253cc3 ARM tests for LDRH(register) assembly parsing and encoding.
llvm-svn: 137261
2011-08-10 22:45:42 +00:00
Jim Grosbach cd4dd255c0 ARM LDRH(immediate) assembly parsing and encoding support.
llvm-svn: 137260
2011-08-10 22:42:16 +00:00
Jim Grosbach ae1b002fa3 Add FIXME
llvm-svn: 137258
2011-08-10 22:20:38 +00:00
Jim Grosbach 1d9d5e93d1 ARM LDRD(register) assembly parsing and encoding.
Add support for literal encoding of #-0 along the way.

llvm-svn: 137254
2011-08-10 21:56:18 +00:00
Devang Patel bb23a4a9a5 Distinguish between two copies of one inlined variable. Take 2.
llvm-svn: 137253
2011-08-10 21:50:54 +00:00
Devang Patel 37a62058fe While extending definition range of a debug variable, consult lexical scopes also. There is no point extending debug variable out side its lexical block. This provides 6x compile time speedup in some cases.
llvm-svn: 137250
2011-08-10 21:25:34 +00:00
Devang Patel e30746c844 Revert unintentional parts of previous check-in.
llvm-svn: 137249
2011-08-10 21:16:49 +00:00
Devang Patel 7e62302fae Start using LexicalScopes utility. No intetional functionality change.
llvm-svn: 137246
2011-08-10 20:55:27 +00:00
Jim Grosbach f7164b2cfd Fix typo. Not quite sure how that slipped in there.
llvm-svn: 137245
2011-08-10 20:49:18 +00:00
Jim Grosbach 5b96b80644 ARM LDRD(immediate) assembly parsing and encoding support.
llvm-svn: 137244
2011-08-10 20:29:19 +00:00
Eli Friedman 224fe0d4cb Changes per Jeffrey's comments.
llvm-svn: 137243
2011-08-10 20:17:43 +00:00