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291 Commits

Author SHA1 Message Date
Chris Lattner 9ad5915559 SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBits 
a chance to hack on it.  This compiles:

int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

instead of:

_baz:
        srwi r2, r4, 24
        rlwimi r2, r3, 8, 0, 23
        srwi r2, r2, 9
        extsh r3, r2
        blr

This implements CodeGen/PowerPC/sign_ext_inreg1.ll

llvm-svn: 36212
 2007-04-17 19:03:21 +00:00
Chris Lattner 18e4ac4107 fix an infinite loop compiling ldecod, notice by JeffC. 
llvm-svn: 35910
 2007-04-11 16:51:53 +00:00
Chris Lattner a083ffcad7 Fix this harder. 
llvm-svn: 35888
 2007-04-11 06:50:51 +00:00
Chris Lattner c5f85d3738 don't create shifts by zero, fix some problems with my previous patch 
llvm-svn: 35887
 2007-04-11 06:43:25 +00:00
Chris Lattner 65786b078c Teach the codegen to turn [aez]ext (setcc) -> selectcc of 1/0, which often 
allows other simplifications.  For example, this compiles:
int isnegative(unsigned int X) {
   return !(X < 2147483648U);
}

Into this code:

x86:
        movl 4(%esp), %eax
        shrl $31, %eax
        ret
arm:
        mov r0, r0, lsr #31
        bx lr
thumb:
        lsr r0, r0, #31
        bx lr

instead of:

x86:
        cmpl $0, 4(%esp)
        sets %al
        movzbl %al, %eax
        ret

arm:
        mov r3, #0
        cmp r0, #0
        movlt r3, #1
        mov r0, r3
        bx lr

thumb:
        mov r2, #1
        mov r1, #0
        cmp r0, #0
        blt LBB1_2      @entry
LBB1_1: @entry
        cpy r2, r1
LBB1_2: @entry
        cpy r0, r2
        bx lr

Testcase here: test/CodeGen/Generic/ispositive.ll

llvm-svn: 35883
 2007-04-11 05:32:27 +00:00
Chris Lattner 41189c63cc Codegen integer abs more efficiently using the trick from the PPC CWG. This 
improves codegen on many architectures.  Tests committed as CodeGen/*/iabs.ll

X86 Old:			X86 New:
_test:				_test:
   movl 4(%esp), %ecx		   movl 4(%esp), %eax
   movl %ecx, %eax		   movl %eax, %ecx
   negl %eax			   sarl $31, %ecx
   testl %ecx, %ecx		   addl %ecx, %eax
   cmovns %ecx, %eax		   xorl %ecx, %eax
   ret				   ret

PPC Old:			PPC New:
_test:				_test:
   cmpwi cr0, r3, -1		   srawi r2, r3, 31
   neg r2, r3			   add r3, r3, r2
   bgt cr0, LBB1_2 ;		   xor r3, r3, r2
LBB1_1: ;			   blr
   mr r3, r2
LBB1_2: ;
   blr

ARM Old:			ARM New:
_test:				_test:
   rsb r3, r0, #0		   add r3, r0, r0, asr #31
   cmp r0, #0			   eor r0, r3, r0, asr #31
   movge r3, r0			   bx lr
   mov r0, r3
   bx lr

Thumb Old:			Thumb New:
_test:				_test:
   neg r2, r0			   asr r2, r0, #31
   cmp r0, #0			   add r0, r0, r2
   bge LBB1_2			   eor r0, r2
LBB1_1: @			   bx lr
   cpy r0, r2
LBB1_2: @
   bx lr


Sparc Old:			Sparc New:
test:				test:
   save -96, %o6, %o6		   save -96, %o6, %o6
   sethi 0, %l0			   sra %i0, 31, %l0
   sub %l0, %i0, %l0		   add %i0, %l0, %l1
   subcc %i0, -1, %l1		   xor %l1, %l0, %i0
   bg .BB1_2			   restore %g0, %g0, %g0
   nop				   retl
.BB1_1:				   nop
   or %g0, %l0, %i0
.BB1_2:
   restore %g0, %g0, %g0
   retl
   nop

It also helps alpha/ia64 :)

llvm-svn: 35881
 2007-04-11 05:11:38 +00:00
Scott Michel 16627a542f 1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL. 
2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.

llvm-svn: 35605
 2007-04-02 21:36:32 +00:00
Dale Johannesen 4bbd2eefba Fix incorrect combination of different loads. Reenable zext-over-truncate 
combination.

llvm-svn: 35517
 2007-03-30 21:38:07 +00:00
Evan Cheng ccee35fd0d Disable load width reduction xform of variant (zext (truncate load x)) for 
big endian targets until llvm-gcc build issue has been resolved.

llvm-svn: 35449
 2007-03-29 07:56:46 +00:00
Evan Cheng 8275f0e0af SIGN_EXTEND_INREG requires one extra operand, a ValueType node. 
llvm-svn: 35350
 2007-03-26 07:12:51 +00:00
Evan Cheng b7051f596a Adjust offset to compensate for big endian machines. 
llvm-svn: 35293
 2007-03-24 00:02:43 +00:00
Evan Cheng a883b58caf Make sure SEXTLOAD of the specific type is supported on the target. 
llvm-svn: 35289
 2007-03-23 22:13:36 +00:00
Evan Cheng e2f5f24e8e Also replace uses of SRL if that's also folded during ReduceLoadWidth(). 
llvm-svn: 35286
 2007-03-23 20:55:21 +00:00
Evan Cheng a824e79f06 A couple of bug fixes for reducing load width xform: 
1. Address offset is in bytes.
2. Make sure truncate node uses are replaced with new load.

llvm-svn: 35274
 2007-03-23 02:16:52 +00:00
Evan Cheng 464dc9b74c More opportunities to reduce load size. 
llvm-svn: 35254
 2007-03-22 01:54:19 +00:00
Evan Cheng d63baead9b fold (truncate (srl (load x), c)) -> (smaller load (x+c/vt bits)) 
llvm-svn: 35239
 2007-03-21 20:14:05 +00:00
Evan Cheng 8a1d09d079 Avoid combining indexed load further. 
llvm-svn: 35005
 2007-03-07 08:07:03 +00:00
Chris Lattner 47206667c0 fold away addc nodes when we know there cannot be a carry-out. 
llvm-svn: 34913
 2007-03-04 20:40:38 +00:00
Chris Lattner 2dcc6e7f58 generalize 
llvm-svn: 34910
 2007-03-04 20:08:45 +00:00
Chris Lattner e2e13caeb2 canonicalize constants to the RHS of addc/adde. If nothing uses the carry out of 
addc, turn it into add.

This allows us to compile:

long long test(long long A, unsigned B) {
  return (A + ((long long)B << 32)) & 123;
}

into:

_test:
        movl $123, %eax
        andl 4(%esp), %eax
        xorl %edx, %edx
        ret

instead of:
_test:
        xorl %edx, %edx
        movl %edx, %eax
        addl 4(%esp), %eax   ;; add of zero
        andl $123, %eax
        ret

llvm-svn: 34909
 2007-03-04 20:03:15 +00:00
Chris Lattner fce448f856 Fold (sext (truncate x)) more aggressively, by avoiding creation of a 
sextinreg if not needed.   This is useful in two cases: before legalize,
it avoids creating a sextinreg that will be trivially removed.  After legalize
if the target doesn't support sextinreg, the trunc/sext would not have been
removed before.

llvm-svn: 34621
 2007-02-26 03:13:59 +00:00
Evan Cheng 92658d5648 Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. 
llvm-svn: 34065
 2007-02-08 22:13:59 +00:00
Evan Cheng 00a640dbe0 Fix for PR1108: type of insert_vector_elt index operand is PtrVT, not MVT::i32. 
llvm-svn: 33398
 2007-01-20 10:10:26 +00:00
Evan Cheng 9201100b29 Remove this xform: 
(shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
Replace it with:
(add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )

This fixes test/CodeGen/ARM/smul.ll

llvm-svn: 33361
 2007-01-19 17:51:44 +00:00
Chris Lattner 4dc4489286 Fix PR1114 and CodeGen/Generic/2007-01-15-LoadSelectCycle.ll by being 
careful when folding "c ? load p : load q" that C doesn't reach either load.
If so, folding this into load (c ? p : q) will induce a cycle in the graph.

llvm-svn: 33251
 2007-01-16 05:59:59 +00:00
Chris Lattner f70c5cd5db add options to view the dags before the first or second pass of dag combine. 
llvm-svn: 33249
 2007-01-16 04:55:25 +00:00
Chris Lattner 0199fd6d59 Implement some trivial FP foldings when -enable-unsafe-fp-math is specified. 
This implements CodeGen/PowerPC/unsafe-math.ll

llvm-svn: 33024
 2007-01-08 23:04:05 +00:00
Chris Lattner aee775a6b7 Eliminate static ctors from Statistics 
llvm-svn: 32698
 2006-12-19 22:41:21 +00:00
Evan Cheng 28cf4277bb Cannot combine an indexed load / store any further. 
llvm-svn: 32629
 2006-12-16 06:25:23 +00:00
Jim Laskey 26df19ace6 This code was usurping the sextload expand in teh legalizer. Just make 
sure the right conditions are checked.

llvm-svn: 32611
 2006-12-15 21:38:30 +00:00
Chris Lattner b7524b6d0e make this code more aggressive about turning store fpimm into store int imm. 
This is not sufficient to fix X86/store-fp-constant.ll

llvm-svn: 32465
 2006-12-12 04:16:14 +00:00
Evan Cheng 218369881f Don't convert store double C, Ptr to store long C, Ptr if i64 is not a legal type. 
llvm-svn: 32434
 2006-12-11 17:25:19 +00:00
Nate Begeman 8e20c760fa Move something that should be in the dag combiner from the legalizer to the 
dag combiner.

llvm-svn: 32431
 2006-12-11 02:23:46 +00:00
Chris Lattner d9f04e4875 Fix CodeGen/PowerPC/2006-12-07-SelectCrash.ll on PPC64 
llvm-svn: 32336
 2006-12-07 22:36:47 +00:00
Bill Wendling 22e978a736 Removing even more <iostream> includes. 
llvm-svn: 32320
 2006-12-07 20:04:42 +00:00
Chris Lattner 700b873130 Detemplatize the Statistic class. The only type it is instantiated with 
is 'unsigned'.

llvm-svn: 32279
 2006-12-06 17:46:33 +00:00
Chris Lattner 3da631f29a For better or worse, load from i1 is assumed to be zero extended. Do not 
form a load from i1 from larger loads that may not be zext'd.

llvm-svn: 31933
 2006-11-27 04:40:53 +00:00
Chris Lattner 3676a994ca Fix PR1011 and CodeGen/Generic/2006-11-20-DAGCombineCrash.ll 
llvm-svn: 31878
 2006-11-20 18:05:46 +00:00
Evan Cheng f64da389f8 Fix an incorrectly inverted condition. 
llvm-svn: 31773
 2006-11-16 00:08:20 +00:00
Chris Lattner a0a8003f59 disallow preinc of a frameindex. This is not profitable and causes 2-addr 
pass to explode.  This fixes a bunch of llc-beta failures on ppc last night.

llvm-svn: 31661
 2006-11-11 01:00:15 +00:00
Chris Lattner eabc15c1d8 reduce indentation by using early exits. No functionality change. 
llvm-svn: 31660
 2006-11-11 00:56:29 +00:00
Chris Lattner ffad2166e1 move big chunks of code out-of-line, no functionality change. 
llvm-svn: 31658
 2006-11-11 00:39:41 +00:00
Chris Lattner 4eac5f59e6 Fix a dag combiner bug exposed by my recent instcombine patch. This fixes 
CodeGen/Generic/2006-11-10-DAGCombineMiscompile.ll and PPC gsm/toast

llvm-svn: 31644
 2006-11-10 21:37:15 +00:00
Evan Cheng 13440b025c When forming a pre-indexed store, make sure ptr isn't the same or is a pred of value being stored. It would cause a cycle. 
llvm-svn: 31631
 2006-11-10 08:28:11 +00:00
Evan Cheng 6878378390 Don't attempt expensive pre-/post- indexed dag combine if target does not support them. 
llvm-svn: 31598
 2006-11-09 19:10:46 +00:00
Evan Cheng b15000736c Rename ISD::MemOpAddrMode to ISD::MemIndexedMode 
llvm-svn: 31595
 2006-11-09 17:55:04 +00:00
Evan Cheng b58e06bc9e getPostIndexedAddressParts change: passes in load/store instead of its loaded / stored VT. 
llvm-svn: 31584
 2006-11-09 04:29:46 +00:00
Evan Cheng 85e54223cd Match more post-indexed ops. 
llvm-svn: 31569
 2006-11-08 20:27:27 +00:00
Jim Laskey 61feeb90f9 Remove redundant <cmath>. 
llvm-svn: 31561
 2006-11-08 19:16:44 +00:00
Evan Cheng 0303cb9b33 - When performing pre-/post- indexed load/store transformation, do not worry 
about whether the new base ptr would be live below the load/store. Let two
  address pass split it back to non-indexed ops.
- Minor tweaks / fixes.

llvm-svn: 31544
 2006-11-08 08:30:28 +00:00