e18980aeaa
Add support for parsing register lists. We can't use a bitfield to keep track of
...
the registers, because the register numbers may be much greater than the number
of bits available in the machine's register.
I extracted the register list verification code out of the actual parsing of the
registers. This made checking for errors much easier. It also limits the number
of warnings that would be emitted for cascading infractions.
llvm-svn: 118363
2010-11-06 22:36:58 +00:00
9654e108d7
add aliases for movs between seg registers and mem. There are multiple
...
different forms of this instruction (movw/movl/movq) which we reported
as being ambiguous. Since they all do the same thing, gas just picks the
one with the shortest encoding. Follow its lead here.
This implements rdar://8208615
llvm-svn: 118362
2010-11-06 22:35:34 +00:00
7923358842
move the "sh[lr]d op,op" -> "shld $1, op,op" aliases to the .td file.
...
llvm-svn: 118361
2010-11-06 22:25:39 +00:00
b884a8ee44
Return the base register of a register list for the "getReg()" method. This is
...
to satisfy the ClassifyOperand method of the Asm matcher without having to add a
RegList type to every back-end.
llvm-svn: 118360
2010-11-06 22:19:43 +00:00
d6746d5b46
pass literals like $$1 through to the asm matcher. This isn't right yet, but doesn't hurt.
...
llvm-svn: 118359
2010-11-06 22:06:03 +00:00
2abbeded98
work-in-progress
...
llvm-svn: 118358
2010-11-06 22:05:43 +00:00
ee7f1f9914
General cleanup:
...
- Make ARMOperand a class so that some things are internal to the class.
- Reformatting.
llvm-svn: 118357
2010-11-06 21:42:12 +00:00
ca7801e472
go to great lengths to work around a GAS bug my previous patch
...
exposed:
GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)"
even though st(0) is implicit in all other fp stack instructions.
Fortunately, there is an alias for fcomip named "fcompi" and gas does
accept the default argument for the alias (boggle!).
As such, switch the canonical form of this instruction to "pi" instead
of "ip". This makes the code generator and disassembler generate pi,
avoiding the gas bug.
llvm-svn: 118356
2010-11-06 21:37:06 +00:00
64f91b9825
rework the rotate-by-1 instructions to be defined like the
...
shift-by-1 instructions, where the asmstring doesn't contain
the implicit 1. It turns out that a bunch of these rotate
instructions were completely broken because they used 1
instead of $1.
This fixes assembly mismatches on "rclb $1, %bl" and friends,
where we used to generate the 3 byte form, we now generate the
proper 2-byte form.
llvm-svn: 118355
2010-11-06 21:23:40 +00:00
05031e7f1a
change the fp comparison instructions to not have %st0 explicitly
...
listed in its asm string, for consistency with the other similar
instructions.
llvm-svn: 118354
2010-11-06 20:55:09 +00:00
290199f8ee
move the plethora of fp stack aliases to the .td file.
...
llvm-svn: 118353
2010-11-06 20:47:38 +00:00
4869d346e3
add (and document) the ability for alias results to have
...
fixed physical registers. Start moving fp comparison
aliases to the .td file (which default to using %st1 if
nothing is specified).
llvm-svn: 118352
2010-11-06 19:57:21 +00:00
7cef447c14
Add a RegList (register list) object to ARMOperand. It will be used soon to hold
...
(surprise!) a list of registers. Register lists are consecutive, so we only need
to record the start register plus the number of registers.
llvm-svn: 118351
2010-11-06 19:56:04 +00:00
b6f8e8248d
generalize alias support to allow the result of an alias to
...
add fixed immediate values. Move the aad and aam aliases to
use this, and document it.
llvm-svn: 118350
2010-11-06 19:25:43 +00:00
161bf7de25
move fnstsw aliases to .td file, fix typo
...
llvm-svn: 118349
2010-11-06 18:58:32 +00:00
ec66010e80
move in/out aliases to the .td files.
...
llvm-svn: 118348
2010-11-06 18:52:40 +00:00
6881e175c3
move sldt, imul, and movabsq aliases from c++ to .td file.
...
llvm-svn: 118347
2010-11-06 18:44:26 +00:00
fab9413b01
correct suffix matching to search for s/l/t suffixes on
...
floating point stack instructions instead of looking for b/w/l/q.
This fixes issues where we'd accidentally match fistp to fistpl,
when it is in fact an ambiguous instruction.
This changes the behavior of llvm-mc to reject fstp, which was the
correct fix for rdar://8456389:
t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt')
fstp (%rax)
it also causes us to correctly reject fistp and fist, which addresses
PR8528:
t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl')
fistp (%rax)
^
t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl')
fist (%rax)
^
Thanks to Ismail Donmez for tracking down the issue here!
llvm-svn: 118346
2010-11-06 18:28:02 +00:00
63abc84630
Prune includes.
...
llvm-svn: 118342
2010-11-06 11:45:59 +00:00
8300d834c9
Fix grammar.
...
llvm-svn: 118341
2010-11-06 10:51:53 +00:00
4f4bce0682
Fix grammar.
...
llvm-svn: 118340
2010-11-06 10:48:18 +00:00
518e43c453
MatchRegisterName() returns 0 if it can't match the register.
...
llvm-svn: 118339
2010-11-06 10:45:34 +00:00
6d2eb737af
Use TryParseRegister() instead of MatchRegisterName(). The former returns -1
...
while the latter doesn't.
llvm-svn: 118338
2010-11-06 10:40:24 +00:00
8628e2a19c
Add a note.
...
llvm-svn: 118337
2010-11-06 10:37:16 +00:00
8b0a71fc31
document instalias.
...
llvm-svn: 118335
2010-11-06 08:30:26 +00:00
db6f90c61c
fix a bug where we had an implicit assumption that the
...
result instruction operand numbering matched the result pattern.
Fixing this allows us to move the xchg/test aliases to the .td file.
llvm-svn: 118334
2010-11-06 08:20:59 +00:00
89965d7091
Make sure we have movw on the target before using it.
...
Fixes 8559.
llvm-svn: 118333
2010-11-06 07:53:11 +00:00
aa7847df06
move the lcall/ljmp aliases to the .td file.
...
llvm-svn: 118332
2010-11-06 07:48:45 +00:00
9535f90abe
move the "movsd -> movsl" alias to the .td files,
...
tidy up the movsx and movzx aliases.
llvm-svn: 118331
2010-11-06 07:34:58 +00:00
8188fb264f
fix some bugs in the alias support, unblocking changing of "clr" aliases
...
from c++ hacks to proper .td InstAlias definitions. Change them!
llvm-svn: 118330
2010-11-06 07:31:43 +00:00
fecdad6237
Reimplement BuildResultOperands to be in terms of the result instruction's
...
operand list instead of the operand list redundantly declared on the alias
or instruction.
With this change, we finally remove the ins/outs list on the alias. Before:
def : InstAlias<(outs GR16:$dst), (ins GR8 :$src),
"movsx $src, $dst",
(MOVSX16rr8W GR16:$dst, GR8:$src)>;
After:
def : InstAlias<"movsx $src, $dst",
(MOVSX16rr8W GR16:$dst, GR8:$src)>;
This also makes the alias mechanism more general and powerful, which will
be exploited in subsequent patches.
llvm-svn: 118329
2010-11-06 07:14:44 +00:00
b625dd2d87
implement more checking to reject things like:
...
(someinst GR16:$foo, GR32:$foo)
Reimplement BuildAliasOperandReference to be correctly
based on the names of operands in the result pattern,
instead of on the instruction operand definitions.
llvm-svn: 118328
2010-11-06 07:06:09 +00:00
7603052d49
decode and validate instruction alias result definitions.
...
llvm-svn: 118327
2010-11-06 06:54:38 +00:00
23064cb4e5
simplify
...
llvm-svn: 118326
2010-11-06 06:45:08 +00:00
9f093815fa
fix another fixme, replacing a string with a semantic pointer.
...
llvm-svn: 118325
2010-11-06 06:43:11 +00:00
8ffd129950
disolve a hack, having CodeGenInstAlias decode the alias in the .td
...
file instead of the asmmatcher.
llvm-svn: 118324
2010-11-06 06:39:47 +00:00
2db0ea03ba
Hook up the '.code {16|32}' directive to the streamer.
...
llvm-svn: 118310
2010-11-05 22:40:53 +00:00
cbdf7efe1c
Add '.code 32' assembler directive to MC streamers.
...
llvm-svn: 118309
2010-11-05 22:40:09 +00:00
c6db8ce5da
Hook up the '.thumb_func' directive to the streamer.
...
llvm-svn: 118307
2010-11-05 22:33:53 +00:00
0fe92e3fea
Fix past-o.
...
llvm-svn: 118304
2010-11-05 22:11:33 +00:00
5a2c68d308
MC'ize the '.code 16' and '.thumb_func' ARM directives.
...
llvm-svn: 118301
2010-11-05 22:08:08 +00:00
a4076924d1
Disallow the certain NEON modified-immediate forms when generating vorr or vbic.
...
llvm-svn: 118300
2010-11-05 21:57:54 +00:00
45846666f1
Trailing whitespace.
...
llvm-svn: 118296
2010-11-05 20:41:12 +00:00
ff9e507d8e
MC'ize simple ARMConstantValue entry emission (with a FIXME).
...
llvm-svn: 118295
2010-11-05 20:34:24 +00:00
80bb80f5fc
Put class into an anonymous namespace.
...
llvm-svn: 118294
2010-11-05 19:56:38 +00:00
30c4892ea5
Add codegen and encoding support for the immediate form of vbic.
...
llvm-svn: 118291
2010-11-05 19:27:46 +00:00
2bab7570f5
Enable MachO writing for ARM/Darwin. Lots of stuff still doesn't work
...
(relocations, e.g.), but this will allow simple things to flow through.
llvm-svn: 118289
2010-11-05 18:50:35 +00:00
46c2acbcb4
Allow targets to specify the MachO CPUType/CPUSubtype information.
...
llvm-svn: 118288
2010-11-05 18:48:58 +00:00
c75bb744e1
syntaxunified directive is a no-op for MachO writing.
...
llvm-svn: 118287
2010-11-05 18:47:32 +00:00
b51745765a
Add v5 and v7 ARM CPU subtype values.
...
llvm-svn: 118281
2010-11-05 17:48:05 +00:00
1df82e67d1
Add FIXME.
...
llvm-svn: 118280
2010-11-05 17:37:13 +00:00
6c25ca4f2b
When passing a parameter using the 'byval' mechanism, inline code needs to be used
...
to perform the copy, which may be of lots of memory [*]. It would be good if the
fall-back code generated something reasonable, i.e. did the copy in a loop, rather
than vast numbers of loads and stores. Add a note about this. Currently target
specific code seems to always kick in so this is more of a theoretical issue rather
than a practical one now that X86 has been fixed.
[*] It's amazing how often people pass mega-byte long arrays by copy...
llvm-svn: 118275
2010-11-05 15:20:29 +00:00
f4d90ba9f5
CrashRecoveryContext: Add RunSafelyOnThread helper function.
...
llvm-svn: 118272
2010-11-05 07:19:09 +00:00
98512315f7
When passing a huge parameter using the byval mechanism, a long
...
sequence of loads and stores was being generated to perform the
copy on the x86 targets if the parameter was less than 4 byte
aligned, causing llc to use up vast amounts of memory and time.
Use a "rep movs" form instead. PR7170.
llvm-svn: 118260
2010-11-04 21:16:46 +00:00
ed8b7bf9ed
Use arrays instead of constant-sized SmallVectors.
...
llvm-svn: 118257
2010-11-04 18:45:27 +00:00
38d0756b88
Add 118023 back, but with proper spelling for .uleb128/.sleb128.
...
llvm-svn: 118254
2010-11-04 18:17:08 +00:00
bbc0ac2236
Revert previous patch. Some targets don't support uleb and say
...
they do :-(
llvm-svn: 118250
2010-11-04 17:04:24 +00:00
cfd6243940
MCize.
...
llvm-svn: 118249
2010-11-04 16:32:18 +00:00
57c5a20364
Introduce DIBuilder. It is intended to be a front-end friendly interface to emit debuggging information entries in LLVM IR.
...
To create debugging information for a pointer, using DIBUilder front-end just needs
DBuilder.CreatePointerType(Ty, Size);
instead of
DebugFactory.CreateDerivedType(llvm::dwarf::DW_TAG_pointer_type,
TheCU, "", getOrCreateMainFile(),
0, Size, 0, 0, 0, OCTy);
llvm-svn: 118248
2010-11-04 15:01:38 +00:00
a0148df273
Add getFile() to get DIFile of a DIType.
...
llvm-svn: 118247
2010-11-04 14:56:34 +00:00
71049f78ed
In the calling convention logic, ValVT is always a legal type,
...
and as such can be represented by an MVT - the more complicated
EVT is not needed. Use MVT for ValVT everywhere.
llvm-svn: 118245
2010-11-04 10:49:57 +00:00
21acf9fb38
Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli.
...
llvm-svn: 118237
2010-11-04 05:19:35 +00:00
4efe13d8d4
partition operand processing between aliases and instructions.
...
Right now the code is partitioned but the behavior is the same.
This should be improved in the near future. This removes some
uses of TheOperandList.
llvm-svn: 118232
2010-11-04 02:11:18 +00:00
ccde463250
pull name slicing out of BuildInstructionOperandReference so
...
it doesn't do any lexical stuff anymore.
llvm-svn: 118230
2010-11-04 01:58:23 +00:00
897a140e2a
cleanups.
...
llvm-svn: 118228
2010-11-04 01:55:23 +00:00
7108dad130
replace SrcOpNum with SrcOpName, eliminating a numering dependency
...
on the incoming operand list. This also makes the code simpler.
llvm-svn: 118225
2010-11-04 01:42:59 +00:00
cdd4c5443e
System: Add llvm_execute_on_thread, which does what it says.
...
- Primarily useful for running some code with a specified stack size, when
pthreads are available.
llvm-svn: 118222
2010-11-04 01:26:25 +00:00
0fb841fd19
Add ARM fixup info for load/store label references. Probably will need a bit of
...
tweaking when we start using it for object file emission or JIT, but it's a
start.
llvm-svn: 118221
2010-11-04 01:12:30 +00:00
c002463ac4
Add encoding for VSTR.
...
llvm-svn: 118220
2010-11-04 00:59:42 +00:00
4779e3e94a
strength reduce some code, resolving a fixme.
...
llvm-svn: 118219
2010-11-04 00:57:06 +00:00
743081d097
take a big step to making aliases more general and less of a hack:
...
now matchables contain an explicit list of how to populate each
operand in the result instruction instead of having them somehow
magically be correlated to the input inst.
llvm-svn: 118217
2010-11-04 00:43:46 +00:00
a2e098df12
Disable fancy splitting during spilling unless -extra-spiller-splits is given.
...
This way, InlineSpiller does the same amount of splitting as the standard
spiller. Splitting should really be guided by the register allocator, and
doesn't belong in the spiller at all.
llvm-svn: 118216
2010-11-04 00:32:32 +00:00
2eed7a1310
Teach ARM Target to use the tblgen support for generating an MC'ized
...
CodeEmitter.
llvm-svn: 118209
2010-11-03 23:52:49 +00:00
cd536df63c
Add rule to build MC'ized CodeEmitter.
...
llvm-svn: 118207
2010-11-03 23:46:01 +00:00
e4e6bf49f3
Support generating an MC'ized CodeEmitter directly. Maintain a reference to the
...
Fixups list for the instruction so the operand encoders can add to it as
needed.
llvm-svn: 118206
2010-11-03 23:38:14 +00:00
bc9b31c493
Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization.
...
This is both the conceptually correct place for it, as well as allowing it to be more aggressive.
llvm-svn: 118204
2010-11-03 23:15:26 +00:00
0747307049
Add support for code generation of the one register with immediate form of vorr.
...
We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.
llvm-svn: 118201
2010-11-03 22:44:51 +00:00
49b0c45ecf
trailing whitespace
...
llvm-svn: 118199
2010-11-03 22:03:20 +00:00
c6418b105a
Just return undef for invalid masks or elts, and since we're doing that,
...
just do it earlier too.
llvm-svn: 118195
2010-11-03 20:44:42 +00:00
c913201259
Let RegAllocBasic require MachineDominators - they are already available and
...
splitting needs them.
llvm-svn: 118194
2010-11-03 20:39:26 +00:00
cbbd819248
Tag debug output as regalloc
...
llvm-svn: 118193
2010-11-03 20:39:23 +00:00
e4dd7378d0
Optimize generated code for integer materialization a bit.
...
llvm-svn: 118192
2010-11-03 20:21:17 +00:00
896cf04885
rename Operand -> AsmOperand for clarity.
...
llvm-svn: 118190
2010-11-03 19:47:34 +00:00
3ad8df65c5
Fix test.
...
llvm-svn: 118187
2010-11-03 18:21:33 +00:00
bb81f80af6
Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead,
...
all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.
llvm-svn: 118183
2010-11-03 18:16:27 +00:00
c7d82d58b5
This test assumes SSE is present; that is not the default
...
on non-X86 hosts. Hopefully fixes ppc-host buildbot.
llvm-svn: 118182
2010-11-03 18:08:41 +00:00
7d0ac84abd
Add codegen patterns for VST1-lane instructions. Radar 8599955.
...
llvm-svn: 118176
2010-11-03 16:24:53 +00:00
ceb49296ef
Check for extractelement with a variable operand for the element number.
...
For NEON we had been assuming this was always an immediate constant.
llvm-svn: 118175
2010-11-03 16:24:50 +00:00
b8211b80bc
Rename FindExecutable to PrependMainExecutablePath.
...
Makes it more clear that it is just a path manipulation function.
llvm-svn: 118174
2010-11-03 16:14:16 +00:00
189c6c687c
80-col violations, trailing whitespace.
...
llvm-svn: 118173
2010-11-03 16:14:07 +00:00
9d1fe4c40d
Rename PointsToLocalMemory to PointsToLocalOrConstantMemory to make
...
the code more self-documenting.
llvm-svn: 118171
2010-11-03 14:45:05 +00:00
1462777017
Simplify uses of MVT and EVT. An MVT can be compared directly
...
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.
llvm-svn: 118169
2010-11-03 12:17:33 +00:00
900edd4b54
Fix a comment typo.
...
llvm-svn: 118168
2010-11-03 11:55:03 +00:00
f5dda01f33
Inside the calling convention logic LocVT is always a simple
...
value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
llvm-svn: 118167
2010-11-03 11:35:31 +00:00
fcc9e6848a
If we have an undef mask our Elt will be -1 for our access, handle
...
this by using an undef as a pointer.
Fixes rdar://8625016
llvm-svn: 118164
2010-11-03 09:36:40 +00:00
8eb254aed6
Fix typo, pointed out by Trevor Harmon.
...
llvm-svn: 118163
2010-11-03 08:16:50 +00:00
8740ee3637
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
...
llvm-svn: 118160
2010-11-03 06:34:55 +00:00
6f36042557
Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.
...
llvm-svn: 118152
2010-11-03 05:14:24 +00:00
6552a109bb
Put the PC encoding in the correct bit position.
...
llvm-svn: 118151
2010-11-03 04:57:44 +00:00
c63d846ad6
Invert these branches by default, it makes assembly comparisons a little
...
easier to read.
llvm-svn: 118148
2010-11-03 04:29:11 +00:00
e84eb99cbb
The MC code couldn't handle ARM LDR instructions with negative offsets:
...
vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
llvm-svn: 118144
2010-11-03 01:49:29 +00:00
68fb004616
Fix DAGCombiner to avoid going into an infinite loop when it
...
encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff).
This fixes rdar://8606584.
llvm-svn: 118143
2010-11-03 01:47:46 +00:00
fd96701456
Remove unused function.
...
llvm-svn: 118141
2010-11-03 01:35:15 +00:00
e7f7de95e0
Remove the no longer used 'Modifier' optional operand to the ARM
...
printOperand() asm printer helper functions. rdar://8425198
llvm-svn: 118140
2010-11-03 01:11:15 +00:00
50ba3c09bf
Remove unused function.
...
llvm-svn: 118139
2010-11-03 01:07:48 +00:00
c6af2b4066
Break ARM addrmode4 (load/store multiple base address) into its constituent
...
parts. Represent the operation mode as an optional operand instead.
rdar://8614429
llvm-svn: 118137
2010-11-03 01:01:43 +00:00
debf9c502a
Two sets of changes. Sorry they are intermingled.
...
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
"optimize for latency". Call instructions don't have the right latency and
this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
not # of micro-ops since multi-latency instructions is completely executed
even when the predicate is false. Also, some instruction will be "slower"
when they are predicated due to the register def becoming implicit input.
rdar://8598427
llvm-svn: 118135
2010-11-03 00:45:17 +00:00
634ab6c2b7
Modify scheduling itineraries to correct instruction latencies (not operand
...
latencies) of loads.
llvm-svn: 118134
2010-11-03 00:40:22 +00:00
edc76749b3
Factor code out of APInt to form a isUIntN helper function.
...
llvm-svn: 118133
2010-11-03 00:38:40 +00:00
3e6c919469
fix typo, patch by Trevor Harmon (PR8537)
...
llvm-svn: 118131
2010-11-03 00:30:29 +00:00
0baea2aa1b
Print an error as one big string instead of breaking it up.
...
llvm-svn: 118130
2010-11-03 00:24:33 +00:00
a3bb142db6
Delete unused variables.
...
llvm-svn: 118128
2010-11-03 00:09:12 +00:00
ecc4d73498
Remove several unhelpful checks for isValid from sys::Path.
...
llvm-svn: 118127
2010-11-03 00:01:23 +00:00
1e43892e4b
Make sure we're only storing a single bit here.
...
llvm-svn: 118126
2010-11-02 23:59:09 +00:00
9c9bfb6870
per a suggestion by Frits van Bommel, mark all MBlaze Pseudo
...
instructions as isCodeGenOnly in the parent class instead of
sprinkling it throughout the .td files.
llvm-svn: 118125
2010-11-02 23:57:05 +00:00
11d21e8e78
chase owen.
...
llvm-svn: 118124
2010-11-02 23:55:24 +00:00
d0502c1777
tweak this to pass.
...
llvm-svn: 118122
2010-11-02 23:50:17 +00:00
0ebd1fd594
Revert r118097 to fix buildbots.
...
llvm-svn: 118121
2010-11-02 23:47:29 +00:00
daf7a2a7de
temporarily xfail this.
...
llvm-svn: 118120
2010-11-02 23:44:50 +00:00
cc5dce89d4
Completely reject instructions that have an operand in their
...
ins/outs list that isn't specified by their asmstring. Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right. Mark a bunch of ARM instructions that use this as
isCodeGenOnly. Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).
llvm-svn: 118119
2010-11-02 23:40:41 +00:00
1d73c0e462
Tweak the opt -O2 / opt -O3 inliner thresholds to be the same as llvm-gcc and
...
clang are using.
llvm-svn: 118118
2010-11-02 23:40:28 +00:00
31a7eb40c1
Let the -inline-threshold command line argument take precedence over the
...
threshold given to createFunctionInliningPass().
Both opt -O3 and clang would silently ignore the -inline-threshold option.
llvm-svn: 118117
2010-11-02 23:40:26 +00:00
c0a8bee4b0
Don't try to enforce MAXPATHLEN in sys::Path for Unix. OS's can check
...
limits on their own.
llvm-svn: 118113
2010-11-02 23:19:55 +00:00
4d23eb2f0e
make MatchableInfo::Validate reject instructions (like LDR_PRE in ARM)
...
that have complicated tying going on.
llvm-svn: 118112
2010-11-02 23:18:43 +00:00
a8b6315cd7
Simplify.
...
llvm-svn: 118110
2010-11-02 23:16:26 +00:00
beffa5bef1
Inline asm mult-alt constraint tests.
...
llvm-svn: 118107
2010-11-02 23:01:44 +00:00
6e05d6c218
Fix a copy+pasto.
...
llvm-svn: 118106
2010-11-02 22:56:51 +00:00
a47bfef1bf
Avoid manipulating paths in fixed-sized arrays.
...
llvm-svn: 118105
2010-11-02 22:55:34 +00:00
e032dbfd9e
rewrite EmitConvertToMCInst to iterate over the MCInst operands,
...
filling them in one at a time. Previously this iterated over the
asmoperands, which left the problem of "holes". The new approach
simplifies things.
llvm-svn: 118104
2010-11-02 22:55:03 +00:00
f9eebb58b9
Obsessive formatting changes. No functionality impact.
...
llvm-svn: 118103
2010-11-02 22:53:11 +00:00
32d51fa0b5
Simplify this code.
...
llvm-svn: 118102
2010-11-02 22:50:10 +00:00
23436b6530
Omit unused parameter name.
...
llvm-svn: 118099
2010-11-02 22:46:04 +00:00
91da9abbee
Simplify the EncodeInstruction method now that a lot of the special case stuff
...
is handled with the MC encoder.
llvm-svn: 118098
2010-11-02 22:44:12 +00:00
7c30390277
Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning.
...
llvm-svn: 118097
2010-11-02 22:41:42 +00:00
f6e13ceb2b
Use '\0' instead of 0 for nul character constants.
...
llvm-svn: 118096
2010-11-02 22:41:19 +00:00
603bd8f54c
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work
...
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.
llvm-svn: 118094
2010-11-02 22:31:46 +00:00
a4b63e19d2
Rename encoder methods to match naming convention.
...
llvm-svn: 118093
2010-11-02 22:28:01 +00:00
15977afb02
mark a few codegenonly instructions.
...
llvm-svn: 118092
2010-11-02 22:26:33 +00:00
7282901079
appendSuffix: don't append a dot when the suffix is empty.
...
Additionally, move the implementation of appendSuffix to Path.cpp: it is
platform-independent.
llvm-svn: 118089
2010-11-02 22:18:37 +00:00
4fb337560c
Revert r118057, this is better fixed in appendSuffix itself.
...
llvm-svn: 118088
2010-11-02 22:18:28 +00:00
dec87e10fd
Provide correct encodings for the remaining vst variants that we currently generate.
...
llvm-svn: 118087
2010-11-02 22:18:18 +00:00
44e24e5403
Eliminate some temporary std::strings.
...
llvm-svn: 118086
2010-11-02 22:07:47 +00:00
adf88d4c5f
Tentative encodings for the "single element from one lane" variant of vst1.
...
llvm-svn: 118084
2010-11-02 21:54:45 +00:00
5cf8a4a909
merge two large parallel loops in EmitConvertToMCInst, no change
...
in the generated .inc files.
llvm-svn: 118083
2010-11-02 21:49:44 +00:00
b95618cfe0
Add correct encodings for basic variants for vst3 and vst4.
...
llvm-svn: 118082
2010-11-02 21:47:03 +00:00
f8343f87e7
Do relaxations with FT_Org fragments. Fixes the FIXME:
...
// FIXME: We should compute this sooner, we don't want to recurse here, and
// we would like to be more functional.
In MCAssembler::ComputeFragmentSize.
llvm-svn: 118080
2010-11-02 21:38:23 +00:00
64cb0eed22
Removed obsolete section about VC++ project files.
...
llvm-svn: 118072
2010-11-02 21:34:19 +00:00
d80b29d6f7
Add NEON VST1-lane instructions. Partial fix for Radar 8599955.
...
llvm-svn: 118069
2010-11-02 21:18:25 +00:00
fa08e1e277
Add correct encodings for the basic variants for vst2.
...
llvm-svn: 118068
2010-11-02 21:16:58 +00:00
87c62e54e6
Add correct encodings for the basic form of vst1.
...
llvm-svn: 118067
2010-11-02 21:06:06 +00:00
bba85850e3
Micro-optimize.
...
llvm-svn: 118058
2010-11-02 20:52:47 +00:00
35b2013bf8
Don't append a dot on platforms which don't use exe suffixes.
...
llvm-svn: 118057
2010-11-02 20:49:48 +00:00
0ddd57451e
llvmc: Fix tool finding logic.
...
llvm-svn: 118056
2010-11-02 20:47:41 +00:00
9f20daf3b4
Factor out a common encoding class for loads and stores with a lane parameter.
...
llvm-svn: 118055
2010-11-02 20:47:39 +00:00
415c551459
Fix DIType verifier. The element 3 is DIFile now.
...
llvm-svn: 118054
2010-11-02 20:41:13 +00:00
a83859539f
Add correct encodings for the rest of the vld instructions that we generate.
...
llvm-svn: 118053
2010-11-02 20:40:59 +00:00
2c3991acf3
GetDLLSuffix: Remove the leading dot from LTDL_SHLIB_EXT.
...
This allows using GetDLLSuffix() with appendSuffix().
llvm-svn: 118051
2010-11-02 20:32:59 +00:00
f26f4a0535
Trailing whitespace.
...
llvm-svn: 118050
2010-11-02 20:32:52 +00:00
82ee8dad50
FindExecutable: remove the executability check.
...
This makes the behaviour of FindExecutable more consistent across platforms, but
I'm not very happy with the name...
llvm-svn: 118049
2010-11-02 20:32:46 +00:00
a581d8a27a
Make FindProgramByName return paths with slashes unmodified on Windows.
...
This makes its behaviour more consistent across platforms.
llvm-svn: 118048
2010-11-02 20:32:39 +00:00
b4921a035e
80-col violations.
...
llvm-svn: 118045
2010-11-02 20:32:31 +00:00
fcfaf51e52
Path: Add GetEXESuffix() to complement GetDLLSuffix().
...
llvm-svn: 118042
2010-11-02 20:32:26 +00:00
82ae9a95a5
Fixes <rdar://problem/8612856>: During postRAsched, the antidependence
...
breaker needs to check all definitions of the antidepenent register to
avoid multiple defs of the same new register.
llvm-svn: 118032
2010-11-02 18:16:45 +00:00
77d3ead281
a bunch of random cleanup, move a helper to CGT where it belongs.
...
llvm-svn: 118031
2010-11-02 18:10:06 +00:00
e81d45d2cc
Apply patch for use-after-free in InlineAsm constant handling,
...
PR 8522 / 8616046. Test reduction, analysis and patch by Tim Deegan!
(However, review by someone who understands the classes here better
is welcome. John Krum will return!)
llvm-svn: 118030
2010-11-02 17:59:27 +00:00
93a4d44ee6
Sort bit assignments. Cosmetic change only.
...
llvm-svn: 118029
2010-11-02 17:59:04 +00:00
e755966913
Simplify.
...
llvm-svn: 118027
2010-11-02 17:37:00 +00:00
0b7fda23cc
Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke
...
assumptions about stack layout. Specifically, LR must be saved next to FP.
llvm-svn: 118026
2010-11-02 17:35:25 +00:00
a7a903e706
add and update comments.
...
llvm-svn: 118025
2010-11-02 17:34:28 +00:00
28ea9b18cf
refactor/cleanup MatchableInfo by eliminating the Tokens array,
...
merging it into a Token field in Operand, and moving the first
token to an explicit mnemonic field. These were parallel
arrays before (except for the mnemonic) which kept confusing me.
llvm-svn: 118024
2010-11-02 17:30:52 +00:00
5e874982f2
Add support for expressions in .sleb/.uleb directives.
...
llvm-svn: 118023
2010-11-02 17:22:24 +00:00
bc741405a7
If value map does not have register for an argument then try to find frame index before giving up.
...
llvm-svn: 118022
2010-11-02 17:19:03 +00:00
94f2a2578c
Use frameindex, if available, as a last resort to emit debug info for a parameter.
...
llvm-svn: 118020
2010-11-02 17:01:30 +00:00
a5de53640b
Fix comment typo.
...
llvm-svn: 118016
2010-11-02 15:12:48 +00:00
68cbbb027a
Add some comments explaining what MVT and EVT are, and how they differ.
...
llvm-svn: 118014
2010-11-02 13:57:09 +00:00
36eb1ee5eb
Remove trailing whitespace.
...
llvm-svn: 118013
2010-11-02 13:43:07 +00:00
526ffd57d2
Add correct NEON encodings for vld2, vld3, and vld4 basic variants.
...
llvm-svn: 117997
2010-11-02 01:24:55 +00:00
b2abb508ae
Remove an assert - it's possible to be hit, and we just want to avoid
...
handling those cases for now.
llvm-svn: 117996
2010-11-02 01:24:49 +00:00
ac746e1b38
Whitespeace
...
llvm-svn: 117995
2010-11-02 01:22:45 +00:00
e8fccc82e4
No really, no thumb1 for arm fast isel. Also add an informative comment as
...
to what someone would need to do to support thumb1.
llvm-svn: 117994
2010-11-02 01:21:28 +00:00
d64b7c0685
rename operands -> asmoperands to be more descriptive.
...
llvm-svn: 117993
2010-11-02 01:03:43 +00:00
ea26319185
Don't try to split weird critical edges that really aren't:
...
BB#1: derived from LLVM BB %bb.nph28
Live Ins: %AL
Predecessors according to CFG: BB#0
TEST8rr %reg16384<kill>, %reg16384, %EFLAGS<imp-def>; GR8:%reg16384
JNE_4 <BB#2>, %EFLAGS<imp-use,kill>
JMP_4 <BB#2>
Successors according to CFG: BB#2 BB#2
These double CFG edges only ever occur in bugpoint-generated code, so there is
no need to attempt something clever.
llvm-svn: 117992
2010-11-02 00:58:37 +00:00
b3ca2060c0
Attempt to provide correct encodings for a number of other vld1 variants, which we can't test
...
since we can neither generate nor parse them at the moment.
llvm-svn: 117988
2010-11-02 00:24:52 +00:00
9a33835caa
Tidy up.
...
llvm-svn: 117987
2010-11-02 00:16:39 +00:00
f1610f7910
Add aesthetic break.
...
llvm-svn: 117986
2010-11-02 00:14:00 +00:00
e0d4975781
Tweak to fix spelling and grammar in comment.
...
llvm-svn: 117985
2010-11-02 00:13:15 +00:00
ad40234eff
Add correct NEON encodings for the "multiple single elements" form of vld.
...
llvm-svn: 117984
2010-11-02 00:05:05 +00:00
5c86d22e67
MachineLICM should not claim to be preserving the CFG when it can split critical
...
edges on demand.
llvm-svn: 117982
2010-11-01 23:59:55 +00:00
2551f13c83
Be more precise about verifying missing kill flags.
...
It is legal for an instruction to have two operands using the same register,
only one a kill. This is interpreted as a kill.
llvm-svn: 117981
2010-11-01 23:59:53 +00:00
1e32688e4c
When inserting copies during splitting, always use the parent register as the
...
source, and let rewrite() clean it up.
This way, kill flags on the inserted copies are fixed as well during rewrite().
We can't just assume that all the copies we insert are going to be kills since
critical edges into loop headers sometimes require both source and dest to be
live out of a block.
llvm-svn: 117980
2010-11-01 23:59:48 +00:00
e3c48deff5
fix computation of ambiguous instructions to not ignore the mnemonic.
...
FWIW, X86 has 254 ambiguous instructions.
llvm-svn: 117979
2010-11-01 23:57:23 +00:00
2ba03aa618
Explicitly check for non-consant reference in an LDRi12 instruction. Add FIXME
...
for handling the fixup necessary.
llvm-svn: 117978
2010-11-01 23:45:50 +00:00
a3efae35f5
Remove unused function.
...
llvm-svn: 117977
2010-11-01 23:40:56 +00:00
dd9fbaa9c0
Add support for alignment operands on VLD1-lane instructions.
...
This is another part of the fix for Radar 8599955.
llvm-svn: 117976
2010-11-01 23:40:51 +00:00
7e57573844
Add VLD1-lane testcases for quad-register types.
...
llvm-svn: 117975
2010-11-01 23:40:46 +00:00
3f37ade36e
Missed reverting this bit.
...
llvm-svn: 117971
2010-11-01 23:17:54 +00:00
f7e176a3ec
Minor cleanup.
...
llvm-svn: 117969
2010-11-01 23:11:22 +00:00
c28e1db284
give MatchableInfo::Operand a constructor
...
llvm-svn: 117968
2010-11-01 23:08:02 +00:00
60d555c178
rearrange a bit.
...
llvm-svn: 117967
2010-11-01 23:07:52 +00:00
dc44990c7d
Add NEON VLD1-lane instructions. Partial fix for Radar 8599955.
...
llvm-svn: 117964
2010-11-01 22:04:05 +00:00
d7a824006e
Add kill flag verification.
...
At least X86FloatingPoint requires correct kill flags after register allocation,
and targets using register scavenging benefit. Conservative kill flags are not
enough.
llvm-svn: 117960
2010-11-01 21:51:31 +00:00
a5d4b4ffa2
Update kill flags while rewriting instructions after splitting.
...
llvm-svn: 117959
2010-11-01 21:51:29 +00:00
418bd53008
Move the machine operand MC encoding patterns to the parent classes.
...
llvm-svn: 117956
2010-11-01 21:17:06 +00:00
793af5fa07
Use ARM-style comments.
...
llvm-svn: 117955
2010-11-01 21:16:39 +00:00
6186c96765
When folding away a (shl (shr)) pair, we need to check that the bits that will BECOME the low
...
bits are zero, not that the current low bits are zero. Fixes <rdar://problem/8606771>.
llvm-svn: 117953
2010-11-01 21:08:20 +00:00
865dd96f22
use our fancy new MnemonicAlias mechanism to remove a bunch of hacks
...
from X86AsmParser.cpp
llvm-svn: 117952
2010-11-01 21:06:34 +00:00
c6627eec13
When we look at instructions to convert to setting the 's' flag, we need to look
...
at more than those which define CPSR. You can have this situation:
(1) subs ...
(2) sub r6, r5, r4
(3) movge ...
(4) cmp r6, 0
(5) movge ...
We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:
(1) sub r1, r2, r3
(2) sub r4, r5, r6
(3) cmp r4, ...
(5) movge ...
(6) cmp r1, ...
(7) movge ...
We cannot convert (1) to "subs" because of the intervening use of CPSR.
llvm-svn: 117950
2010-11-01 20:41:43 +00:00
ba9a4985a2
Don't assign new registers created during a split to the same stack slot, but
...
give them individual stack slots once the are actually spilled.
llvm-svn: 117945
2010-11-01 19:49:57 +00:00
31fffb62d9
Add basic LiveStacks verification.
...
When an instruction refers to a spill slot with a LiveStacks entry, check that
the spill slot is live at the instruction.
llvm-svn: 117944
2010-11-01 19:49:52 +00:00
cd9da22f68
Use ARM-style comment syntax.
...
llvm-svn: 117941
2010-11-01 18:33:37 +00:00
44be217af1
NEON does not support truncating vector stores. Radar 8598391.
...
llvm-svn: 117940
2010-11-01 18:31:39 +00:00
083ddf7d6a
Covert this test to .s form.
...
llvm-svn: 117939
2010-11-01 18:30:39 +00:00
a7d985738c
Convert this test to .s form.
...
llvm-svn: 117938
2010-11-01 18:26:43 +00:00
e5271a935a
Covert this test to .s form.
...
llvm-svn: 117937
2010-11-01 18:13:11 +00:00
7d45c101e5
Add FIXME.
...
llvm-svn: 117936
2010-11-01 18:11:14 +00:00
051b7893dd
Covert this test to .s form.
...
llvm-svn: 117935
2010-11-01 18:03:16 +00:00
55ebc962ab
Fix test.
...
llvm-svn: 117932
2010-11-01 17:10:53 +00:00
fddf36d254
Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates
...
codegen using the patterns; the latter gates the assembler recognizing the
instruction.
llvm-svn: 117931
2010-11-01 17:08:58 +00:00
13ddd6d410
Write the line info to .debug_line.
...
llvm-svn: 117930
2010-11-01 17:07:14 +00:00
0190a649e8
Mark ARM subtarget features that are available for the assembler.
...
llvm-svn: 117929
2010-11-01 16:59:54 +00:00
99710a871c
trailing whitespace
...
llvm-svn: 117927
2010-11-01 16:44:21 +00:00
72b5488680
Move EmitInstruction to MCObjectStreamer so that ELF and MachO can share it.
...
llvm-svn: 117925
2010-11-01 16:27:31 +00:00
5b373341fc
The T2 extract/pack instructions are only valid in Thumb2 mode. Mark the
...
patterns as such
llvm-svn: 117923
2010-11-01 15:59:52 +00:00
144fb8af58
Add support for .value.
...
llvm-svn: 117922
2010-11-01 15:29:07 +00:00
1614597873
Implement .weakref.
...
llvm-svn: 117911
2010-11-01 14:28:48 +00:00
2623343625
Move instruction encoding bits into the parent class and remove the temporary
...
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.
llvm-svn: 117906
2010-11-01 06:00:39 +00:00
359dd0c6bd
More tests to XFAIL. The arm-and-txt-peephole.ll test passes even when the
...
peephole optimizer is disabled. That's not good at all.
llvm-svn: 117905
2010-11-01 05:59:43 +00:00
7a23c1fb7d
The testcase is now XFAILed. Sorry about the breakage.
...
llvm-svn: 117904
2010-11-01 05:50:55 +00:00
cd4750cb4d
Disable because peephole is disabled.
...
llvm-svn: 117903
2010-11-01 05:48:44 +00:00
1acd6b1edc
"mov[zs]x (mem), GR16" are not ambiguous: the mem
...
must be 8 bits. Support this memory form.
llvm-svn: 117902
2010-11-01 05:41:10 +00:00
dd3b09c234
Implement enough of the missing instalias support to get
...
aliases installed and working. They now work when the
matched pattern and the result instruction have exactly
the same operand list.
This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.
Note that we do not accept instructions like:
movzx 0(%rsp), %rsi
GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand. It could be 8/16/32 bits.
llvm-svn: 117901
2010-11-01 05:34:34 +00:00
fccb9d032f
Convert this test to .s form.
...
llvm-svn: 117900
2010-11-01 05:23:58 +00:00
ad77681253
rename InstructionInfo -> MatchableInfo since it now
...
represents InstAliases as well. Rename
isAssemblerInstruction -> Validate since that is what
it does (modulo the ARM $lane hack).
llvm-svn: 117899
2010-11-01 05:06:45 +00:00
ba465f9a8a
refactor initialization of InstructionInfo to be sharable between
...
instructions and InstAliases. Start creating InstructionInfo's
for Aliases.
llvm-svn: 117898
2010-11-01 04:53:48 +00:00
178f4bb62d
make the asm matcher emitter reject instructions that have comments
...
in their asmstring. Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.
llvm-svn: 117897
2010-11-01 04:44:29 +00:00
39bc53b33a
refactor InstructionInfo to not have a pointer to CodeGenInstruction
...
member, and make isAssemblerInstruction() a method (pushing some code
around inside it).
llvm-svn: 117895
2010-11-01 04:34:44 +00:00
488c201bb7
define a new CodeGenInstAlias. It has an asmstring and operand list for now,
...
todo: the result field.
llvm-svn: 117894
2010-11-01 04:05:41 +00:00
d8adec70f3
factor the operand list (and related fields/operations) out of
...
CodeGenInstruction into its own helper class. No functionality change.
llvm-svn: 117893
2010-11-01 04:03:32 +00:00
86e1c9484f
avoid needless throw/catch/rethrow, stringref'ize some simple stuff.
...
llvm-svn: 117892
2010-11-01 03:19:09 +00:00
a397716081
eliminate the old InstFormatName which is always "AsmString",
...
simplify CodeGenInstruction. No functionality change.
llvm-svn: 117891
2010-11-01 02:15:23 +00:00
517dc95d47
all predicates on an MnemonicAlias must be AssemblerPredicates.
...
llvm-svn: 117890
2010-11-01 02:09:21 +00:00
f7a01e9f46
change the singleton register handling code to be based on Record*'s
...
instead of strings, simplifying it.
llvm-svn: 117889
2010-11-01 01:47:07 +00:00
b80ab36179
Give AsmMatcherInfo a CodeGenTarget, which simplifies a bunch of
...
argument passing. Consolidate all SingletonRegister detection
and handling into a new
InstructionInfo::getSingletonRegisterForToken method instead of
having it scattered about. No change in generated .inc files.
llvm-svn: 117888
2010-11-01 01:37:30 +00:00
25d9c7fa2e
move FlattenVariants out of AsmMatcherEmitter into a shared
...
CodeGenInstruction::FlattenAsmStringVariants method. Use it
to simplify the code in AsmWriterInst, which now no longer
needs to worry about variants.
llvm-svn: 117886
2010-11-01 01:07:14 +00:00
40dd3f0939
add a FIXME, $lane in ARM is an issue that needs to be resolved before
...
this can start rejecting instructions.
llvm-svn: 117885
2010-11-01 00:51:32 +00:00
941c19b7ba
reject instructions that contain a \n in their asmstring. Mark
...
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.
llvm-svn: 117884
2010-11-01 00:46:16 +00:00
baa5126dbc
Add a specialization for 'long', a hole in the set of fundamental
...
specializations provided here. This is a little annoying because its size
changes from platform to platform. If possible, I may follow up with a patch
that uses standard constants to simplify much of this, but assuming for now
that was avoided for a reason.
llvm-svn: 117880
2010-10-31 22:57:03 +00:00
ef5a1c3ec3
Revert r117876 for now, it's causing more testsuite failures.
...
llvm-svn: 117879
2010-10-31 22:42:55 +00:00
0392f1b437
Disable the peephole optimizer until 186.crafty on armv6 is fixed. This is what
...
looks like is happening:
Without the peephole optimizer:
(1) sub r6, r6, #32
orr r12, r12, lr, lsl r9
orr r2, r2, r3, lsl r10
(x) cmp r6, #0
ldr r9, LCPI2_10
ldr r10, LCPI2_11
(2) sub r8, r8, #32
(a) movge r12, lr, lsr r6
(y) cmp r8, #0
LPC2_10:
ldr lr, [pc, r10]
(b) movge r2, r3, lsr r8
With the peephole optimizer:
ldr r9, LCPI2_10
ldr r10, LCPI2_11
(1*) subs r6, r6, #32
(2*) subs r8, r8, #32
(a*) movge r12, lr, lsr r6
(b*) movge r2, r3, lsr r8
(1) is used by (x) for the conditional move at (a). (2) is used by (y) for the
conditional move at (b). After the peephole optimizer, these the flags resulting
from (1*) are ignored and only the flags from (2*) are considered for both
conditional moves.
llvm-svn: 117876
2010-10-31 22:07:12 +00:00
3dbe6cc155
Attach a GCModuleInfo to a MachineFunction.
...
llvm-svn: 117867
2010-10-31 20:38:38 +00:00
d689026899
fix a crash on:
...
let Constraints = "$val = $dst", Defs = [EFLAGS] in, isCodeGenOnly = 1 {
we now get:
X86InstrCompiler.td:653:52: error: Expected class, def, defm, multiclass or let definition
let Constraints = "$val = $dst", Defs = [EFLAGS] in, isCodeGenOnly = 1 {
^
llvm-svn: 117863
2010-10-31 19:27:15 +00:00
7ff334687d
fix the !eq operator in tblgen to return a bit instead of an int.
...
Use this to make the X86 and ARM targets set isCodeGenOnly=1
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.
llvm-svn: 117862
2010-10-31 19:22:57 +00:00
9492c17baf
two changes: make the asmmatcher generator ignore ARM pseudos properly,
...
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.
llvm-svn: 117861
2010-10-31 19:15:18 +00:00
33fc3e095b
reapply r117858 with apparent editor malfunction fixed (somehow I
...
got a dulicated line).
llvm-svn: 117860
2010-10-31 19:10:56 +00:00
e59eef3dd1
revert r117858 while I check out a failure I missed.
...
llvm-svn: 117859
2010-10-31 19:05:32 +00:00
9293008e90
the asm matcher can't handle operands with modifiers (like ${foo:bar}).
...
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the
instruction 'isCodeGenOnly'.
Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are
doing this.
llvm-svn: 117858
2010-10-31 18:48:12 +00:00
eb8c0fc2eb
sketch out the planned instruction alias mechanism, add some comments about
...
how the push/pop mnemonic aliases are wrong.
llvm-svn: 117857
2010-10-31 18:43:46 +00:00
fb0a48ef96
Factorize the duplicated logic for choosing the right argument
...
calling convention out of the fast and normal ISel files, and
into the calling convention TD file.
llvm-svn: 117856
2010-10-31 13:21:44 +00:00
fa7e6f2417
Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86,
...
which has the same logic specified in the CallingConv TD file.
This brings FastISel in line with the standard X86 ISel.
llvm-svn: 117855
2010-10-31 13:02:38 +00:00
df71c2c9c7
Explain the return value of CCAssignFn.
...
llvm-svn: 117854
2010-10-31 10:29:14 +00:00
3fe87a1eed
Add support for files with more than 65280 sections. No testcase since
...
it would be a bit too big :-)
llvm-svn: 117849
2010-10-31 00:16:26 +00:00
04b0a3e651
Make sure we have a legal type (and simple) before continuing.
...
llvm-svn: 117848
2010-10-30 21:25:26 +00:00
c940bcf564
Validate HTML.
...
llvm-svn: 117847
2010-10-30 21:07:28 +00:00
4dd6ca9a69
add missing tag
...
llvm-svn: 117846
2010-10-30 20:21:00 +00:00
43690071cf
have GetAliasRequiredFeatures get its features from
...
AsmMatcherInfo so we don't have two places that know the
feature -> enum mapping. No functionality change.
llvm-svn: 117845
2010-10-30 20:15:02 +00:00
a0e871901b
simplify code that creates SubtargetFeatureInfo, ensuring that features
...
that are only used by MnemonicAliases will be found.
llvm-svn: 117844
2010-10-30 20:07:57 +00:00
25896af4bb
fix a fixme in stringmatcher, having it generate nice looking code if the
...
'tomatch' code contains \n's.
llvm-svn: 117843
2010-10-30 19:57:17 +00:00
f9ec2fb34a
fix typos and some serious bugs in feature handling (but not for
...
cases that are currently exercised). Thanks to Frits van Bommel for
the great review!
llvm-svn: 117840
2010-10-30 19:47:49 +00:00
aac142cc06
Resolve a terrible hack in tblgen: instead of hardcoding
...
"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.
llvm-svn: 117831
2010-10-30 19:38:20 +00:00
2cb092dc55
Implement (and document!) support for MnemonicAlias's to have Requires
...
directives, allowing things like this:
def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
Move the rest of the X86 MnemonicAliases over to the .td file.
llvm-svn: 117830
2010-10-30 19:23:13 +00:00
ec56397eb4
fix build problem
...
llvm-svn: 117828
2010-10-30 18:57:07 +00:00
cf9b6e3107
diagnose targets that define two alises with the same 'from' mnemonic
...
with a useful error message instead of having tblgen explode with an
assert.
llvm-svn: 117827
2010-10-30 18:56:12 +00:00
477fba4f54
emit the mnemonic aliases in their own helper function instead of
...
inline into MatchInstructionImpl.
llvm-svn: 117826
2010-10-30 18:48:18 +00:00
57bfc66d60
really zap alias.
...
llvm-svn: 117824
2010-10-30 18:23:25 +00:00
462bc666d2
move fcompi alias to .td file and zap some useless code.
...
llvm-svn: 117823
2010-10-30 18:22:53 +00:00
daae9eea8a
move rep aliases to td file
...
llvm-svn: 117822
2010-10-30 18:17:33 +00:00
fa40aee871
move sal aliases to .td file.
...
llvm-svn: 117821
2010-10-30 18:14:54 +00:00
4d9f157203
fix an encoding mismatch where "sal %eax, 1" was not using the short encoding
...
for shl. Caught by inspection.
llvm-svn: 117820
2010-10-30 18:13:10 +00:00
069132311a
move a bunch more aliases from .cpp -> .td file.
...
llvm-svn: 117819
2010-10-30 18:07:17 +00:00
b4a1674421
move cmov aliases to .td file.
...
llvm-svn: 117818
2010-10-30 17:56:50 +00:00
f04cbe6291
move setcc and jcc aliases from .cpp to .td
...
llvm-svn: 117817
2010-10-30 17:51:45 +00:00
72c0b59e81
move some code.
...
llvm-svn: 117816
2010-10-30 17:38:55 +00:00
ba7b4fea97
implement (and document!) the first kind of MC assembler alias, which
...
just remaps one mnemonic to another. Convert a few of the X86 aliases
from .cpp to .td code.
llvm-svn: 117815
2010-10-30 17:36:36 +00:00
e490b5c29e
add a test for the ud2a alias.
...
llvm-svn: 117803
2010-10-30 17:01:25 +00:00
e659aba516
Now that the MallocInst no longer exists, this workaround for
...
it claiming not to have side-effects is no longer needed.
llvm-svn: 117789
2010-10-30 16:12:16 +00:00
685b77332c
Allow specifying a CPU to llvm-mc, so that we can properly set up subtarget
...
feature lists for instruction pattern predicates.
llvm-svn: 117788
2010-10-30 15:57:50 +00:00
bbe2bbd7f7
Add FIXME.
...
llvm-svn: 117787
2010-10-30 14:54:23 +00:00
4cf25f5ba9
Clean up comments.
...
llvm-svn: 117785
2010-10-30 13:48:28 +00:00
584850b921
80 columns.
...
llvm-svn: 117784
2010-10-30 13:46:39 +00:00
b8f3b14dfb
If a function does a volatile load from a global constant, do not
...
consider it to be readonly. In fact, don't even consider it to be
readonly if it does a volatile load from an AllocaInst either (it
is debatable as to whether readonly would be correct or not in this
case; play safe for the moment). This fixes PR8279.
llvm-svn: 117783
2010-10-30 12:59:44 +00:00
a71c9e2ebf
Tidy up.
...
llvm-svn: 117782
2010-10-30 12:59:16 +00:00
fa898b2b24
Rename alignof -> alignOf to avoid irritating C++'0x compilers,
...
PR8423, patch by nobled.
llvm-svn: 117774
2010-10-30 05:14:01 +00:00
de30afc3d9
stay out of the reserved namespace
...
llvm-svn: 117773
2010-10-30 04:57:14 +00:00
549a31cd34
simplify this code.
...
llvm-svn: 117771
2010-10-30 04:35:59 +00:00
44e5981c1b
split MaybeParseRegister into its two logical uses, eliminating malloc+free traffic.
...
llvm-svn: 117769
2010-10-30 04:09:10 +00:00
7b275105d6
Avoid re-evaluating MI.getNumOperands() every iteration of the loop.
...
llvm-svn: 117766
2010-10-30 01:40:16 +00:00
80717dd7c6
Include MachineBasicBlock numbers in viewCFG() output.
...
llvm-svn: 117765
2010-10-30 01:26:19 +00:00
0cfc497f19
Make sure copies are inserted after any exception handling labels at the top of
...
a basic block.
llvm-svn: 117764
2010-10-30 01:26:16 +00:00
ef54185724
Add SkipPHIsAndLabels from PHIElimination to MachineBasicBlock. It is needed
...
elsewhere.
llvm-svn: 117763
2010-10-30 01:26:14 +00:00
db84d8f4fd
Disable more of physical register live intervals verification.
...
llvm-svn: 117762
2010-10-30 01:26:11 +00:00
6d808331ae
Print out register class of spilled register.
...
llvm-svn: 117761
2010-10-30 01:26:09 +00:00
7ed597149b
Overhaul memory barriers in the ARM backend. Radar 8601999.
...
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain. It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions. Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions. Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.
llvm-svn: 117756
2010-10-30 00:54:37 +00:00
ea9dca4c6c
Add polly support to the build system.
...
Update the cmake and autoconf build system to compile polly
as a shared library if it is checked out into tools/polly. In case
polly is not checked out, nothing changes.
This models the way clang can be added to llvm if checked out to tools/clang.
Also rebuild configure.
Patch contributed by ether.
llvm-svn: 117755
2010-10-30 00:54:26 +00:00
74ef9e184e
Encode the register list operands for ARM mode LDM/STM instructions.
...
llvm-svn: 117753
2010-10-30 00:37:59 +00:00
193961bb1a
Some instructions end with an "ls" prefix, but it doesn't indicate that they are
...
conditional. Check for those instructions explicitly.
llvm-svn: 117747
2010-10-29 23:50:21 +00:00
a319ba384d
Mult-alt constraint incremental development step 3.
...
llvm-svn: 117746
2010-10-29 23:37:38 +00:00
2b3f25e031
Teach machine cse to eliminate instructions with multiple physreg uses and defs. rdar://8610857.
...
llvm-svn: 117745
2010-10-29 23:36:03 +00:00
069f38d1bf
Remove hard tab characters.
...
llvm-svn: 117742
2010-10-29 23:23:15 +00:00
5f0d616ae5
80 column fix.
...
llvm-svn: 117741
2010-10-29 23:21:57 +00:00
96d828448f
trailing whitespace
...
llvm-svn: 117740
2010-10-29 23:21:03 +00:00
58018e62a8
s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand
...
encoder functions.
llvm-svn: 117738
2010-10-29 23:19:55 +00:00
99cce36cf5
Fix fpscr <-> GPR latency info.
...
llvm-svn: 117737
2010-10-29 23:16:55 +00:00
45834a0065
Be more strict on when we produce an undefined reference. In gas a file with
...
just
.type foo,@object
will produce an undefined reference to foo. On the other hand, a file with
just
.weakref bar, foo
will not. It is somewhat hard to support both in MC since both statements
should create the symbols. It should be possible if we really need to by
adding to the flags, but hopefully that is not necessary.
With this patch we do not produce a undefined reference in any of those cases.
The assembly file needs an actual use for the undefined reference to be
present.
This is in preparation for a patch implementing .weakref.
llvm-svn: 117735
2010-10-29 23:09:31 +00:00
96f54c9d3e
Apply a patch from Frits van Bommel to fix the CMake build.
...
llvm-svn: 117731
2010-10-29 22:36:50 +00:00
67a6f32c59
Clean up indentation and other whitespace.
...
llvm-svn: 117728
2010-10-29 22:20:45 +00:00
8ecf98b04f
Remove trailing whitespace.
...
llvm-svn: 117727
2010-10-29 22:20:43 +00:00
0eccfc2693
trailing whitespace
...
llvm-svn: 117724
2010-10-29 22:13:48 +00:00
9d07f39ace
Fix 80-column violation.
...
llvm-svn: 117722
2010-10-29 22:03:07 +00:00
11ee456e23
Change instcombine's getShuffleMask to represent undef with negative values.
...
This code had previously used 2*N, where N is the mask length, to represent
undef. That is not safe because the shufflevector operands may have more
than N elements -- they don't have to match the result type.
llvm-svn: 117721
2010-10-29 22:03:05 +00:00
08882be86c
Remove DAG combiner patch to fold vector splats. Instcombiner does it now.
...
llvm-svn: 117720
2010-10-29 22:03:02 +00:00
cb11b48e7a
Make instcombine a little more aggressive in combining vector shuffles.
...
Allow splats even if they don't match either of the original shuffles,
possibly due to undef entries in the shuffles masks. Radar 8597790.
Also fix some 80-column violations.
llvm-svn: 117719
2010-10-29 22:02:50 +00:00
31f23b48ba
add FIXME
...
llvm-svn: 117718
2010-10-29 21:56:51 +00:00
4a0c2d73c3
Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in
...
the ARMExpandPseudos pass rather than during the asm lowering.
llvm-svn: 117714
2010-10-29 21:35:25 +00:00
8e7b73743d
Update testcase since we're no longer doing the constant forwarding inline with correlated value propagation.
...
llvm-svn: 117712
2010-10-29 21:18:23 +00:00
5c308f8452
Handle comparison values we already have - this fixes the consumer-typeset
...
failure for llvm-gcc on arm fast isel.
llvm-svn: 117710
2010-10-29 21:08:19 +00:00
374e1464ae
Give up on doing in-line instruction simplification during correlated value propagation. Instruction simplification
...
needs to be guaranteed never to be run on an unreachable block. However, earlier block simplifications may have
changed the CFG to make block that were reachable when we began our iteration unreachable by the time we try to
simplify them. (Note that this also means that our depth-first iterators were potentially being invalidated).
This should not have a large impact on code quality, since later runs of instcombine should pick up these simplifications.
Fixes PR8506.
llvm-svn: 117709
2010-10-29 21:05:17 +00:00
72dfc6a7c7
Convert this test to .s form.
...
llvm-svn: 117708
2010-10-29 20:39:19 +00:00
e477b1ad30
ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need to
...
handle it in the asm lowering.
llvm-svn: 117707
2010-10-29 20:37:06 +00:00
665b9e37ff
Convert this test to .s form.
...
llvm-svn: 117704
2010-10-29 20:23:45 +00:00
cb8aec8ec9
Fix typo.
...
llvm-svn: 117703
2010-10-29 20:21:49 +00:00
3b7e05bb97
ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS.
...
llvm-svn: 117702
2010-10-29 20:21:36 +00:00
b75ce4f816
not is testing for a normal exit with a non-zero value. It shouldn't
...
return success if the child process is killed with a signal.
llvm-svn: 117701
2010-10-29 20:20:29 +00:00
fe4b52a066
Convert this test to .s form.
...
llvm-svn: 117699
2010-10-29 20:17:07 +00:00
dcb354b234
Make ScalarEvolution::forgetLoop forget all contained loops too, because
...
they may have ValuesAtScopes map entries referencing their outer loops.
This fixes a user-after-free reported in PR8471.
llvm-svn: 117698
2010-10-29 20:16:10 +00:00
0093f9a634
Convert this test to .s form.
...
llvm-svn: 117696
2010-10-29 20:12:34 +00:00
4e57b52394
ARM mode LDREX*/STREX* binary encodings.
...
llvm-svn: 117695
2010-10-29 19:58:57 +00:00
ede9d861db
Covert this test to .s form.
...
llvm-svn: 117694
2010-10-29 19:56:07 +00:00
6f9cd06ff9
Convert this test to .s form.
...
llvm-svn: 117693
2010-10-29 19:51:11 +00:00
3ad831ac77
Convert this test to .s form.
...
llvm-svn: 117690
2010-10-29 19:45:32 +00:00
302596e5e1
Convert this test to .s form.
...
llvm-svn: 117689
2010-10-29 19:37:05 +00:00
6ae3fba7c8
Encoding information for ARM conditional move instructions.
...
llvm-svn: 117687
2010-10-29 19:28:17 +00:00
efdf57afdc
Convert this test to .s form.
...
llvm-svn: 117686
2010-10-29 19:17:08 +00:00
221b524fe1
Convert this test to .s form.
...
llvm-svn: 117685
2010-10-29 19:09:08 +00:00
b916206545
Covert this test to .s form.
...
llvm-svn: 117684
2010-10-29 19:05:26 +00:00
733d1b1a60
Convert this test to .s form.
...
llvm-svn: 117683
2010-10-29 18:58:30 +00:00
7d23a78188
Convert this test to .s form.
...
llvm-svn: 117682
2010-10-29 18:48:59 +00:00
7eed15242d
Convert this file to less fragile .s form.
...
llvm-svn: 117681
2010-10-29 18:41:40 +00:00
13ff53e7b6
Replace this test with the less fragile .s version. Still XFAIL'd, since the ASM parser doesn't parse vabal yet.
...
llvm-svn: 117679
2010-10-29 18:31:26 +00:00
0cce30fd34
Fix sign error.
...
llvm-svn: 117677
2010-10-29 18:21:18 +00:00
66aa87021c
Covert this test to a .s file to reduce fragility.
...
llvm-svn: 117676
2010-10-29 18:18:40 +00:00
6c1414f9c2
Avoiding overly aggressive latency scheduling. If the two nodes share an
...
operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.
BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB
=>
BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB
This fixed the recent 256.bzip2 regression.
llvm-svn: 117675
2010-10-29 18:09:28 +00:00
0c4c5ca6e1
- Don't schedule nodes with only MVT::Flag and MVT::Other values for latency.
...
- Compute CopyToReg use operand latency correctly.
llvm-svn: 117674
2010-10-29 18:07:31 +00:00
140542fcea
Don't transfer unused values to the new intervals formed by splitting.
...
llvm-svn: 117673
2010-10-29 17:47:49 +00:00
16bd9f1ab5
Handle ARM addrmode5 instructions with an offset.
...
llvm-svn: 117672
2010-10-29 17:41:25 +00:00
25ed920b0e
Silence Release build warnings.
...
llvm-svn: 117671
2010-10-29 17:40:05 +00:00
dff6a6e4f1
Teach ConnectedVNInfoEqClasses::Classify to deal with unused values.
...
We don't want unused values forming their own equivalence classes, so we lump
them all together in one class, and then merge them with the class of the last
used value.
llvm-svn: 117670
2010-10-29 17:37:29 +00:00
2cdca45861
Never propagate the idom value out of a block that defines its own value.
...
llvm-svn: 117669
2010-10-29 17:37:25 +00:00
e8360b7182
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
...
llvm-svn: 117667
2010-10-29 17:29:13 +00:00
5bc07d2bce
Check if ErrMsg is null. This fixes the "not" command.
...
llvm-svn: 117666
2010-10-29 17:20:42 +00:00
e1db7f2005
Fix these error messages to be less confusing. These error
...
messages primarily indicate errors running the viewer, not
errors with the graph file itself.
llvm-svn: 117665
2010-10-29 17:03:40 +00:00
fc81579b5e
Make Program::Wait differentiate execution failure due to the file
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being not found from the file being not executable.
llvm-svn: 117664
2010-10-29 16:54:25 +00:00
305ec65927
Revert 117660. Apparently it's not as trivial as that...
...
llvm-svn: 117663
2010-10-29 16:50:53 +00:00
15aedf93bf
Simplify.
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- DIFile F = getFieldAs<DIFile>(6);
- return F.getDirectory();
+ return getFieldAs<DIFile>(6).getDirectory();
llvm-svn: 117662
2010-10-29 16:42:37 +00:00
cae3c53b31
Make Program::Wait provide an error message string for errors
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executing the child process and abnormal child process termination.
llvm-svn: 117661
2010-10-29 16:39:01 +00:00
8682b69b81
ARM addrmode5 instructions have neither writeback nor post-indexed modes.
...
llvm-svn: 117660
2010-10-29 16:38:59 +00:00
094da1dc44
Check for (unlikely) errors from FindExecutable.
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llvm-svn: 117658
2010-10-29 16:18:26 +00:00
9e08246040
Fix these error messages to not mention PATH in cases where
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PATH isn't actually searched, and to not mention the executable
directory when it isn't actually searched.
llvm-svn: 117657
2010-10-29 16:15:23 +00:00
a42c78fadb
Delete this obsolete comment.
...
llvm-svn: 117655
2010-10-29 16:03:34 +00:00
624bcc7371
Trailing whitespace.
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llvm-svn: 117651
2010-10-29 14:46:02 +00:00
08b8c534f7
ARMAsmParser: Plug a memory leak.
...
llvm-svn: 117648
2010-10-29 09:43:39 +00:00
91d7b90185
Add an unreachable to silence warning - the switch is actually
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fully enumerated.
llvm-svn: 117647
2010-10-29 09:26:59 +00:00
dd7bb199b7
unittests/CMakeLists.txt: Don't use RTTI, or linking failed.
...
llvm-svn: 117646
2010-10-29 08:59:43 +00:00
c2d549e007
This may be an ARM target, so check for _Unwind_SjLj_Resume.
...
llvm-svn: 117643
2010-10-29 07:46:01 +00:00
821de3d161
test/Scripts/macho-dump: Make hack for Python-2.4. [PR7995]
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With Python-2.4, Reader::read64 always returns (unexpected) long integer.
FileCheck detects failure on test/MC/MachO among '0' and '0L'.
CentOS5(aka RHEL5 clone) provides python-2.4.
llvm-svn: 117637
2010-10-29 01:14:16 +00:00
15a43965ac
Teach memdep to use pointsToConstantMemory to determine that loads
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from constant memory don't alias any stores.
llvm-svn: 117636
2010-10-29 01:14:04 +00:00
b101af04b4
Convert this test to a .s file, so that it's not sensitive to codegen changes.
...
llvm-svn: 117633
2010-10-29 01:01:56 +00:00
c16d9afe04
Add a basic testcase for TBAA-aware DSE.
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llvm-svn: 117632
2010-10-29 00:54:02 +00:00
13d7e0d012
Fix broken equivalence class calculation. We could probably also use
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EquvivalenceClasses.h except it looks like overkill when elements are continuous
integers.
llvm-svn: 117631
2010-10-29 00:40:59 +00:00
b98755472e
Print out the connected components in the verifier after complaining about their
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multiplicity.
llvm-svn: 117630
2010-10-29 00:40:57 +00:00
a2578fe7f3
Run a verification pass before any splitting to better distribute blame.
...
llvm-svn: 117629
2010-10-29 00:40:55 +00:00
5d6f6a061b
add simple support for addrmode5 operands, allowing
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vldr.64 to work. I have no idea if this is fully right, but
it is in the right direction.
llvm-svn: 117626
2010-10-29 00:27:31 +00:00
fc1b990b1d
The ARM jit cannot handle these tests as of 2010-10-27.
...
(A PR will be linked to this rev.)
llvm-svn: 117620
2010-10-29 00:23:43 +00:00
6e0d58968d
Ignore empty blocks.
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llvm-svn: 117615
2010-10-28 22:11:59 +00:00
d27b05e54a
give better error diagnostics, for example:
...
t.s:1:14: error: invalid operand for instruction
vldr.64 d17, [r0]
^
instead of:
t.s:1:1: error: unrecognized instruction
vldr.64 d17, [r0]
^
llvm-svn: 117611
2010-10-28 21:41:58 +00:00
f20f79808e
hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes
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the opcode string in the inst dump, e.g.:
vmov r2, r3, d17 @ encoding: [0x31,0x2b,0x53,0xec]
@ <MCInst #989 VMOVRRD
@ <MCOperand Reg:68>
@ <MCOperand Reg:69>
@ <MCOperand Reg:19>
@ <MCOperand Imm:14>
@ <MCOperand Reg:0>>
The "VMOVRRD" is new.
llvm-svn: 117609
2010-10-28 21:37:33 +00:00
8aefb66376
Improvements to .section parsing:
...
* If we have a M or a G, reject sections without the type
* Only parse the flag specific arguments if we have M or G
* Parse the corresponding arguments for M and G
We ignore the G arguments and flag for now.
llvm-svn: 117608
2010-10-28 21:33:33 +00:00
327a61423b
most simple arm instructions match correctly now,
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it looks like we're not handling [] operands though
llvm-svn: 117607
2010-10-28 21:31:07 +00:00
1be0697ab9
fix the asmmatcher generator to handle targets with no RegisterPrefix
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(like ARM) correctly. With this change, we can now match "bx lr"
because we recognize lr as a register.
llvm-svn: 117606
2010-10-28 21:28:42 +00:00
9487de6160
move a method out of line.
...
llvm-svn: 117605
2010-10-28 21:28:01 +00:00
9f9f4ebf0c
remove the rest of hte owningptr's, no functionality change.
...
llvm-svn: 117603
2010-10-28 20:52:15 +00:00
dc5e7065a4
One day, physical register live ranges will be sensible.
...
llvm-svn: 117602
2010-10-28 20:44:22 +00:00
9268658646
Fix indentation.
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llvm-svn: 117601
2010-10-28 20:41:11 +00:00
c9f90c2a32
Replace SplitKit SSA update with an iterative algorithm very similar to the one
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in SSAUpdaterImpl.h
Verifying live intervals revealed that the old method was completely wrong, and
we need an iterative approach to calculating PHI placemant. Fortunately, we have
MachineDominators available, so we don't have to compute that over and over
like SSAUpdaterImpl.h must.
Live-out values are cached between calls to mapValue() and computed in a greedy
way, so most calls will be working with very small block sets.
Thanks to Bob for explaining how this should work.
llvm-svn: 117599
2010-10-28 20:34:52 +00:00
e172a8b794
Make MachineDominators available for SplitEditor. We are going to need it for
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proper SSA updating.
This doesn't cause MachineDominators to be recomputed since we are already
requiring MachineLoopInfo which uses dominators as well.
llvm-svn: 117598
2010-10-28 20:34:50 +00:00
1005cf323d
Add a temporary command line option to verify machine code after each spill or
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split.
llvm-svn: 117597
2010-10-28 20:34:47 +00:00
47215f4e04
Revert r117582, which reverted r77396. Searching PATH for a string
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which contains slashes is inconsistent with the meaning of PATH on
Unix-type platforms, and pretty surprising.
If the user has given a specific path to execute and we can't
execute it, we should fail and say why. (Apparently the new
posix_spawn code doesn't always say why, but that's a separate
issue.)
llvm-svn: 117596
2010-10-28 20:34:33 +00:00
9f414eee8c
Backward compatibility. Gracefully handle older versions of debug info.
...
llvm-svn: 117595
2010-10-28 20:08:13 +00:00
63760ba38e
Add support for the .string directive.
...
llvm-svn: 117592
2010-10-28 20:02:27 +00:00
1c75865037
Do not work too hard to find type's file info. There is a special field to record file info.
...
llvm-svn: 117588
2010-10-28 19:50:08 +00:00
99811141c1
Fix indentation.
...
llvm-svn: 117586
2010-10-28 19:40:13 +00:00
3c5a54e4b9
Defined weak symbols should have non-zero value.
...
llvm-svn: 117585
2010-10-28 19:39:57 +00:00
4b94986562
llvmc: Make ExecuteProgram() look in the driver directory first.
...
llvm-svn: 117584
2010-10-28 19:33:08 +00:00
fdba1308ee
Remove an unnecessary check and an unnecessary temporary.
...
llvm-svn: 117583
2010-10-28 19:33:04 +00:00
d7faab5c95
Revert r77396.
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Original commit message:
On "Unix", if Program::FindProgramByName is given a name containing
slashes, just go with it, regardless of whether it looks like it will
be executable. This follows the behavior of sh(1) more closely.
It's better when behaviour is consistent between platforms. This change also
makes FindExecutable() behave as expected on unix-likes (before this commit, it
used to always succeed).
llvm-svn: 117582
2010-10-28 19:32:58 +00:00
0e9d9b51eb
Trailing whitespace.
...
llvm-svn: 117581
2010-10-28 19:32:53 +00:00
a90bee3ee8
80-col violations.
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llvm-svn: 117580
2010-10-28 19:32:47 +00:00
1742de5cbe
Do not rely on context to find file info. It is already provided as a separate field.
...
llvm-svn: 117577
2010-10-28 19:14:28 +00:00
29f70afbae
Fix relocations with renamed symbols.
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llvm-svn: 117575
2010-10-28 19:08:03 +00:00
851a994a42
Reduce malloc thrashing.
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llvm-svn: 117572
2010-10-28 18:41:23 +00:00
505607e4c6
PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.
...
llvm-svn: 117571
2010-10-28 18:34:10 +00:00
6cd76e63f8
Aliases defined with .symver should copy the binding of the symbols they alias.
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Move the existing patching for undefined symbols so that all the patching
is done in the same function.
llvm-svn: 117570
2010-10-28 18:33:03 +00:00
c4b69051b7
Technically DIFile scope should also be handled here.
...
llvm-svn: 117563
2010-10-28 17:30:52 +00:00
b24ba7be49
rearrange ParseRegisterList.
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llvm-svn: 117560
2010-10-28 17:23:41 +00:00
bd7c9fa36b
refactor some code to simplify it, eliminating some owningptr's.
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llvm-svn: 117559
2010-10-28 17:20:03 +00:00
f63da12be9
Teach the DAG combiner to fold a splat of a splat. Radar 8597790.
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Also do some minor refactoring to reduce indentation.
llvm-svn: 117558
2010-10-28 17:06:14 +00:00
41e6cebb40
Use the IDVal directly as there's no need to convert to std::string.
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Pointed out by Chris!
llvm-svn: 117557
2010-10-28 16:57:58 +00:00
fdac6365ab
Implement .equ directive as a synonym to .set.
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llvm-svn: 117553
2010-10-28 16:22:58 +00:00
efb139130f
Testcase for PR8494 (invalid bitcode crashing the bitcode reader).
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llvm-svn: 117552
2010-10-28 15:57:30 +00:00
89d412a140
Fix PR8494: when reading invalid bitcode, getTypeByID may return
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a null pointer.
llvm-svn: 117551
2010-10-28 15:47:26 +00:00
936ba3af28
Implement R_X86_64_DTPOFF32.
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llvm-svn: 117548
2010-10-28 15:11:03 +00:00
2dbec3f762
Implement TLSLD.
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llvm-svn: 117547
2010-10-28 15:02:40 +00:00
e8f08be11c
Implement DTPOFF.
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llvm-svn: 117546
2010-10-28 14:48:59 +00:00
b1f9380cac
Document LLVM_BUILD_TESTS, LLVM_INCLUDE_TESTS. New convenience target
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UnitTests for building all the unit tests.
llvm-svn: 117545
2010-10-28 14:38:35 +00:00
6f23eb380d
Implement TLSLDM.
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llvm-svn: 117544
2010-10-28 14:37:09 +00:00
b3b49bbc39
Implement VK_GOTNTPOFF and switch RelocNeedsGOT to use VariantKind.
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llvm-svn: 117543
2010-10-28 14:22:44 +00:00
080d86fecc
Reindent.
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llvm-svn: 117538
2010-10-28 08:25:44 +00:00
ff310737e5
Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
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llvm-svn: 117531
2010-10-28 06:47:08 +00:00
0165e25564
Disable most of the ARM vfp / NEON MC tests. These are too fragile to be useful.
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I'll work with Jim, Owen, and Bill on an alternative testing strategy until
the assembly parser is available.
llvm-svn: 117530
2010-10-28 06:46:17 +00:00
959807fa37
test/Transforms/SimplifyLibCalls/floor.ll: Mark as XFAIL:win32 due to lack of nearbyintf on MSVC. [PR8466]
...
llvm-svn: 117529
2010-10-28 06:46:04 +00:00
a1d4430cc8
tools/llvm-shlib/Makefile: Support for FreeBSD and OpenBSD.
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Thanks to Yuri Gribov and Vladimir Kirillov!
*BSD(s) have environ(7) in CRT startup and cannot resolve "environ" at linking llvm.so.
environ(7) is used inlib/System/Unix/Program.inc.
llvm-svn: 117528
2010-10-28 06:45:57 +00:00
15597538ae
clarify that not having the ".o file writing" feature
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doesn't mean that you can't get a .o file. Apparently
this is confusing :)
llvm-svn: 117523
2010-10-28 02:22:02 +00:00
e2c211c1b9
Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh.
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llvm-svn: 117520
2010-10-28 02:00:25 +00:00
ff1c862f8e
- Assign load / store with shifter op address modes the right itinerary classes.
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- For now, loads of [r, r] addressing mode is the same as the
[r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
is "free".
llvm-svn: 117519
2010-10-28 01:49:06 +00:00
523fa3a2e8
Fix a major bug in operand latency computation. The use index must be adjusted
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by the number of defs first for it to match the instruction itinerary.
llvm-svn: 117518
2010-10-28 01:46:29 +00:00
9c3f6bf2bf
Fix pastos in handling of AVX cvttsd2si, PR8491.
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Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!
llvm-svn: 117514
2010-10-28 00:35:54 +00:00
2ef668840a
Add correct NEON encodings for vtbl and vtbx.
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llvm-svn: 117513
2010-10-28 00:18:46 +00:00
14be930317
Add correct NEON encodings for vext, vtrn, vuzp, and vzip.
...
llvm-svn: 117512
2010-10-27 23:56:39 +00:00
6c55007edb
Fix compiler warnings about signed/unsigned comparisons.
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llvm-svn: 117511
2010-10-27 23:49:00 +00:00
16bb87a90e
Teach InstCombine not to use Add and Neg on FP. PR 8490.
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llvm-svn: 117510
2010-10-27 23:45:18 +00:00
59bbc545e0
Shifter ops are not always free. Do not fold them (especially to form
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complex load / store addressing mode) when they have higher cost and
when they have more than one use.
llvm-svn: 117509
2010-10-27 23:41:30 +00:00
cbdf7e874a
Putting r117193 back except for the compile time cost. Rather than assuming fallthroughs uses all registers, just gather the union of all successor liveins.
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llvm-svn: 117506
2010-10-27 23:17:17 +00:00
338de3ee56
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
...
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
llvm-svn: 117505
2010-10-27 23:12:14 +00:00
9f371e7efa
Tests for NEON encoding of vrev.
...
llvm-svn: 117502
2010-10-27 22:54:49 +00:00
fadb951e5b
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
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for specifying fractional bits for fixed point conversions.
llvm-svn: 117501
2010-10-27 22:49:00 +00:00
055de2c789
Trailing whitespace
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llvm-svn: 117496
2010-10-27 21:39:08 +00:00
ed9652f959
Provide correct encodings for the get_lane and set_lane variants of vmov.
...
llvm-svn: 117495
2010-10-27 21:28:09 +00:00
f8537165bd
Add support for R_386_TLS_GD, R_386_TLS_LE_32, R_386_TLS_IE and R_386_TLS_LE.
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llvm-svn: 117494
2010-10-27 21:23:52 +00:00
5e7cb5fc27
Added the x86 instruction ud2b (2nd official undefined instruction).
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llvm-svn: 117485
2010-10-27 20:46:49 +00:00
f4ea7084c5
JIT imm12 encoding for constant pool entry references.
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llvm-svn: 117483
2010-10-27 20:39:40 +00:00
c7334a146e
SelectionDAG shuffle nodes do not allow operands with different numbers of
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elements than the result vector type. So, when an instruction like:
%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is:
shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]
That's probably the right thing for x86 but for NEON, we'd much rather have:
shuffle [a,b,c,d], undef
Teach the DAG combiner how to do that transformation for ARM. Radar 8597007.
llvm-svn: 117482
2010-10-27 20:38:28 +00:00
Bill Wendling