Commit Graph

1638 Commits

Author SHA1 Message Date
Artem Belevich 4d80105792 [CUDA] Fix names of __nvvm_vote* intrinsics.
Also fixed a syntax error in activemask().

Differential Revision: https://reviews.llvm.org/D38188

llvm-svn: 314129
2017-09-25 17:55:26 +00:00
Jina Nahias 123c599a0f fixing a bug in mask[z]_set1 intrinsic
Differential Revision: https://reviews.llvm.org/D38231

Change-Id: I80bbff9cbe93e4be54d8a761ef9723edf3f57c57
llvm-svn: 314102
2017-09-25 13:38:08 +00:00
Artem Belevich b542f1f3df [CUDA] Fixed order of words in the names of shfl builtins.
Differential Revision: https://reviews.llvm.org/D38147

llvm-svn: 313899
2017-09-21 18:46:39 +00:00
Artem Belevich 42960b4188 [NVPTX] Implemented bar.warp.sync, barrier.sync, and vote{.sync} instructions/intrinsics/builtins.
Differential Revision: https://reviews.llvm.org/D38148

llvm-svn: 313898
2017-09-21 18:44:49 +00:00
Artem Belevich 4654dc89be [NVPTX] Implemented shfl.sync instruction and supporting intrinsics/builtins.
Differential Revision: https://reviews.llvm.org/D38090

llvm-svn: 313820
2017-09-20 21:23:07 +00:00
Jina Nahias 3ad702a1ed Lowering Mask Set1 intrinsics to LLVM IR
This patch, together with a matching llvm patch (https://reviews.llvm.org/D37669), implements the lowering of X86 mask set1 intrinsics to IR.

Differential Revision: https://reviews.llvm.org/D37668

llvm-svn: 313624
2017-09-19 11:00:27 +00:00
Craig Topper 04370d3a82 [X86] Disable _mm512_maskz_set1_epi64 intrinsic on 32-bit targets to prevent a backend isel failure.
The __builtin_ia32_pbroadcastq512_mem_mask we were previously trying to use in 32-bit mode is not implemented in the x86 backend and causes isel to fail in release builds. In debug builds it fails even earlier during legalization with an llvm_unreachable.

While there add the missing test case for this intrinsic for this for 64-bit mode.

This fixes PR34631. D37668 should be able to recover this for 32-bit mode soon. But I wanted to fix the crash ahead of that.

llvm-svn: 313392
2017-09-15 20:27:59 +00:00
Artem Belevich 9d0052160f [CUDA] Work around a new quirk in CUDA9 headers.
In CUDA-9 some of device-side math functions that we need are conditionally
defined within '#if _GLIBCXX_MATH_H'. We need to temporarily undo the guard
around inclusion of math_functions.hpp.

Differential Revision: https://reviews.llvm.org/D37906

llvm-svn: 313369
2017-09-15 17:30:53 +00:00
Martin Storsjo 0fd7c5ccd6 [Headers] Fix the return type of _InterlockedCompareExchange_rel
This was a typo in SVN r282447, where it was added.

llvm-svn: 313232
2017-09-14 07:04:59 +00:00
Sjoerd Meijer c05609ca36 This adds the _Float16 preprocessor macro definitions.
Differential Revision: https://reviews.llvm.org/D34695

llvm-svn: 313152
2017-09-13 15:23:19 +00:00
Yael Tsafrir 23e7733230 [X86] Lower _mm[256|512]_[mask[z]]_avg_epu[8|16] intrinsics to native llvm IR
Differential Revision: https://reviews.llvm.org/D37562

llvm-svn: 313011
2017-09-12 07:46:32 +00:00
Artem Belevich 8af4e23d1e [CUDA] Added rudimentary support for CUDA-9 and sm_70.
For now CUDA-9 is not included in the list of CUDA versions clang
searches for, so the path to CUDA-9 must be explicitly passed
via --cuda-path=.

On LLVM side NVPTX added sm_70 GPU type which bumps required
PTX version to 6.0, but otherwise is equivalent to sm_62 at the moment.

Differential Revision: https://reviews.llvm.org/D37576

llvm-svn: 312734
2017-09-07 18:14:32 +00:00
Justin Lebar 3310888aec [CUDA] Add device overloads for non-placement new/delete.
Summary:
Tests have to live in the test-suite, and so will come in a separate
patch.

Fixes PR34360.

Reviewers: tra

Subscribers: llvm-commits, sanjoy

Differential Revision: https://reviews.llvm.org/D37539

llvm-svn: 312681
2017-09-07 00:37:20 +00:00
Simon Pilgrim 1ba2bf2162 [X86][AVX512] _mm512_stream_load_si512 should take a void const* argument (PR33977)
Based off the Intel Intrinsics guide, we should expect a void const* argument.

Prevents 'passing 'const void *' to parameter of type 'void *' discards qualifiers' warnings.

Differential Revision: https://reviews.llvm.org/D37449

llvm-svn: 312523
2017-09-05 10:06:41 +00:00
Craig Topper 5ece4cfe1e [X86] Implement broadcastf32x2 and broadcasti32x2 intrinsics using __builtin_shufflevector instead builtins
This patch implements the broadcastf32x2/broadcasti32x2 intrinsics using __builtin_shufflevector.

Differential Revision: https://reviews.llvm.org/D37287

llvm-svn: 312135
2017-08-30 16:15:12 +00:00
Saleem Abdulrasool 65101adb16 Headers: explicitly specify double-word alignment
GCC will interpret `__attribute__((__aligned__))` as 8-byte alignment on
ARM, but clang will not.  Explicitly specify the alignment.  This
mirrors the declaration in libunwind.

llvm-svn: 311576
2017-08-23 16:57:55 +00:00
Saleem Abdulrasool 75cfabef35 Headers: give _Unwind_Control_Block double-word alignment
The C++ ABI requires that the exception object (which under AEABI is the
`_Unwind_Control_Block`) is double-word aligned.  The attribute was
applied to the `_Unwind_Exception` type, but not the
`_Unwind_Control_Block`.  This should fix the libunwind test for the
alignment of the exception type.

llvm-svn: 311563
2017-08-23 15:35:33 +00:00
Yaxun Liu a3c3d7b442 [OpenCL] Remove extra select functions from opencl-c.h
OpenCL spec v2.0 s6.13.6:

gentype select (gentype a,
gentype b,
igentype c)

gentype select (gentype a,
gentype b,
ugentype c)

igentype and ugentype must have the same number
of elements and bits as gentype.

Differential Revision: https://reviews.llvm.org/D36259

llvm-svn: 310160
2017-08-05 02:23:47 +00:00
Yaxun Liu 39195062c2 Add OpenCL 2.0 atomic builtin functions as Clang builtin
OpenCL 2.0 atomic builtin functions have a scope argument which is ideally
represented as synchronization scope argument in LLVM atomic instructions.

Clang supports translating Clang atomic builtin functions to LLVM atomic
instructions. However it currently does not support synchronization scope
of LLVM atomic instructions. Without this, users have to use LLVM assembly
code to implement OpenCL atomic builtin functions.

This patch adds OpenCL 2.0 atomic builtin functions as Clang builtin
functions, which supports generating LLVM atomic instructions with
synchronization scope operand.

Currently only constant memory scope argument is supported. Support of
non-constant memory scope argument will be added later.

Differential Revision: https://reviews.llvm.org/D28691

llvm-svn: 310082
2017-08-04 18:16:31 +00:00
Bruno Cardoso Lopes d89a1eb4fb [Headers][Darwin] Allow #include_next<float.h> to work on Darwin prior to 10.7
This fixes PR31504 and it's a follow up from adding #include_next<float.h>
for Darwin in r289018.

rdar://problem/29856682

llvm-svn: 309752
2017-08-01 22:10:36 +00:00
Simon Pilgrim c14865c0c5 [X86][AVX] Ensure vector non-temporal load/store intrinsics force pointer alignment (PR33830)
Clang specifies a max type alignment of 16 bytes on darwin targets (annoyingly in the driver not via cc1), meaning that the builtin nontemporal stores don't correctly align the loads/stores to 32 or 64 bytes when required, resulting in lowering to temporal unaligned loads/stores.

This patch casts the vectors to explicitly aligned types prior to the load/store to ensure that the require alignment is respected.

Differential Revision: https://reviews.llvm.org/D35996

llvm-svn: 309488
2017-07-29 15:33:34 +00:00
Simon Pilgrim 0b37ffbbf9 Strip trailing whitespace. NFCI.
llvm-svn: 309383
2017-07-28 14:01:51 +00:00
Saleem Abdulrasool b5eca2f9a2 Headers: fix _Unwind_{G,S}etGR for non-EHABI targets
The EHABI definition was being inlined into the users even when EHABI
was not in use.  Adjust the condition to ensure that the right version
is defined.

llvm-svn: 309327
2017-07-27 21:56:25 +00:00
Saleem Abdulrasool 9c13bbe953 Headers: improve ARM EHABI coverage of unwind.h
Ensure that we define the `_Unwind_Control_Block` structure used on ARM
EHABI targets.  This is needed for building libc++abi with the unwind.h
from the resource dir.  A minor fallout of this is that we needed to
create a typedef for _Unwind_Exception to work across ARM EHABI and
non-EHABI targets.  The structure definitions here are based originally
on the documentation from ARM under the "Exception Handling ABI for the
ARM® Architecture" Section 7.2.  They are then adjusted to more closely
reflect the definition in libunwind from LLVM.  Those changes are
compatible in layout but permit easier use in libc++abi and help
maintain compatibility between libunwind and the compiler provided
definition.

llvm-svn: 309226
2017-07-26 22:55:23 +00:00
Mandeep Singh Grang 79249e1be7 [clang] Add ARM64 support to armintr.h for MSVC compatibility
Summary: This fixes compiling with headers from the Windows SDK for ARM64.

Reviewers: compnerd, ruiu, mstorsjo

Reviewed By: compnerd, mstorsjo

Subscribers: mgorny, aemerson, javed.absar, kristof.beyls, llvm-commits, cfe-commits

Differential Revision: https://reviews.llvm.org/D35862

llvm-svn: 309081
2017-07-26 05:29:40 +00:00
Ulrich Weigand 6af2559562 [SystemZ] Add support for IBM z14 processor (3/3)
This patch updates the vecintrin.h header file to provide the new
set of high-level vector built-in functions.  This matches the
updated definition implemented by other compilers for the platform,
indicated by the pre-defined macro __VEC__ == 10302.

Note that some of the new functions (notably those involving the
vector float data type) are only available with -march=z14
(indicated by __ARCH__ == 12).

llvm-svn: 308199
2017-07-17 17:47:35 +00:00
Ekaterina Romanova 03ecd774ba [DOXYGEN] Corrected typos and incorrect parameters description.
Corrected several typos and incorrect parameters description that Sony
's techinical writer found during review.

I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream.

llvm-svn: 307838
2017-07-12 20:18:55 +00:00
Zvi Rackover 064f00061b X86 Intrinsics: _bit_scan_forward should not be under #ifdef __RDRND__
Summary:
The _bit_scan_forward and _bit_scan_reverse intrinsics were accidentally
masked under the preprocessor checks that prune intrinsics definitions for the
benefit of faster compile-time on Windows. This patch moves the
definitons out of that region.

Fixes pr33722

Reviewers: craig.topper, aaboud, thakis

Reviewed By: craig.topper

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D35184

llvm-svn: 307524
2017-07-10 07:13:56 +00:00
Craig Topper b2f8b311d1 [X86] Add more feature flag bit defines to cpuid.h for gcc compatibility.
llvm-svn: 307507
2017-07-09 17:43:11 +00:00
Craig Topper f6e8408a11 [X86] Add __get_cpuid_count to cpuid.h. Update __get_cpuid to check the maximum level support before accessing the leaf. Rename level to leaf everywhere.
This matches gcc behavior.

llvm-svn: 307506
2017-07-09 17:43:10 +00:00
Ekaterina Romanova cb3603a4eb [DOXYGEN] Corrected several typos and incorrect parameters description that Sony's techinical writer found during review.
I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream.

llvm-svn: 304840
2017-06-06 22:58:01 +00:00
Benjamin Kramer c796245431 [PPC] Make altivec conversion function macros.
The second argument must be a constant, otherwise instruction selection
will fail. always_inline is not enough for isel to always fold
everything away at -O0.

Sadly the overloading turned this into a big macro mess. Fixes PR33212.

llvm-svn: 304205
2017-05-30 11:37:29 +00:00
Oren Ben Simhon 140c1fb9ec [X86] Adding avx512_vpopcntdq feature set and its intrinsics
AVX512_VPOPCNTDQ is a new feature set that was published by Intel.
The patch represents the Clang side of the addition of six intrinsics for two new machine instructions (vpopcntd and vpopcntq).
It also includes the addition of the new feature set.

Differential Revision: https://reviews.llvm.org/D33170

llvm-svn: 303857
2017-05-25 13:44:11 +00:00
Tony Jiang 9aa2c0383d [PowerPC] Implement vec_xxsldwi builtin.
The vec_xxsldwi builtin is missing from altivec.h. This has been requested by
developers working on libvpx for VP9 support for Google.

The patch fixes PR: https://bugs.llvm.org/show_bug.cgi?id=32653
Differential Revision: https://reviews.llvm.org/D33236

llvm-svn: 303766
2017-05-24 15:54:13 +00:00
Tony Jiang bbc48e9164 [PowerPC] Implement vec_xxpermdi builtin.
The vec_xxpermdi builtin is missing from altivec.h. This has been requested by
developers working on libvpx for VP9 support for Google.

The patch fixes PR: https://bugs.llvm.org/show_bug.cgi?id=32653
Differential Revision: https://reviews.llvm.org/D33053

llvm-svn: 303760
2017-05-24 15:13:32 +00:00
Ekaterina Romanova bfc1e3a84e (1) Fixed mismatch in intrinsics names in declarations and in doxygen comments.
(2) Removed uncessary anymore \c commands, since the same effect will be achived by <c> ... </c> sequence. 

I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream.

llvm-svn: 303228
2017-05-17 01:46:11 +00:00
Ekaterina Romanova 1d4a0f270c [DOXYGEN] Minor improvements in doxygen comments.
Separated very long brief sections into two sections. 

I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream.

llvm-svn: 303031
2017-05-15 03:25:04 +00:00
Egor Churaev 44800c5aba [OpenCL] Added checking OpenCL version for cl_khr_mipmap_image built-ins
Reviewers: Anastasia, cfe-commits

Reviewed By: Anastasia

Subscribers: bader, yaxunl

Differential Revision: https://reviews.llvm.org/D32897

llvm-svn: 302630
2017-05-10 08:23:01 +00:00
Simon Pilgrim 073c4e66b0 [X86][LWP] Remove MSVC LWP intrinsics stubs.
Now provided in lwpintrin.h

llvm-svn: 302559
2017-05-09 17:50:16 +00:00
Simon Pilgrim 7855510ae3 [X86][LWP] Removing LWP todo comment. NFCI.
LWP / lwpintrin.h is now supported

llvm-svn: 302557
2017-05-09 17:43:16 +00:00
Simon Pilgrim 3511348dbb [X86][LWP] Add clang support for LWP instructions.
This patch adds support for the the LightWeight Profiling (LWP) instructions which are available on all AMD Bulldozer class CPUs (bdver1 to bdver4).

Differential Revision: https://reviews.llvm.org/D32770

llvm-svn: 302418
2017-05-08 12:09:45 +00:00
Sam Parker b9ea36f9c1 [ARM] ACLE Chapter 9 intrinsics
Implemented the remaining integer data processing intrinsics from
the ARM ACLE v2.1 spec, such as parallel arithemtic and DSP style
multiplications.

Differential Revision: https://reviews.llvm.org/D32282

llvm-svn: 302131
2017-05-04 08:37:59 +00:00
Simon Pilgrim 96d02f5503 [X86][AVX] Added support for _mm256_zext* helper intrinsics (PR32839)
llvm-svn: 301749
2017-04-29 17:17:06 +00:00
Ekaterina Romanova ea8702d393 [DOXYGEN] Minor improvements in doxygen comments.
- I removed doxygen comments for the intrinsics that "alias" the other existing documented intrinsics and that only sligtly differ in spelling (single underscores vs. double underscores). 
 #define _tzcnt_u16(a)     (__tzcnt_u16((a)))

It will be very hard to keep the documentation for these "aliases" in sync with the documentation for the intrinsics they alias to. Out of sync documentation will be more confusing than no documentation.

I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream.

llvm-svn: 301652
2017-04-28 16:45:39 +00:00
Simon Pilgrim 99ed27053d [X86][SSE] Add _mm_set_pd1 (PR32827)
Matches _mm_set_ps1 implementation

llvm-svn: 301637
2017-04-28 10:28:32 +00:00
Duncan P. N. Exon Smith e77a3aff6f Headers: Make the type of SIZE_MAX the same as size_t
size_t is usually defined as unsigned long, but on 64-bit platforms,
stdint.h currently defines SIZE_MAX using "ull" (unsigned long long).
Although this is the same width, it doesn't necessarily have the same
alignment or calling convention.  It also triggers printf warnings when
using the format flag "%zu" to print SIZE_MAX.

This changes SIZE_MAX to reuse the compiler-provided __SIZE_MAX__, and
provides similar fixes for the other integers:

  - INTPTR_MIN
  - INTPTR_MAX
  - UINTPTR_MAX
  - PTRDIFF_MIN
  - PTRDIFF_MAX
  - INTMAX_MIN
  - INTMAX_MAX
  - UINTMAX_MAX
  - INTMAX_C()
  - UINTMAX_C()

... and fixes the typedefs for intptr_t and uintptr_t to use
__INTPTR_TYPE__ and __UINTPTR_TYPE__ instead of int32_t, effectively
reverting r89224, r89226, and r89237 (r89221 already having been
effectively reverted).

We can probably also kill __INTPTR_WIDTH__, __INTMAX_WIDTH__, and
__UINTMAX_WIDTH__ in a follow-up, but I was hesitant to delete all the
per-target CHECK lines in this commit since those might serve their own
purpose.

rdar://problem/11811377

llvm-svn: 301593
2017-04-27 21:49:45 +00:00
Eric Fiselier 56be04284f Use __CLANG_ATOMIC_TYPE_LOCK_FREE macros in `stdatomic.h`
Summary: This patch makes the header `stdatomic.h` work when `-fms-compatibility` is specified.

Reviewers: rsmith

Reviewed By: rsmith

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D32322

llvm-svn: 300919
2017-04-20 23:07:38 +00:00
Ekaterina Romanova 0a40d67b20 [DOXYGEN] Minor improvements in doxygen comments.
- To be consistent with the rest of the intrinsics headers, I removed the tags <i> .. </i> for marking instruction names in italics in in smmintrin.h. 

- Formatting changes to fit into 80 characters. 

I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream.

llvm-svn: 300578
2017-04-18 19:44:07 +00:00
Simon Pilgrim 9f6e79c5e4 [X86][SSE] Update MOVNTDQA non-temporal loads to generic implementation (clang)
MOVNTDQA non-temporal aligned vector loads can be correctly represented using generic builtin loads, allowing us to remove the existing x86 intrinsics.

LLVM companion patch: D31767.

Differential Revision: https://reviews.llvm.org/D31766

llvm-svn: 300326
2017-04-14 15:05:57 +00:00
Sanjay Patel bd0d0068ef [x86] fix AVX FP cmp intrinsic documentation (PR28110)
This copies the text used in the #define statements to the code comments. 
The conflicting text comes from AMD manuals, but those are wrong. Sadly, 
that FP cmp text has not been updated even after some docs were updated 
for Zen:
http://support.amd.com/en-us/search/tech-docs 
( AMD64 Architecture Programmer's Manual Volume 4 )

See PR28110 for more discussion:
https://bugs.llvm.org/show_bug.cgi?id=28110

Differential Revision: https://reviews.llvm.org/D31428

llvm-svn: 300068
2017-04-12 15:19:08 +00:00
Hans Wennborg 5c3c51fe05 Implement _interlockedbittestandset as a builtin
It's used by MS headers in VS 2017 without including intrin.h, so we
can't implement it in the header anymore.

Differential Revision: https://reviews.llvm.org/D31736

llvm-svn: 299782
2017-04-07 16:41:47 +00:00
Craig Topper 01bba17819 Recommit r299321 '[X86] Add __extension__ to f16c macro intrinsics to suppress warnings about compound literals when compiled for with earlier language standards enabled.'
The bot didn't recover after the revert. So it looks like this wasn't the issue.

llvm-svn: 299397
2017-04-03 22:59:30 +00:00
Craig Topper 27b71e5b1b Revert r299321 '[X86] Add __extension__ to f16c macro intrinsics to suppress warnings about compound literals when compiled for with earlier language standards enabled.' to see if recovers a fuzzer bot.
llvm-svn: 299382
2017-04-03 19:43:47 +00:00
Craig Topper bf82498301 [AVX-512] Fix a couple more intrinsic macros I missed in r299346.
llvm-svn: 299347
2017-04-03 03:51:57 +00:00
Craig Topper ac9959eb53 [AVX-512] Fix some intrinsic macros that use the wrong macro parameter names and don't have parentheses around them.
Thanks to Matthew Barr for reporting this issue.

llvm-svn: 299346
2017-04-03 03:41:29 +00:00
Craig Topper ce272ae2c5 [X86] Add __extension__ to f16c macro intrinsics to suppress warnings about compound literals when compiled for with earlier language standards enabled.
Fixes PR32491.

llvm-svn: 299321
2017-04-02 03:02:53 +00:00
Hans Wennborg 043f402586 [X86] Implement __readgsqword (and the rest) as builtins (PR32373)
It seems MS headers have started using __readgsqword, and since it's
used in a header that doesn't include intrin.h, we can't implement it as
an inline function anymore.

That was already the case for __readfsdword, which Saleem added support
for in r220859. This patch reuses that codegen to implement all of
__read[fg]s{byte,word,dword,qword}.

Differential Revision: https://reviews.llvm.org/D31248

llvm-svn: 298538
2017-03-22 19:13:13 +00:00
Ekaterina Romanova 6a5702a093 [DOXYGEN] Improvements to smmintrin.h and emmintrin.h intrinsics.
I made some small changes in smmintrin.h and emmintrin.h intrinsics.
 - changed some regular comments '//' into doxygen-style comments '///' where necessary
 - removed some trailing spaces in doxygen comments.

I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream.

llvm-svn: 298371
2017-03-21 13:34:06 +00:00
Simon Pilgrim 60e924985c [X86][AVX512] Add _mm512_cvtsd_f64 and _mm512_cvtss_f32 intrinsics (PR32305)
Differential Revision: https://reviews.llvm.org/D31155

llvm-svn: 298364
2017-03-21 12:46:13 +00:00
Eric Christopher 5ba576ffe6 Fix parsing of htmxlintrin.h in C++ mode
- Fix a variable naming mismatch
 - Fix gcc extension pointer arithmetic on void to cast to char *.
 - Test that the header (and htmintrin.h) parse.

llvm-svn: 298318
2017-03-20 22:31:33 +00:00
Anastasia Stulova bb27dfe049 [OpenCL] Fix extension guards for atomic functions
Review: D30830

Patch by James Price!

llvm-svn: 298256
2017-03-20 15:02:54 +00:00
Igor Breger f050b797ac [X86][AVX512][Clang][Intrinsics] Adding missing intrinsics to Clang .
Summary:
Adding missing intrinsics :
    _mm512_set_epi16,
    _mm512_set_epi8,
    _mm512_permutevar_epi32
    _mm512_mask_permutevar_epi32

Reviewers: zvi, guyblank, eladcohen, craig.topper

Reviewed By: craig.topper

Subscribers: craig.topper, cfe-commits

Differential Revision: https://reviews.llvm.org/D31034

llvm-svn: 298208
2017-03-19 08:27:16 +00:00
Craig Topper 6afc436a78 [AVX-512] Change the input type for some load intrinsics to take void type like the spec (and the test cases say).
llvm-svn: 298042
2017-03-17 05:59:25 +00:00
Craig Topper 2e5058c403 [AVX-512] Add missing typecasts and parentheses to _mm512_mask_i64gather_ps. My macro cleanup script I used on the others last year must have missed it.
llvm-svn: 298040
2017-03-17 05:14:37 +00:00
Bruno Cardoso Lopes ae1249e4f2 [Headers] Reapply: Add #include_next for tgmath.h on Darwin
Reapply r289181 but rename the include guard to avoid
conflict with the one from Darwin.

Allow darwin to provide additional definitions and implementation
specifc values for tgmath.h on Apple platforms.

rdar://problem/19019845

llvm-svn: 298013
2017-03-16 23:19:00 +00:00
Egor Churaev 60c30ae1f1 [OpenCL] Implement as_type operator as alias of __builtin_astype.
Reviewers: Anastasia

Reviewed By: Anastasia

Subscribers: cfe-commits, yaxunl, bader

Differential Revision: https://reviews.llvm.org/D28136

llvm-svn: 297947
2017-03-16 12:15:10 +00:00
Reid Kleckner b04cb9ab7a [MS] Add support for __ud2 and __int2c MSVC intrinsics
This was requested in PR31958 and elsewhere.

llvm-svn: 297057
2017-03-06 19:43:16 +00:00
Oren Ben Simhon 259b091669 [X86] DAZ Macros Relocation
The DAZ feature introduces the denormal zero support for x86.
Currently the definitions are located under SSE3 header, however there are some SSE2 targets that support the feature as well.

Differential Revision: https://reviews.llvm.org/D30194

llvm-svn: 296296
2017-02-26 11:58:15 +00:00
Simon Pilgrim a81d45a1ba [X86][XOP] Fix type conversion warning in vpcmov generic implementations.
llvm-svn: 295584
2017-02-18 23:47:34 +00:00
Craig Topper 117892098a [X86] Replace XOP vpcmov builtins with native vector logical operations.
llvm-svn: 295570
2017-02-18 21:15:30 +00:00
Ekaterina Romanova ff266f5236 Added doxygen comments to smmintrin.h's intrinsics.
Note: The doxygen comments are automatically generated based on Sony's intrinsic
s document.

I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream.

llvm-svn: 295404
2017-02-17 02:49:50 +00:00
Anastasia Stulova 58984e7087 [OpenCL] Correct ndrange_t implementation
Removed ndrange_t as Clang builtin type and added
as a struct type in the OpenCL header.

Use type name to do the Sema checking in enqueue_kernel
and modify IR generation accordingly.

Review: D28058

Patch by Dmitry Borisenkov!  
 

llvm-svn: 295311
2017-02-16 12:27:47 +00:00
Craig Topper f0d1147fae [AVX-512] Replace 512-bit masked packss/packus builtins and replace with new unmasked builtins.
These new unmasked builtins will enable us to easily support optimizing these builtins in InstCombine in the backend.

llvm-svn: 295291
2017-02-16 06:32:07 +00:00
Reid Kleckner 2a02c2e331 Fix some warnings in intrin.h
llvm-svn: 295082
2017-02-14 18:38:19 +00:00
Reid Kleckner 04f9f91da6 [MS] Implement the __fastfail intrinsic as a builtin
__fastfail terminates the process immediately with a special system
call. It does not run any process shutdown code or exception recovery
logic.

Fixes PR31854

llvm-svn: 294606
2017-02-09 18:31:06 +00:00
Craig Topper 4574226c3f [X86] Clzero flag addition and inclusion under znver1
1. Adds the command line flag for clzero.
2. Includes the clzero flag under znver1.
3. Defines the macro for clzero.
4. Adds a new file which has the intrinsic definition for clzero instruction.

Patch by Ganesh Gopalasubramanian with some additional tests from me.

Differential revision: https://reviews.llvm.org/D29386

llvm-svn: 294559
2017-02-09 06:10:14 +00:00
Ekaterina Romanova ae7b82eaf8 Doxygen comments for prfchwintrin.h
Added doxygen comments to prfchwintrin.h's intrinsics. 

Note: The doxygen comments are automatically generated based on Sony's intrinsic
s document.

I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream.

llvm-svn: 293745
2017-02-01 07:37:40 +00:00
Anastasia Stulova d1f390ef99 [OpenCL] Diagnose write_only image3d when extension is disabled
Prior to OpenCL 2.0, image3d_t can only be used with the write_only
access qualifier when the cl_khr_3d_image_writes extension is enabled,
see e.g. OpenCL 1.1 s6.8b.

Require the extension for write_only image3d_t types and guard uses of
write_only image3d_t in the OpenCL header.

Patch by Sven van Haastregt!

Review: https://reviews.llvm.org/D28860
llvm-svn: 293050
2017-01-25 12:18:50 +00:00
Paul Robinson a363d14538 Guard __gnuc_va_list typedef.
Differential Revision: http://reviews.llvm.org/D28620

llvm-svn: 292819
2017-01-23 19:09:21 +00:00
Tim Shen 867be0d14c [Altivec] Change vec_sl to a << (b % (sizeof(a) * 8))
For a << b (as original vec_sl does), if b >= sizeof(a) * 8, the
behavior is undefined. However, Power instructions do define the
behavior, which is equivalent to a << (b % (sizeof(a) * 8)).

This patch changes altivec.h to use a << (b % (sizeof(a) * 8)), to
ensure the consistent semantic of the instructions. Then it combines
the generated multiple instructions back to a single shift.

This patch handles left shift only. Right shift, on the other hand, is
more complicated, considering arithematic/logical right shift.

Differential Revision: https://reviews.llvm.org/D28037

llvm-svn: 292659
2017-01-20 22:05:33 +00:00
Craig Topper 367c86ddbe [AVX-512] Replace subvector broadcast builtins with shufflevectors and selects.
Verified that the backend codegens this equally well.

llvm-svn: 292329
2017-01-18 02:17:10 +00:00
Ekaterina Romanova 2e041c9c20 [DOXYGEN] Documentation for the newly added x86 intrinsics.
Added doxygen comments for the newly added intrinsics in avxintrin.h, namely _mm256_cvtsd_f64, _mm256_cvtsi256_si32 and _mm256_cvtss_f32 

Added doxygen comments for the new intrinsics in emmintrin.h, namely _mm_loadu_si64 and _mm_load_sd.

Explicit parameter names were added for _mm_clflush and _mm_setcsr 

The rest of the changes are editorial, removing trailing spaces at the end of the lines.

Differential Revision: https://reviews.llvm.org/D28503

llvm-svn: 291876
2017-01-13 01:14:08 +00:00
Tony Jiang 974e4c7899 [PowerPC] Fix the wrong implementation of builtin vec_rlnm.
llvm-svn: 291702
2017-01-11 20:59:42 +00:00
Sean Fertile 96d9e0ec05 Add vec_insert4b and vec_extract4b functions to altivec.h
Add builtins for the functions and custom codegen mapping the builtins to their
corresponding intrinsics and handling the endian related swapping.

https://reviews.llvm.org/D26546

llvm-svn: 291179
2017-01-05 21:43:30 +00:00
Justin Lebar b8f7a3b8b1 [CUDA] Rename keywords used in macro so they don't conflict with MSVC.
Summary:
MSVC seems to use "__in" and "__out" for its own purposes, so we have to
pick different names in this macro.

Reviewers: tra

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D28325

llvm-svn: 291138
2017-01-05 16:54:11 +00:00
Justin Lebar 11d5116904 [CUDA] Don't define functions that the CUDA headers themselves define on Windows.
Reviewers: tra

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D28324

llvm-svn: 291137
2017-01-05 16:53:55 +00:00
Justin Lebar 1863d611f8 [Windows] Remove functions in intrin.h that are defined in Builtin.def.
Summary:
These duplicate declarations cause a problem for CUDA compiles on
Windows.  All implicitly-defined functions are host+device, and this
applies to the declarations in Builtin.def.  But then when we see the
declarations in intrin.h, they have no attributes, so are host-only
functions.  This is an error.

(A better fix might be to make these builtins host-only, but that is a
much bigger change.)

Reviewers: rnk

Subscribers: cfe-commits, echristo

Differential Revision: https://reviews.llvm.org/D28317

llvm-svn: 291128
2017-01-05 16:51:37 +00:00
Artem Belevich 60f25f70c8 [CUDA] Pre-include sm_60 and sm_61 headers.
CUDA-8.0 comes with new headers which nvcc pre-includes via cuda_runtime.h
Clang now makes them available as well.

Differential Revision: https://reviews.llvm.org/D28301

llvm-svn: 290982
2017-01-04 18:39:29 +00:00
Ekaterina Romanova c9ed514632 [DOXYGEN] Improved doxygen comments for xmmintrin.h intrinsics.
Added \n commands to insert a line breaks where necessary, since one long line of documentation is nearly unreadable.
Formatted comments to fit into 80 chars.
In some cases added \a command in front of the parameter names to display them in italics.

llvm-svn: 290619
2016-12-27 18:53:29 +00:00
Craig Topper 70536f4e47 [AVX-512] Replace masked 512-bit pmuldq and pmuludq builtins with the newly added unmasked versions and selects.
llvm-svn: 290580
2016-12-27 04:04:57 +00:00
Craig Topper 32866ab800 Revert r290574 "foo"
This was supposed to be merged with another commit with a real commit message. Sorry.

llvm-svn: 290579
2016-12-27 04:03:29 +00:00
Craig Topper c5ab78d4c3 Revert r290575 "[AVX-512] Replace masked 512-bit pmuldq and pmuludq builtins with the newly added unmasked versions and selects."
I failed to merge this with r290574.

llvm-svn: 290578
2016-12-27 04:03:25 +00:00
Craig Topper 6ad5bcc8ac [AVX-512] Replace masked 512-bit pmuldq and pmuludq builtins with the newly added unmasked versions and selects.
llvm-svn: 290575
2016-12-27 03:46:16 +00:00
Craig Topper 39b9e32493 foo
llvm-svn: 290574
2016-12-27 03:46:13 +00:00
Ekaterina Romanova dffe45b3e6 [DOXYGEN] Improved doxygen comments for x86 intrinsics.
Improved doxygen comments for the following intrinsics headers:  __wmmintrin_pclmul.h, bmiintrin.h, emmintrin.h, f16cintrin.h, immintrin.h, mmintrin.h, pmmintrin.h, tmmintrin.h

Added \n commands to insert a line breaks where necessary, since one long line of documentation is nearly unreadable.
Formatted comments to fit into 80 chars.
In some cases added \a command in front of the parameter names to display them in italics.

llvm-svn: 290561
2016-12-27 00:49:38 +00:00
Marina Yatsina c42fd03bf8 [inline-asm]No error for conflict between inputs\outputs and clobber list
According to extended asm syntax, a case where the clobber list includes a variable from the inputs or outputs should be an error - conflict.
for example:

const long double a = 0.0;
int main()
{

char b;
double t1 = a;
__asm__ ("fucompp": "=a" (b) : "u" (t1), "t" (t1) : "cc", "st", "st(1)");

return 0;
}

This should conflict with the output - t1 which is st, and st which is st aswell.
The patch fixes it.

Commit on behald of Ziv Izhar.

Differential Revision: https://reviews.llvm.org/D15075

llvm-svn: 290539
2016-12-26 12:23:42 +00:00
Ekaterina Romanova 16166a4d71 [DOXYGEN] Improved doxygen comments for tmmintrin.h intrinsics.
Added \n commands to insert a line breaks where necessary to make the documentation more readable. 
Formatted comments to fit into 80 chars.

llvm-svn: 290458
2016-12-23 23:36:26 +00:00
Ekaterina Romanova 6de0cd870b [DOXYGEN] Improved doxygen comments for tmmintrin.h intrinsics.
Tagged parameter names with \a doxygen command to display parameters in italics.
Added \n commands to insert a line break to make the documentation more readable. 
Formatted comments to fit into 80 chars.

llvm-svn: 290455
2016-12-23 22:47:16 +00:00
Yaxun Liu 5b74665a41 Recommit r289979 [OpenCL] Allow disabling types and declarations associated with extensions
Fixed undefined behavior due to cast integer to bool in initializer list.

llvm-svn: 290056
2016-12-18 05:18:55 +00:00
Yaxun Liu 35f6d66b0d Revert r289979 due to regressions
llvm-svn: 289991
2016-12-16 21:23:55 +00:00
Yaxun Liu 2e8331cab6 [OpenCL] Allow disabling types and declarations associated with extensions
Added a map to associate types and declarations with extensions.

Refactored existing diagnostic for disabled types associated with extensions and extended it to declarations for generic situation.

Fixed some bugs for types associated with extensions.

Allow users to use pragma to declare types and functions for supported extensions, e.g.

#pragma OPENCL EXTENSION the_new_extension_name : begin
// declare types and functions associated with the extension here
#pragma OPENCL EXTENSION the_new_extension_name : end

Differential Revision: https://reviews.llvm.org/D21698

llvm-svn: 289979
2016-12-16 19:22:08 +00:00
Bruno Cardoso Lopes 88458c31e7 Revert "[Headers] Add #include_next for tgmath.h on Darwin"
Reverts r289181: it's currently breaking modules using simd.h in
10.12 SDK.

This reverts commit 6e73e3464e96a4e00492c24aa790d36e1adb5702.

llvm-svn: 289487
2016-12-12 23:06:58 +00:00
Craig Topper 678b07fe3c [AVX-512] Remove masking from 512-bit vpermil builtins. The backend now has versions without masking so wrap it with select.
This will allow the backend to constant fold these to generic shuffle vectors like 128-bit and 256-bit without having to working about handling masking.

llvm-svn: 289351
2016-12-11 01:26:52 +00:00
Craig Topper cdd3603c04 [AVX-512] Remove masking from 512-bit pshufb builtin. The backend now has a version without masking so wrap it with select.
This will allow the backend to constant fold these to generic shuffle vectors like 128-bit and 256-bit without having to working about handling masking.

llvm-svn: 289345
2016-12-10 23:09:52 +00:00
Craig Topper 5391c98341 [AVX-512] Remove 128/256-bit masked vpermilvar builtins and replace with select and the avx unmasked builtins.
llvm-svn: 289338
2016-12-10 20:27:39 +00:00
Ekaterina Romanova 0c1c3bbc78 [DOXYGEN] Improved doxygen comments for x86 intrinsics headers.
Tagged instruction names with <c> INSTR_NAME </c> to display them in typewriter font.

In the past, \c command was used, unfortunately it applied to only one word. 
<c> .. </c> has the same meaning, but applies to all words in between the tags.

llvm-svn: 289249
2016-12-09 18:35:50 +00:00
Bruno Cardoso Lopes 052e6ddf27 [Headers] Add #include_next for tgmath.h on Darwin
Allow darwin to provide additional definitions and implementation
specifc values for tgmath.h on Apple platforms.

rdar://problem/19019845

llvm-svn: 289181
2016-12-09 03:30:46 +00:00
Ekaterina Romanova 08da283295 [DOXYGEN] Improved doxygen comments for xmmintrin.h intrinsics.
Tagged parameter names with \a doxygen command to display parameters in italics.
Formatted comments to fit into 80 chars.

llvm-svn: 289159
2016-12-08 23:58:39 +00:00
Ekaterina Romanova 3494a597e9 [DOXYGEN] Improved doxygen comments.
Improved doxygen comments for fxsrintrin.h and mmintrin.h intrinsics by taagging parameter names with \a doxygen command to display parameters in italics.

Formatted comments to fit into 80 chars.

llvm-svn: 289154
2016-12-08 23:32:07 +00:00
Ekaterina Romanova 797b0ebf2d [DOXYGEN] Improved doxygen comments for emmintrin.h intrinsics.
Tagged parameter names with \a doxygen command to display parameters in italics.
Formatted comments to fit into 80 chars.

llvm-svn: 289116
2016-12-08 22:10:51 +00:00
Ekaterina Romanova a8fde7ce8b [DOXYGEN] Improved doxygen comments.
Improved doxygen comments for __wmmintrin_pclmul.h and ammintrin.h intrinsics by taagging parameter names with \a doxygen command to display parameters in italics.

Formatted comments to fit into 80 chars.

llvm-svn: 289083
2016-12-08 17:57:23 +00:00
Ekaterina Romanova d6042197db [DOXYGEN] Improved doxygen comments for avxintrin.h intrinsics.
Tagged parameter names with \a doxygen command to display them in italics.
Formatted comments to fit into 80 chars.

llvm-svn: 289022
2016-12-08 04:09:17 +00:00
Bruno Cardoso Lopes d93779da15 [Headers] Enable #include_next<float.h> on Darwin
Allows darwin targets to provide additional definitions and
implementation specifc values for float.h

rdar://problem/21961491

llvm-svn: 289018
2016-12-08 02:13:56 +00:00
Ekaterina Romanova 4c77e8940e [DOXYGEN] Updated instruction names corresponding to avxintrin.h intrinsics.
Documentation for some of the avxintrin.h's intrinsics errorneously said that
non VEX-prefixed instructions could be generated. This was fixed.

I tried several different solutions to achieve pretty printing of unordered lists (nested and non-nested) in param sections in doxygen. 

llvm-svn: 287990
2016-11-26 19:38:19 +00:00
Ehsan Amiri 85f5bfcf0d [PPC] support for arithmetic builtins in the FE
(commit again after fixing the buildbot failures)
This adds various overloads of the following builtins to altivec.h:

    vec_neg
    vec_nabs
    vec_adde
    vec_addec
    vec_sube
    vec_subec
    vec_subc

Note that for vec_sub builtins on 32 bit integers, the semantics is similar to
what ISA describes for instructions like vsubecuq that work on quadwords: the
first operand is added to the one's complement of the second operand. (As
opposed to two's complement which I expected).

llvm-svn: 287872
2016-11-24 12:40:04 +00:00
Ehsan Amiri 9cce1ee88c [PPC] revert r287795
A test that passed locally is failing on one of the build bots.

llvm-svn: 287796
2016-11-23 18:55:17 +00:00
Ehsan Amiri 9b91cfa0b0 [PPC] support for arithmetic builtins in the FE
(commit again after fixing the buildbot failures)
This adds various overloads of the following builtins to altivec.h:

    vec_neg
    vec_nabs
    vec_adde
    vec_addec
    vec_sube
    vec_subec
    vec_subc

Note that for vec_sub builtins on 32 bit integers, the semantics is similar to
what ISA describes for instructions like vsubecuq that work on quadwords: the
first operand is added to the one's complement of the second operand. (As
opposed to two's complement which I expected).

llvm-svn: 287795
2016-11-23 18:36:29 +00:00
Ehsan Amiri ac10595b0d [PPC] Reverting r287772
Due to buildbot failure, I revert. Will recommit after investigation.

llvm-svn: 287775
2016-11-23 16:56:03 +00:00
Ehsan Amiri 5ea1054dab [PPC] support for arithmetic builtins in the FE
This adds various overloads of the following builtins to altivec.h:

    vec_neg
    vec_nabs
    vec_adde
    vec_addec
    vec_sube
    vec_subec
    vec_subc

Note that for vec_sub builtins on 32 bit integers, the semantics is similar to
what ISA describes for instructions like vsubecuq that work on quadwords: the
first operand is added to the one's complement of the second operand. (As
opposed to two's complement which I expected).

llvm-svn: 287772
2016-11-23 16:32:05 +00:00
Craig Topper 6aefe00ccf [X86] Replace valignd/q builtins with appropriate __builtin_shufflevector.
llvm-svn: 287733
2016-11-23 01:47:12 +00:00
Ekaterina Romanova bf667b21ac Add doxygen comments to immintrin.h's intrinsics.
The doxygen comments are automatically generated based on Sony's intrinsics docu
ment.

I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream. This patch was internally reviewed by Charles Li.

llvm-svn: 287483
2016-11-20 08:35:05 +00:00
Ekaterina Romanova 0a70076121 Doxygen comments for avxintrin.h.
Added doxygen comments to avxintrin.h's intrinsics. As of now, all the intrinsics in this file that were documented by Sony's intrinsics guide should have corresponding doxygen comments.

Note: The doxygen comments are automatically generated based on Sony's intrinsic
s document.

I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream.

Reviewed by Wolfgang Pieb.

llvm-svn: 287436
2016-11-19 04:59:08 +00:00
Ekaterina Romanova 06b1914cb7 Add doxygen comments for lzcntintrin.h's intrinsics.
The doxygen comments are automatically generated based on Sony's intrinsics document.

I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream. This patch was internally reviewed by Charles Li.

llvm-svn: 287317
2016-11-18 06:26:01 +00:00
Craig Topper 37bf5c6a3f [AVX-512] Replace masked 16-bit element variable shift builtins with new unmasked versions and selects.
llvm-svn: 287313
2016-11-18 05:04:51 +00:00
Ekaterina Romanova 53088dd44d Add doxygen comments to fxsrintrin.h's intrinsics.
The doxygen comments are automatically generated based on Sony's intrinsics document.

I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream. This patch was internally reviewed by Paul Robinson and Charles Li.

llvm-svn: 287295
2016-11-18 01:42:01 +00:00
Justin Lebar 50fe985349 [CUDA] Wrapper header changes necessary to support MacOS.
Reviewers: tra

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D26780

llvm-svn: 287288
2016-11-18 00:41:35 +00:00
Ekaterina Romanova 2174b6fe72 Minor changes in x86 intrinsics headers; NFC
I made several changes for consistency with the rest of x86 instrinsics header files. Some of these changes help to render doxygen comments better.

1. avxintrin.h –  Moved the opening bracket on a separate line for several 
                  intrinsics (for consistency with the rest of the intrinsics).

2. emmintrin.h -  Moved the doxygen comment next to the body of the function;
               -  Added braces after extern "C"  even though there is only 
                  one declaration each time

3. xmmintrin.h -  Moved the doxygen comment next to the body of the function;
               -  Added intrinsic prototypes for a couple of macro definitions
                  into the doxygen comment;
               -  Added braces after extern "C"  even though there is only one
                  declaration each time

4. ammintrin.h –  Removed extra line between the doxygen comment and the body
                  of the functions (for consistency with the rest of the files).

Desk reviewed by Paul Robinson.

llvm-svn: 287278
2016-11-17 23:02:00 +00:00
Simon Pilgrim 698528d83b [X86][AVX512] Replace lossless i32/u32 to f64 conversion intrinsics with generic IR
Both the (V)CVTDQ2PD (i32 to f64) and (V)CVTUDQ2PD (u32 to f64) conversion instructions are lossless and can be safely represented as generic __builtin_convertvector calls instead of x86 intrinsics without affecting final codegen.

This patch removes the clang builtins and their use in the headers - a future patch will deal with removing the llvm intrinsics.

This is an extension patch to D20528 which dealt with the equivalent sse/avx cases.

Differential Revision: https://reviews.llvm.org/D26686

llvm-svn: 287088
2016-11-16 09:27:40 +00:00
Zaara Syeda c1d2952388 vector load store with length (left justified) clang portion
llvm-svn: 286994
2016-11-15 18:04:13 +00:00
Zaara Syeda 56fa12c5a3 test commmit
llvm-svn: 286977
2016-11-15 15:57:33 +00:00
Tony Jiang 6a49aad177 [PowerPC] Implement BE VSX load/store builtins - clang portion.
This patch implements all the overloads for vec_xl_be and vec_xst_be. On BE,
they behaves exactly the same with vec_xl and vec_xst, therefore they are
simply implemented by defining a matching macro. On LE, they are implemented
by defining new builtins and intrinsics. For int/float/long long/double, it
is just a load (lxvw4x/lxvd2x) or store(stxvw4x/stxvd2x). For char/char/short,
we also need some extra shuffling before or after call the builtins to get the
desired BE order. For int128, simply call vec_xl or vec_xst.

llvm-svn: 286971
2016-11-15 14:30:56 +00:00
Sean Fertile a9548937d6 [PPC] altivec.h functions for converting half precision to single precision.
Adds 2 vector functions for converting from a vector of unsigned short to a
vector of float. One converts the low 4 halfwords and one converts the high
4 halfwords.

Differential Revision: https://reviews.llvm.org/D26534

llvm-svn: 286863
2016-11-14 18:47:15 +00:00
Sean Fertile 193430fe51 [PPC] add extract sig/exp test data class for vec float and vec double.
Add vector extract exponent/significand functions to altivec.h, as well as
 functions (and related constants) to test the data class of vector float
 and vector double.

 Differential Revision: https://reviews.llvm.org/D26271

llvm-svn: 286830
2016-11-14 14:43:27 +00:00
Craig Topper 5e0709d60b [AVX-512] Replace masked dword and qword variable shift builtins with unmasked builtins and a select.
This is part of a set of changes to allow InstCombine in the backend to optimize variable shifts without having to know about masking.

llvm-svn: 286757
2016-11-13 07:26:34 +00:00
Craig Topper d7e5b21914 [X86] Remove extra escaped new lines in intrinsic headers left over from an earlier conversion away from a macro. NFC
llvm-svn: 286756
2016-11-13 07:26:31 +00:00
Craig Topper 298aa12b63 [AVX-512] Add returns to shift intrinsics that converted from macros in r286714.
llvm-svn: 286738
2016-11-13 00:35:01 +00:00
Craig Topper 2c8f49e67b [AVX-512] Use scalar vfmsub/vfnmsub mask3 intrinsics instead of inverting the mask argument of a vfmadd intrinsic.
Summary: Inverting the mask argument does not reflect the intended semantics of the intrinsic.

Reviewers: igorb, delena

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D26019

llvm-svn: 286733
2016-11-12 23:24:34 +00:00
Craig Topper 1a44193afd [AVX-512] Convert the rest of the masked shift by immediate and by single element builtins over to the newly added unmasked builtins and a select.
This should also fix PR30691 since the new builtins are handled like the legacy builtins in the backend.

llvm-svn: 286714
2016-11-12 07:16:59 +00:00
Nemanja Ivanovic 4de0011b5c [PowerPC] Implement remaining permute builtins in altivec.h - Clang portion
This patch corresponds to review:
https://reviews.llvm.org/D26479

It adds the remaining vector permute/rotate builtins to altivec.h.

llvm-svn: 286650
2016-11-11 22:34:44 +00:00
Nemanja Ivanovic 4079fc8188 [PowerPC] Add vector conversion builtins to altivec.h - clang portion
This patch corresponds to review:
https://reviews.llvm.org/D26308

It adds a number of vector type conversion builtins to altivec.h.

llvm-svn: 286627
2016-11-11 19:56:17 +00:00
Tony Jiang 7723f97d6a [PowerPC] Implement plain VSX load/store builtins.
Implement all the different 24 overloads for vec_xl and vec_xst.

llvm-svn: 286455
2016-11-10 14:39:56 +00:00
Ekaterina Romanova 64adc38e51 Doxygen comments for avxintrin.h.
Added doxygen comments to avxintrin.h's intrinsics. As of now, around 75% of the
intrinsics in this file are documented here. The patches for the other 25% will be se
nt out later.

Removed extra spaces in emmitrin.h.

Note: The doxygen comments are automatically generated based on Sony's intrinsics document.

I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream.

llvm-svn: 286336
2016-11-09 03:58:30 +00:00
Ayman Musa e60a41ca28 [X86][AVX512][Clang] Add support for mask_{move|store|load}_s{s/d} and int2mask/mask2int intrinsics.
Differential Revision: https://reviews.llvm.org/D26021

llvm-svn: 286229
2016-11-08 12:00:30 +00:00
Tony Jiang c6ddd7221c [PowerPC] Implement remaining vector comparison builtins.
vector bool char vec_cmpeq (vector bool char, vector bool char);
vector bool int vec_cmpeq (vector bool int, vector bool int);
vector bool long long vec_cmpeq (vector bool long long, vector bool long lon
vector bool short vec_cmpeq (vector bool short, vector bool short);

llvm-svn: 286205
2016-11-08 04:15:45 +00:00
Yaxun Liu 7d07ae7c85 [OpenCL] Mark group functions as convergent in opencl-c.h
Certain OpenCL builtin functions are supposed to be executed by all threads in a work group or sub group. Such functions should not be made divergent during transformation. It makes sense to mark them with convergent attribute.

The adding of convergent attribute is based on Ettore Speziale's work and the original proposal and patch can be found at https://www.mail-archive.com/cfe-commits@lists.llvm.org/msg22271.html.

Differential Revision: https://reviews.llvm.org/D25343

llvm-svn: 285725
2016-11-01 18:45:32 +00:00
Nemanja Ivanovic 05ce4ca0dd [PowerPC] Implement vector shift builtins - clang portion
This patch corresponds to review https://reviews.llvm.org/D26092.
Committing on behalf of Tony Jiang.

llvm-svn: 285694
2016-11-01 14:46:20 +00:00
Nemanja Ivanovic 251f6dd93d [PPC] Add vec_absd functions to altivec.h
This patch corresponds to review https://reviews.llvm.org/D26073.
Committing on behalf of Sean Fertile.

llvm-svn: 285679
2016-11-01 08:39:56 +00:00
Craig Topper 08bf53ffda [AVX-512] Remove masked vector insert builtins and replace with native shufflevectors and selects.
Unfortunately, the backend currently doesn't fold masks into the instructions correctly when they come from these shufflevectors. I'll work on that in a future commit.

llvm-svn: 285667
2016-11-01 05:47:56 +00:00
Craig Topper 350729627a [AVX-512] Use selectd instead of selectps for _mm256_mask_extracti32x4_epi32.
llvm-svn: 285545
2016-10-31 05:49:11 +00:00
Craig Topper 93ffabd28d [AVX-512] Remove masked vector extract builtins and replace with native shufflevectors and selects.
Unfortunately, the backend currently doesn't fold masks into the instructions correctly when they come from these shufflevectors. I'll work on that in a future commit.

llvm-svn: 285540
2016-10-31 04:30:56 +00:00
Craig Topper 66b2fd1209 [AVX-512] Remove many of the masked 128/256-bit shift builtins and replace them with unmasked builtins and selects.
llvm-svn: 285539
2016-10-31 04:30:51 +00:00
Michael Zuckerman d343697f1e Fixing "type" issue for (epi32)
and replaceing hardcoded inf with clang builtin inf "__builtin_inff()" for float ({max|min}_{pd|ps})

llvm-svn: 285519
2016-10-30 14:54:05 +00:00
Craig Topper 312ff9d19d [AVX-512] Remove masked 128/256-bit builtins for vpmaddwd and vpmaddubsw. Replace with unmasked builtins and select.
llvm-svn: 285516
2016-10-30 07:11:34 +00:00
Craig Topper 4caf76bee2 [AVX-512] Remove 128/256-bit masked pmulhrsw/pmulhuw/pmulhw builtins and use unmasked builtins and select instead.
llvm-svn: 285505
2016-10-29 19:02:14 +00:00
Craig Topper 2eadf1b67e [AVX-512] Remove masked 128/256-bit sqrt builtins and replace them with unmasked builtins and a select.
llvm-svn: 285504
2016-10-29 19:02:10 +00:00
Craig Topper 09e94007be [AVX-512] Remove masked 128/256-bit pmuludq/pmuldq builtins and replace them with unmasked builtins and a select.
llvm-svn: 285503
2016-10-29 19:02:07 +00:00
Craig Topper 160ca8420d [AVX-512] Remove masked 128/256-bit floating point max/min builtins. Use unmasked builtins with select instead.
llvm-svn: 285502
2016-10-29 19:02:03 +00:00
Michael Zuckerman 25eb420233 [X86][AVX512][Clang][Intrinsics][reduce] Adding missing reduce (max|min) intrinsics to Clang .
After LGTM and Check-all 

Vector-reduction arithmetic accepts vectors as inputs and produces 
scalars as outputs.This class of vector operation forms the basis 
of many scientific computations. In vector-reduction arithmetic, 
the evaluation off is independent of the order of the input elements of V.

Reviewer: 1. craig.topper 
          2. igorb

Differential Revision: https://reviews.llvm.org/D25988

llvm-svn: 285493
2016-10-29 10:29:20 +00:00
Nemanja Ivanovic 931bc548e6 [PPC] add float and double overloads for vec_orc and vec_nand in altivec.h
This patch corresponds to review https://reviews.llvm.org/D25950.
Committing on behalf of Sean Fertile.

llvm-svn: 285439
2016-10-28 20:04:53 +00:00
Nemanja Ivanovic 4f69f924df Implement vector count leading/trailing bytes with zero lsb and vector parity
builtins - clang portion

This patch corresponds to review: https://reviews.llvm.org/D26002
Committing on behalf of Zaara Syeda.

llvm-svn: 285436
2016-10-28 19:49:03 +00:00
Michael Zuckerman edd99eb07a 1. Fixing small types issue (PD|PS) (reduce) .
2. Cosmetic changes

llvm-svn: 285405
2016-10-28 15:16:03 +00:00
Anastasia Stulova 7c30533362 [OpenCL] Diagnose variadic arguments
OpenCL disallows using variadic arguments (s6.9.e and s6.12.5 OpenCL v2.0)
apart from some exceptions:
- printf
- enqueue_kernel

This change adds error diagnostic for variadic functions but accepts printf
and any compiler internal function (which should cover __enqueue_kernel_XXX cases).

It also unifies diagnostic with block prototype and adds missing uncaught cases for blocks.

llvm-svn: 285395
2016-10-28 12:59:39 +00:00
Nemanja Ivanovic 09dd423a7d [PPC] add vector byte reverse functions to altivec.h
This patch corresponds to review https://reviews.llvm.org/D25915.
Committing on behalf of Sean Fertile.

llvm-svn: 285268
2016-10-27 06:23:57 +00:00
Justin Lebar ebeeab87a1 [CUDA] Move device placement new definitions into a wrapper header.
Previously, these were always included -- after this change, you have to
 #include <new>, which is consistent with how things ought to work.

llvm-svn: 285251
2016-10-26 22:13:26 +00:00
Justin Lebar 6f5ec7ee88 [CUDA] Switch cuda_wrappers/complex to use a proper include guard instead of #pragma once.
This is consistent with the rest of our internal headers.

llvm-svn: 285250
2016-10-26 22:13:20 +00:00
Nemanja Ivanovic 3de0a385c9 [PowerPC] Implement vector_insert_exp builtins - clang portion
This patch corresponds to review https://reviews.llvm.org/D25956.
Committing on behalf of Zaara Syeda.

llvm-svn: 285229
2016-10-26 19:27:11 +00:00
Nemanja Ivanovic 85a28dcc5d [PPC] Implement vector reverse elements builtins (vec_reve)
This patch corresponds to review https://reviews.llvm.org/D25906.
Committing on behalf of Tony Jiang.

llvm-svn: 285218
2016-10-26 18:25:45 +00:00
Craig Topper f202365910 [AVX-512] Fix the operand order for all calls to __builtin_ia32_vfmaddss3_mask.
Summary: The preserved input should be the first argument and the vector inputs should be in the same order as the intrinsics it is used to implement.

Reviewers: igorb, delena

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D25902

llvm-svn: 285175
2016-10-26 05:35:38 +00:00
Yaxun Liu a49bd14843 [OpenCL] Add missing atom_xor for 64 bit to opencl-c.h
Differential Revision: https://reviews.llvm.org/D25954

llvm-svn: 285125
2016-10-25 21:37:05 +00:00
Michael Zuckerman facb37cabf [X86][AVX512][Clang][Intrinsics][reduce] Adding missing reduce (Operators: +,*,&&,||) intrinsics to Clang
Committed after LGTM and check-all

 
Vector-reduction arithmetic accepts vectors as inputs and produces scalars as outputs.
This class of vector operation forms the basis of many scientific computations.
In vector-reduction arithmetic, the evaluation off is independent of the order of the input elements of V.
 
Used bisection method. At each step, we partition the vector with previous
step in half, and the operation is performed on its two halves.
This takes log2(n) steps where n is the number of elements in the vector.
 
Reviwer: 1. igorb
         2. craig.topper    
Differential Revision: https://reviews.llvm.org/D25527

llvm-svn: 285054
2016-10-25 07:56:04 +00:00
Michael Zuckerman 33bd5b235b revert r284963
because new test file is failing in some OS.
test/CodeGen/avx512-reduceIntrin.c

llvm-svn: 284967
2016-10-24 11:30:23 +00:00
Michael Zuckerman 98cb041891 [X86][AVX512][Clang][Intrinsics][reduce] Adding missing reduce (Operators: +,*,&&,||) intrinsics to Clang
Committed after LGTM and check-all

Vector-reduction arithmetic accepts vectors as inputs and produces scalars as outputs.
This class of vector operation forms the basis of many scientific computations.
In vector-reduction arithmetic, the evaluation off is independent of the order of the input elements of V.

Used bisection method. At each step, we partition the vector with previous
step in half, and the operation is performed on its two halves.
This takes log2(n) steps where n is the number of elements in the vector.

Differential Revision: https://reviews.llvm.org/D25527

llvm-svn: 284963
2016-10-24 10:53:20 +00:00
Craig Topper eee7c0520c [AVX-512] Replace masked 128/256-bit byte, word, and dword min/max builtins with selects and the older unmasked builtins.
llvm-svn: 284954
2016-10-23 23:57:30 +00:00
Craig Topper 0c5da26572 [AVX-512] Replace 512-bit pmovzx/sx builtins with native IR.
llvm-svn: 284936
2016-10-23 07:35:47 +00:00
Craig Topper 4ef879ac2c [AVX-512] Remove masked 128/256-bit packss/packus builtins and replace with selects and the older unmasked builtins.
llvm-svn: 284935
2016-10-23 07:35:39 +00:00
Ekaterina Romanova 06477bf035 Add more doxygen comments to emmintrin.h's intrinsics.
With this patch, all intrinsics in this file (with an exception of a handful of a recently added ones) will be documented. I will send out a patch for 4 missining intrisics later.

The doxygen comments are automatically generated based on Sony's intrinsics document.

I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream. This patch was internally reviewed by Yunzhong Gao.

llvm-svn: 284934
2016-10-23 07:30:50 +00:00
Craig Topper 4d63dfc286 [AVX-512] Replace masked 128/256-bit pavg builtins and replace with select and older unmasked builtins.
llvm-svn: 284929
2016-10-22 21:24:56 +00:00
Craig Topper 622c63614d [AVX-512] Replace masked 128/256-bit saturating add/sub builtins with select and older unmasked builtins.
llvm-svn: 284928
2016-10-22 21:24:52 +00:00
Craig Topper 11dda92405 [AVX-512] Replace masked 128/256-bit vpmovzx/vpmovsx builtins with native IR.
llvm-svn: 284927
2016-10-22 21:24:48 +00:00
Craig Topper eb1c0afa90 [AVX-512] Remove masked 128/256-bit pshufb builtins. Replace with a select and the older unmaksed builtins.
llvm-svn: 284925
2016-10-22 21:24:42 +00:00
Craig Topper 78a9c40326 [AVX-512] Remove builtins for 128/256-bit pabsb/pabsw. We can use a select and the older non-masked versions instead.
llvm-svn: 284924
2016-10-22 21:24:38 +00:00
Craig Topper c2c7e42bfe [AVX-512] Add typecasts to alignr intrinsics that were modified in r284920.
llvm-svn: 284923
2016-10-22 21:24:34 +00:00
Craig Topper f6373bc6fd [AVX-512] Remove masked 128/256-bit palignr builtins. We can just use a select in the header file with the older unmasked versions instead.
llvm-svn: 284920
2016-10-22 18:32:33 +00:00
Ekaterina Romanova 493091fdef Add more doxygen comments to emmintrin.h's intrinsics.
With this patch, 75% of the intrinsics in this file will be documented now. The patches for the rest of the intrisics in this file will be send out later.

The doxygen comments are automatically generated based on Sony's intrinsics document.

I got an OK from Eric Christopher to commit doxygen comments without prior code review upstream. This patch was internally reviewed by Yunzhong Gao.

llvm-svn: 284754
2016-10-20 17:59:15 +00:00
Albert Gutowski 1deab38717 Implement __stosb intrinsic as a volatile memset
Summary: We need `__stosb` to be an intrinsic, because SecureZeroMemory function uses it without including intrin.h. Implementing it as a volatile memset is not consistent with MSDN specification, but it gives us target-independent IR while keeping the most important properties of `__stosb`.

Reviewers: rnk, hans, thakis, majnemer

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D25334

llvm-svn: 284253
2016-10-14 17:33:05 +00:00
Albert Gutowski 5e08df0266 Add 64-bit MS _Interlocked functions as builtins again
Summary: Previously global 64-bit versions of _Interlocked functions broke buildbots on i386, so now I'm adding them as builtins for x86-64 and ARM only (should they be also on AArch64? I had problems with testing it for AArch64, so I left it)

Reviewers: hans, majnemer, mstorsjo, rnk

Subscribers: cfe-commits, aemerson

Differential Revision: https://reviews.llvm.org/D25576

llvm-svn: 284172
2016-10-13 22:35:07 +00:00
Albert Gutowski 397d81bb9a Implement MS _ReturnAddress and _AddressOfReturnAddress intrinsics
Reviewers: rnk, thakis, majnemer, hans

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D25540

llvm-svn: 284131
2016-10-13 16:03:42 +00:00
Yunzhong Gao d9fa56a4fb [NFC] Fixing the description for _mm_store_ps and _mm_store_ps1.
It seems that the doxygen description of these two intrinsics were swapped by
mistake.

llvm-svn: 284080
2016-10-12 23:27:27 +00:00
Albert Gutowski 2a0621e58a Implement MS _BitScan intrinsics
Summary: _BitScan intrinsics (and some others, for example _Interlocked and _bittest) are supposed to work on both ARM and x86. This is an attempt to isolate them, avoiding repeating their code or writing separate function for each builtin.

Reviewers: hans, thakis, rnk, majnemer

Subscribers: RKSimon, cfe-commits, aemerson

Differential Revision: https://reviews.llvm.org/D25264

llvm-svn: 284060
2016-10-12 22:01:05 +00:00
Yunzhong Gao c37e2231ad [NFC] Trial change to remove a redundant blank line.
llvm-svn: 284033
2016-10-12 19:33:33 +00:00
Justin Lebar 49ec14692a [CUDA] Re-land support for <complex> (r283683 and r283680).
These were reverted in r283753 and r283747.

The first patch added a header to the root 'Headers' install directory,
instead of into 'Headers/cuda_wrappers'.  This was fixed in the second
patch, but by then the damage was done: The bad header stayed in the
'Headers' directory, continuing to break the build.

We reverted both patches in an attempt to fix things, but that still
didn't get rid of the header, so the Windows boostrap build remained
broken.

It's probably worth fixing up our cmake logic to remove things from the
install dirs, but in the meantime, re-land these patches, since we
believe they no longer have this bug.

llvm-svn: 283907
2016-10-11 17:36:03 +00:00
Albert Gutowski fcea61c563 Implement MS read/write barriers and __faststorefence intrinsic
Reviewers: hans, rnk, majnemer

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D25442

llvm-svn: 283793
2016-10-10 19:40:51 +00:00
Albert Gutowski 7216f17653 Implement __emul, __emulu, _mul128 and _umul128 MS intrinsics
Reviewers: rnk, thakis, majnemer, hans

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D25353

llvm-svn: 283785
2016-10-10 18:09:27 +00:00
Nico Weber 21b9c7a6dc Revert r283683 because r283680 got reverted.
llvm-svn: 283753
2016-10-10 14:20:35 +00:00
Nico Weber 67dd74ef89 Revert r283680.
Breaks bootstrap builds on (at least) Windows:
In file included from D:\buildslave\clang-x64-ninja-win7\llvm\lib\Support\Allocator.cpp:14:
In file included from D:\buildslave\clang-x64-ninja-win7\llvm\include\llvm/Support/Allocator.h:24:
In file included from D:\buildslave\clang-x64-ninja-win7\llvm\include\llvm/ADT/SmallVector.h:20:
In file included from D:\buildslave\clang-x64-ninja-win7\llvm\include\llvm/Support/MathExtras.h:19:
D:\buildslave\clang-x64-ninja-win7\stage1.install\bin\..\lib\clang\4.0.0\include\algorithm(63,8) :
    error: unknown type name '__device__'
    inline __device__ const __T &

llvm-svn: 283747
2016-10-10 14:10:00 +00:00
Justin Lebar 3b593f56fc [CUDA] Don't install cuda_wrappers/{algorithm,complex} into the main include dir.
This is obviously wrong -- if we do this, then all compiles will pick up
these wrappers, which is not what we want.

llvm-svn: 283683
2016-10-09 00:27:39 +00:00
Justin Lebar d3c5d2a4de [CUDA] Support <complex> and std::min/max on the device.
Summary:
We do this by wrapping <complex> and <algorithm>.

Tests are in the test-suite.

Reviewers: tra

Subscribers: jhen, beanz, cfe-commits, mgorny

Differential Revision: https://reviews.llvm.org/D24979

llvm-svn: 283680
2016-10-08 22:16:12 +00:00
Justin Lebar 2dfbe9a3b4 [CUDA] Rename cuda_builtin_vars.h to __clang_cuda_builtin_vars.h.
Summary: This matches the idiom we use for our other CUDA wrapper headers.

Reviewers: tra

Subscribers: beanz, mgorny, cfe-commits

Differential Revision: https://reviews.llvm.org/D24978

llvm-svn: 283679
2016-10-08 22:16:08 +00:00
Justin Lebar e9eb792a0f [CUDA] Declare our __device__ math functions in the same inline namespace as our standard library.
Summary:
Currently we declare our inline __device__ math functions in namespace
std.  But libstdc++ and libc++ declare these functions in an inline
namespace inside namespace std.  We need to match this because, in a
later patch, we want to get e.g. <complex> to use our device overloads,
and it only will if those overloads are in the right inline namespace.

Reviewers: tra

Subscribers: cfe-commits, jhen

Differential Revision: https://reviews.llvm.org/D24977

llvm-svn: 283678
2016-10-08 22:16:03 +00:00
Michael Zuckerman 9e43ccfe68 [Clang][AVX512][BuiltIn]Adding missing intrinsics move_{sd|ss} to clang
Differential Revision: http://reviews.llvm.org/D21021

llvm-svn: 283314
2016-10-05 12:56:06 +00:00
Albert Gutowski f3a0bce155 Separate builtins for x84-64 and i386; implement __mulh and __umulh
Summary: We need x86-64-specific builtins if we want to implement some of the MS intrinsics - winnt.h contains definitions of some functions for i386, but not for x86-64 (for example _InterlockedOr64), which means that we cannot treat them as builtins for both i386 and x86-64, because then we have definitions of builtin functions in winnt.h on i386.

Reviewers: thakis, majnemer, hans, rnk

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D24598

llvm-svn: 283264
2016-10-04 22:29:49 +00:00
Craig Topper c4a8228bcc [AVX-512] Use native IR for masked 512-bit add/sub/mul/div ps/pd intrinsics when rounding mode isn't used.
llvm-svn: 283073
2016-10-02 17:43:00 +00:00
Artem Belevich d4d9dc8252 [CUDA] Added support for CUDA-8
Differential Revision: https://reviews.llvm.org/D24946

llvm-svn: 282610
2016-09-28 17:47:40 +00:00
Martin Storsjo 963f75efc2 [Headers] Replace stray indentation with tabs with spaces. NFC.
This matches the rest of the surrounding file.

llvm-svn: 282569
2016-09-28 09:34:51 +00:00
Ayman Musa 17a2819b05 Update to commit r282488, fix the buildboot failure.
llvm-svn: 282492
2016-09-27 15:37:31 +00:00
Ayman Musa 2e250e8845 [avx512] Add aliases to some missing avx512 intrinsics.
Differential Revision:https: //reviews.llvm.org/D24961

llvm-svn: 282488
2016-09-27 14:06:32 +00:00
Nemanja Ivanovic 10e2b5dcaa [Power9] Builtins for ELF v.2 ABI conformance - front end portion
This patch corresponds to review:
https://reviews.llvm.org/D24397

It adds the __POWER9_VECTOR__ macro and the -mpower9-vector option along with
a number of altivec.h functions (refer to the code review for a list).

llvm-svn: 282481
2016-09-27 10:45:22 +00:00
Saleem Abdulrasool eae64f8a62 headers: add missing Windows ARM Interlocked intrinsics
On ARM, there are multiple versions of each of the intrinsics, with
acquire/relaxed/release barrier semantics.

The newly added ones are provided as inline functions here instead of builtins,
since they should only be available on certain archs (arm/aarch64).

This is necessary in order to compile C++ code for ARM in MSVC mode.

Patch by Martin Storsjö!

llvm-svn: 282447
2016-09-26 22:12:43 +00:00
Simon Dardis 3d9c763816 [mips] MSA intrinsics header file
This patch adds the msa.h header file containing the shorter names for the
MSA instrinsics, e.g. msa_sll_b for builtin_msa_sll_b.

Reviewers: vkalintiris, zoran.jovanovic

Differential Review: https://reviews.llvm.org/D24674

llvm-svn: 281975
2016-09-20 15:07:36 +00:00
Justin Lebar e3612a039f [CUDA] Make __clang_cuda_cmath.h compatible with libc++.
Summary:
We need to add a bunch more "using"s, which weren't necessary with
libstdc++.

Once this is in I can check in a test to the test-suite.

Reviewers: tra

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D24588

llvm-svn: 281544
2016-09-14 21:50:14 +00:00
Albert Gutowski 727ab8a803 Add some MS aliases for existing intrinsics
Reviewers: thakis, compnerd, majnemer, rsmith, rnk

Subscribers: alexshap, cfe-commits

Differential Revision: https://reviews.llvm.org/D24330

llvm-svn: 281540
2016-09-14 21:19:43 +00:00
Albert Gutowski fc19fa3721 Temporary fix for MS _Interlocked intrinsics
llvm-svn: 281401
2016-09-13 21:51:37 +00:00
Albert Gutowski 9918cb6573 Reverse commit 281375 (breaks building Chromium)
llvm-svn: 281399
2016-09-13 21:24:51 +00:00
Albert Gutowski ce7a9a47b2 Add bunch of _Interlocked builtins
Reviewers: compnerd, thakis, Prazek, majnemer, rnk

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D24153

llvm-svn: 281378
2016-09-13 19:43:33 +00:00
Albert Gutowski ae3fb3113f Add some MS aliases for existing intrinsics
Reviewers: thakis, compnerd, majnemer, rsmith, rnk

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D24330

llvm-svn: 281375
2016-09-13 19:26:42 +00:00
Albert Gutowski b6a11acb53 Implement MS _rot intrinsics
Reviewers: thakis, Prazek, compnerd, rnk

Subscribers: majnemer, cfe-commits

Differential Revision: https://reviews.llvm.org/D24311

llvm-svn: 280997
2016-09-08 22:32:19 +00:00
Reid Kleckner 5de2bcdcf6 Add MS __nop intrinsic to intrin.h
Summary: There was no definition for __nop function - added inline
assembly.

Patch by Albert Gutowski!

Reviewers: rnk, thakis

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D24286

llvm-svn: 280826
2016-09-07 16:55:12 +00:00
Craig Topper 2dfab63bb3 [AVX-512] Remove 128-bit and 256-bit masked floating point add/sub/mul/div builtins and replace with native operations.
We can't do the 512-bit ones because they take a rounding mode argument that we can't represent.

llvm-svn: 280635
2016-09-04 18:30:17 +00:00
Elad Cohen fb6358d2b5 [Modules] Add 'freestanding' to the 'requires-declaration' feature-list.
This adds support for modules that require (non-)freestanding
environment, such as the compiler builtin mm_malloc submodule.

Differential Revision: https://reviews.llvm.org/D23871

llvm-svn: 280613
2016-09-04 06:00:42 +00:00
Joerg Sonnenberger b50b2fac9f Trailing dot that shouldn't have been committed.
llvm-svn: 280609
2016-09-04 00:51:02 +00:00
Joerg Sonnenberger 82216f0faa PR 27200: Fix names of the atomic lock-free macros.
llvm-svn: 280607
2016-09-04 00:44:10 +00:00
Craig Topper f43e4a1728 [AVX-512] Remove masked integer mullo builtins and replace with native IR.
llvm-svn: 280597
2016-09-03 19:19:49 +00:00
Craig Topper 0e18976b8d [AVX-512] Remove masked integer add/sub builtins and replace with native IR.
llvm-svn: 280596
2016-09-03 18:29:35 +00:00
Craig Topper a815f488d5 [AVX-512] Implement masked floating point logical operations with native IR and remove the builtins.
llvm-svn: 280197
2016-08-31 05:38:58 +00:00
Craig Topper d0681d528d [X86] Use v2i64 vectors to implement _mm_and/andn/or/xor_pd.
These will be reused when removing some builtins from avx512vldqintrin.h and this will make the tests for that change show a better number of vector elements.

llvm-svn: 280196
2016-08-31 05:38:55 +00:00
Bruno Cardoso Lopes 6736e199c7 [Modules] Add 'gnuinlineasm' to the 'requires-declaration' feature-list.
This adds support for modules that require (no-)gnu-inline-asm
environment, such as the compiler builtin cpuid submodule.

This is the gnu-inline-asm variant of https://reviews.llvm.org/D23871

Differential Revision: https://reviews.llvm.org/D23905

rdar://problem/26931199

llvm-svn: 280159
2016-08-30 21:25:42 +00:00
Alexey Bader b5d90e57dc [OpenCL] Make is_valid_event, create_user_event overloadable.
Summary: Make is_valid_event and create_user_event overloadable like other built-ins.

Patch by Evgeniy Tyurin.

Reviewers: bader, yaxunl

Subscribers: Anastasia, cfe-commits

Differential Revision: https://reviews.llvm.org/D23914

llvm-svn: 280097
2016-08-30 14:42:54 +00:00
Asaf Badouh 356bb76809 [X86][AVX512F] minor fix of the parameter names
add "__" prefix

Bug 28842 https://llvm.org/bugs/show_bug.cgi?id=29040

Differential Revision: https://reviews.llvm.org/D23753


 

llvm-svn: 279392
2016-08-21 07:56:47 +00:00
Justin Lebar cb20a09f54 [CUDA] Improve handling of math functions.
Summary:
A bunch of related changes here to our CUDA math headers.

- The second arg to nexttoward is a double (well, technically, long
  double, but we don't have that), not a float.

- Add a forward-declare of llround(float), which is defined in the CUDA
  headers.  We need this for the same reason we need most of the other
  forward-declares: To prevent a constexpr function in our standard
  library from becoming host+device.

- Add nexttowardf implementation.

- Pull "foobarf" functions defined by the CUDA headers in the global
  namespace into namespace std.  This lets you do e.g. std::sinf.

- Add overloads for math functions accepting integer types.  This lets
  you do e.g. std::sin(0) without having an ambiguity between the
  overload that takes a float and the one that takes a double.

With these changes, we pass testcases derived from libc++ for cmath and
math.h.  We can check these testcases in to the test-suite once support
for CUDA lands there.

Reviewers: tra

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D23627

llvm-svn: 279140
2016-08-18 20:43:13 +00:00
Yaxun Liu 3317446301 [OpenCL] AMDGPU: Add extensions cl_amd_media_ops and cl_amd_media_ops2
Differential Revision: https://reviews.llvm.org/D23322

llvm-svn: 278851
2016-08-16 20:49:49 +00:00
Reid Kleckner 66e7717b46 Revert "[X86] Add xgetbv/x[X86] Add xgetbv xsetbv intrinsics to non-windows platforms"
This reverts commit r278783.  It breaks usage of _xgetbv on Windows.

llvm-svn: 278814
2016-08-16 16:04:14 +00:00
Marina Yatsina 197b65f833 [X86] Add xgetbv/x[X86] Add xgetbv xsetbv intrinsics to non-windows platforms
commit on behalf of guyblank

Differential Revision: https://reviews.llvm.org/D21959

llvm-svn: 278783
2016-08-16 08:13:36 +00:00
Lama Saba 5d01f224cf [X86][AVX512] lower __mm512_andnot_ps/__mm512_andnot_pd to IR
Differential revision: https://reviews.llvm.org/D23262
 

llvm-svn: 278209
2016-08-10 10:34:45 +00:00
Justin Lebar 2ef3dabd45 [CUDA] Add __device__ overloads for placement new and delete.
Summary:
Previously these sort of worked because they didn't end up resulting in
calls at the ptx layer.  But I'm adding stricter checks that break
placement new without these changes.

Reviewers: tra

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D23239

llvm-svn: 278194
2016-08-10 01:09:14 +00:00
Asaf Badouh 2f344b788c [AVX512] integer comparisions enumeration.
fix Bug 28842 https://llvm.org/bugs/show_bug.cgi?id=28842

Differential Revision: https://reviews.llvm.org/D22212

 

llvm-svn: 277955
2016-08-07 10:43:04 +00:00
Saleem Abdulrasool afdef205d8 Headers: Add ARM support to intrin.h for MSVC compatibility
This fixes compiling with headers from the Windows SDK for ARM, where the
YieldProcessor function (in winnt.h) refers to _ARM_BARRIER_ISHST.

The actual MSVC armintr.h contains a lot more definitions, but this is enough to
build code that uses the Windows SDK but doesn't use ARM intrinsics directly.

An alternative would to just keep the addition to intrin.h (to include
armintr.h), but not actually ship armintr.h, instead having clang's intrin.h
include armintr.h from MSVC's include directory. (That one works fine with
clang, at least for building code that uses the Windows SDK.)

Patch by Martin Storsjö!

llvm-svn: 277928
2016-08-06 17:58:24 +00:00
Yaxun Liu c489e39eca [OpenCL] Remove extra native_ functions from opencl-c.h
There should be no native_ builtin functions with double type arguments.

Patch by Aaron En Ye Shi.

Differential Revision : https://reviews.llvm.org/D23071

llvm-svn: 277754
2016-08-04 19:30:54 +00:00
Dimitry Andric f8099f256d Add more gcc compatibility names to clang's cpuid.h
Summary:
Some cpuid bit defines are named slightly different from how gcc's
cpuid.h calls them.

Define a few more compatibility names to appease software built for gcc:

* `bit_PCLMUL`      alias of `bit_PCLMULQDQ`
* `bit_SSE4_1`      alias of `bit_SSE41`
* `bit_SSE4_2`      alias of `bit_SSE42`
* `bit_AES`         alias of `bit_AESNI`
* `bit_CMPXCHG8B`   alias of `bit_CX8`

While here, add the misssing 29th bit, `bit_F16C` (which is how gcc
calls this bit).

Reviewers: joerg, rsmith

Subscribers: bruno, cfe-commits

Differential Revision: https://reviews.llvm.org/D22010

llvm-svn: 277307
2016-07-31 20:23:23 +00:00
Eric Christopher b638558e12 Remove unused variable.
Fixes PR28761.

llvm-svn: 277221
2016-07-29 22:11:11 +00:00
Yaxun Liu c944e65a24 [OpenCL] Added CLK_ABGR definition for get_image_channel_order return value
Added CLK_ABGR definition for get_image_channel_order return value inside opencl-c.h file.

Patch by Aaron En Ye Shi.

Differential Revision: https://reviews.llvm.org/D22767

llvm-svn: 277179
2016-07-29 17:50:10 +00:00
Craig Topper 351ed42795 [X86] Block pbroadcastq instructions on 32-bit targets instead of pbroadcastb.
Thanks to Simon Pilgrim for catching the mistake.

llvm-svn: 276564
2016-07-24 14:58:06 +00:00
Ekaterina Romanova a84c24f39c Add doxygen comments to emmintrin.h's intrinsics.
Only around 50% of the intrinsics in this file are documented now. The patches for the rest of the intrisics in this file will be send out later.

The doxygen comments are automatically generated based on Sony's intrinsics docu
ment.

I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream. This patch was internally reviewed by Paul Robinson.

llvm-svn: 276499
2016-07-22 23:49:37 +00:00
Craig Topper 45db56c375 [X86] Add missing __x86_64__ qualifiers on a bunch of intrinsics that assume 64-bit GPRs are available.
Usages of these intrinsics in a 32-bit build results in assertions in the backend.

llvm-svn: 276249
2016-07-21 07:38:39 +00:00
Simon Pilgrim e3b9ee0645 [X86][SSE] Reimplement SSE fp2si conversion intrinsics instead of using generic IR
D20859 and D20860 attempted to replace the SSE (V)CVTTPS2DQ and VCVTTPD2DQ truncating conversions with generic IR instead.

It turns out that the behaviour of these intrinsics is different enough from generic IR that this will cause problems, INF/NAN/out of range values are guaranteed to result in a 0x80000000 value - which plays havoc with constant folding which converts them to either zero or UNDEF. This is also an issue with the scalar implementations (which were already generic IR and what I was trying to match).

This patch changes both scalar and packed versions back to using x86-specific builtins.

It also deals with the other scalar conversion cases that are runtime rounding mode dependent and can have similar issues with constant folding.

Differential Revision: https://reviews.llvm.org/D22105

llvm-svn: 276102
2016-07-20 10:18:01 +00:00
Asaf Badouh a0b6f8fb56 [X86][AVX512F] minor fix of the parameter names
add "__" prefix

llvm-svn: 275384
2016-07-14 08:40:30 +00:00
Michael Zuckerman 3378653f8d [Clang][AVX512] Making cosmetic changes
llvm-svn: 275169
2016-07-12 12:42:27 +00:00
Craig Topper 4d61a3c2d8 [AVX512] Replace masked AND/OR/XOR intrinsics with native code and remove the builtins.
llvm-svn: 275049
2016-07-11 06:14:18 +00:00
Craig Topper 6e76fb61a7 [X86] Use __butilin_shufflevector for 512-bit shufps intrinsics.
llvm-svn: 275012
2016-07-10 05:57:21 +00:00
Craig Topper 95b61b0544 [X86] Use __builtin_ia32_vec_ext_v4hi and __builtin_ia32_vec_set_v4hi to implement pextrw/pinsertw MMX intrinsics instead of trying to use native IR.
Without this we end up generating code that doesn't use mmx registers and probably doesn't work well with other mmx intrinsics.

llvm-svn: 274968
2016-07-09 05:30:41 +00:00
Justin Bogner 2d5de7e568 NVPTX: Use the nvvm builtins to read SRegs rather than the legacy ptx ones
The ptx spellings were removed from LLVM in r274769.

llvm-svn: 274770
2016-07-07 16:41:08 +00:00
Justin Bogner 2f8de9fb4f NVPTX: Rename __builtin_ptx_shfl -> __nvvm_shfl
To match "NVPTX: Make the llvm.nvvm.shfl intrinsics and builtin names
consistent" in LLVM.

llvm-svn: 274663
2016-07-06 19:52:32 +00:00
Michael Zuckerman b920665493 [Clang][Feature] Adding CLFLUSHOPT feature and intrinsic to clang
Differential Revision: http://reviews.llvm.org/D21792

llvm-svn: 274559
2016-07-05 15:56:03 +00:00
Simon Pilgrim f5a8837e1b [X86][AVX512] Converted the VBROADCAST intrinsics to generic IR
llvm-svn: 274544
2016-07-05 12:59:33 +00:00
Asaf Badouh 136332888a [X86][AVX512F] add float/double abs intrinsics
add abs intrinsics that use native LLVM-IR.
change _mm512_mask[z]_and_epi{32|64} to use select intrinsic

Differential Revision: http://reviews.llvm.org/D21973

llvm-svn: 274542
2016-07-05 12:24:14 +00:00
Asaf Badouh f9cdb8de7a [AVX512] minor fix in sqrt{ss|sd} intrinsics arguments
Differential Revision: http://reviews.llvm.org/D21988

llvm-svn: 274541
2016-07-05 11:36:21 +00:00
Anastasia Stulova db7a31cce7 [OpenCL] An implementation of device side enqueue (DSE) from OpenCL v2.0 s6.13.17.
- Added new Builtins: enqueue_kernel, get_kernel_work_group_size
and get_kernel_preferred_work_group_size_multiple.

These Builtins use custom check to diagnose parameters of the passed Blocks
i. e. variable number of 'local void*' type params, and check different
overloads specified in Table 6.31 of OpenCL v2.0.

- IR is generated as an internal library call for each OpenCL Builtin,
reusing ObjC Block implementation.

Review: http://reviews.llvm.org/D20249
llvm-svn: 274540
2016-07-05 11:31:24 +00:00
Michael Zuckerman a72b49efe4 ntrinsics _mm256_permutexvar_epi64 doesn't accept three parameters as specify bellow.
I deleted the extra mask parameter.

__m256i _mm256_permutexvar_epi64 (__m256i idx, __m256i a)
#include "immintrin.h"
Instruction: vpermq
CPUID Flags: AVX512VL + AVX512F
Description
Shuffle 64-bit integers in a across lanes using the corresponding index in idx, and store the results in dst.
Operation
FOR j := 0 to 3
  i := j*64
    id := idx[i+1:i]*64
      dst[i+63:i] := a[id+63:id]
      ENDFOR
      dst[MAX:256] := 0
      dst[MAX:256] := 0
      
(From: Intel intrinsics guide)        

llvm-svn: 274539
2016-07-05 11:30:31 +00:00
Michael Zuckerman 7dac6fbdf8 [Clang][BuiltIn][AVX512] adding _mm{|256|512}_mask_cvt{s|us|}epi16_storeu_epi8 intrinsics
Differential Revision: http://reviews.llvm.org/D21729

llvm-svn: 274532
2016-07-05 08:08:01 +00:00
Craig Topper 2a383c9273 [X86] Use undefined instead of setzero in shufflevector based intrinsics when the second source is unused. Rewrite immediate extractions in shuffle intrinsics to be in ((c >> x) & y) form instead of ((c & z) >> x). This way only x varies between each use instead of having to vary x and z.
llvm-svn: 274525
2016-07-04 22:18:01 +00:00
Simon Pilgrim 427154db2a [X86][AVX512] Converted the VSHUFPD intrinsics to generic IR
llvm-svn: 274523
2016-07-04 21:30:47 +00:00
Simon Pilgrim 30db811526 [X86][AVX512] Converted the VPERMPD/VPERMQ intrinsics to generic IR
llvm-svn: 274502
2016-07-04 13:34:44 +00:00
Simon Pilgrim 17388f2569 [X86][AVX512] Converted the VPERMILPD/VPERMILPS intrinsics to generic IR
llvm-svn: 274492
2016-07-04 11:06:15 +00:00
Simon Pilgrim 275d721485 [X86][AVX512] Converted the MOVDDUP/MOVSLDUP/MOVSHDUP masked intrinsics to generic IR
llvm companion patch imminent

llvm-svn: 274442
2016-07-02 17:16:25 +00:00
Craig Topper b3a4477b13 [X86] Replace 128-bit and 256 masked vpermilps/vpermilpd builtins with native IR.
llvm-svn: 274425
2016-07-02 05:36:43 +00:00
Michael Zuckerman 3f316abdce [Clang][Intrinsics][AVX512][BuiltIn] adding intrinsics for vrangesd instruction set
Differential Revision: http://reviews.llvm.org/D21734

llvm-svn: 274218
2016-06-30 08:05:46 +00:00
Alexey Bader e5b3aebfb5 [OpenCL] Add attribute 'pure' to read_image built-in functions to enable optimizations.
Reviewers: Anastasia, yaxunl

Subscribers: pekka.jaaskelainen, pxli168, cfe-commits

Differential Revision: http://reviews.llvm.org/D21795

llvm-svn: 274122
2016-06-29 12:30:26 +00:00
David Majnemer 2916a612cd [intrin.h] Certain _Interlocked intrinsics return the old value
This fixes PR28326.

llvm-svn: 273986
2016-06-28 02:54:43 +00:00
Asaf Badouh 57819aa185 [X86] add _mm_loadu_si64
Differential Revision: http://reviews.llvm.org/D21504

llvm-svn: 273812
2016-06-26 13:51:54 +00:00
Craig Topper 50e3dfe9d0 [X86] Fix pslldq/psrldq intrinsics to not fail compilation with immediates larger than 16. This was accidentally broken in r272246.
llvm-svn: 273775
2016-06-25 07:31:14 +00:00
Craig Topper 79f53ca0b5 [AVX512] Replace masked unpack builtins with shufflevector and selects.
llvm-svn: 273533
2016-06-23 06:36:42 +00:00
Michael Zuckerman 716859aa64 [Clang][bmi][intrinsics] Adding _mm_tzcnt_64 _mm_tzcnt_32 intrinsics to clang.
Differential Revision: http://reviews.llvm.org/D21373

llvm-svn: 273401
2016-06-22 12:32:43 +00:00
Craig Topper 9ce3ddf2e6 [AVX512] Use a __v8hi vector inside of _mm_setzero_hi to match its name. Probably no real functional change.
llvm-svn: 273389
2016-06-22 06:36:23 +00:00
Craig Topper 08181f795f [AVX512] Fix _mm_setzero_di to not require avx512vl since its used by the avx512dqintrin.h. Also update the avx512dq test to not enable avx512vl feature so we can ensure correct dependencies.
llvm-svn: 273388
2016-06-22 06:36:21 +00:00
Craig Topper c89dda5938 [AVX512] Add missing typecasts to intrinsics.
llvm-svn: 273386
2016-06-22 06:36:16 +00:00
Craig Topper 879b0978f4 [AVX512] Move the 128-bit and 256-bit lzcnt intrinsics to avx512vlcdintrin.h where they belong.
llvm-svn: 273249
2016-06-21 06:53:58 +00:00
Yaxun Liu 143f083e4b [OpenCL] Include opencl-c.h by default as a clang module
Include opencl-c.h by default as a module to utilize the automatic AST caching mechanism of clang modules.

Add an option -finclude-default-header to enable default header for OpenCL, which is off by default.

Differential Revision: http://reviews.llvm.org/D20444

llvm-svn: 273191
2016-06-20 19:26:00 +00:00
Zvi Rackover 453d734201 [X86] _MM_ALIGN16 attribute support for non-windows targets
Summary:
This patch adds support for the _MM_ALIGN16 attribute on non-windows targets. This aligns Clang with ICC which supports the attribute on all targets.

Fixes PR28056

Reviewers: aaboud, echristo, cfe-commits, mkuper

Subscribers: zvi, mehdi_amini

Projects: #clang-c

Differential Revision: http://reviews.llvm.org/D21173

llvm-svn: 273095
2016-06-18 20:01:07 +00:00
Saleem Abdulrasool 5065d8cfc9 Headers: wordsmith error message
Use the marketing name for the MSVC release as pointed out by Nico Weber!

llvm-svn: 272979
2016-06-17 00:27:02 +00:00
Saleem Abdulrasool 13f3baf572 Headers: tweak for MSVC[<1800]
Earlier versions of MSVC did not include inttypes.h.  Ensure that we dont try to
include_next on those releases.

llvm-svn: 272741
2016-06-15 00:28:15 +00:00
Hans Wennborg f8b91f8336 s/Intrin.h/intrin.h/, trying to fix the build after r272701
llvm-svn: 272702
2016-06-14 20:14:24 +00:00
Nico Weber 73384a8f76 Rename Intrin.h to intrin.h, that's how all the documentation calls it.
llvm-svn: 272701
2016-06-14 19:54:40 +00:00
Michael Zuckerman c49f6ce3e1 [Clang][avx512][Intrinsics] adding prefetch gather intrinsics
Differential Revision: http://reviews.llvm.org/D21322

llvm-svn: 272667
2016-06-14 13:45:17 +00:00
Michael Zuckerman 223676d2cc [Clang][AVX512][intrinsics] Adding missing intrinsics div_pd and div_ps
Differential Revision: http://reviews.llvm.org/D20626

llvm-svn: 272658
2016-06-14 12:38:58 +00:00
David Majnemer d423574fde [immintrin] Reimplement _bit_scan_{forward,reverse}
There is no need to use a target-specific intrinsic to implement
_bit_scan_forward or _bit_scan_reverse, reimplementing them using
generic intrinsics makes it more likely that the middle end will
understand what's going on.

llvm-svn: 272564
2016-06-13 17:26:16 +00:00
Asaf Badouh 880f0c252b [X86][AVX512F] bugfix - sqrtps should get __mask16 as mask parameter
CR: Michael Zuckerman
llvm-svn: 272549
2016-06-13 15:15:57 +00:00
Simon Pilgrim beca5f295c [Clang][X86] Convert non-temporal store builtins to generic __builtin_nontemporal_store in headers
We can now use __builtin_nontemporal_store instead of target specific builtins for naturally aligned nontemporal stores which avoids the need for handling in CGBuiltin.cpp

The scalar integer nontemporal (unaligned) store builtins will have to wait as __builtin_nontemporal_store currently assumes natural alignment and doesn't accept the 'packed struct' trick that we use for normal unaligned load/stores.

The nontemporal loads require further backend support before we can safely convert them to __builtin_nontemporal_load

Differential Revision: http://reviews.llvm.org/D21272

llvm-svn: 272540
2016-06-13 09:57:52 +00:00
Craig Topper fc07498e4a [AVX512] Masked pcmpeqd, pcmpeqq, pcmpgtd, and pcmpgtq don't require avx512bw, just avx512vl.
llvm-svn: 272532
2016-06-13 04:15:11 +00:00
Craig Topper 7cc9263ec2 [AVX512] Implement masked and 512-bit pshufd intrinsics directly with __builtin_shufflevector and __builtin_ia32_select.
llvm-svn: 272467
2016-06-11 12:50:19 +00:00
Craig Topper 26d5b87316 [X86] Add explicit typecasts to some intrinsics.
llvm-svn: 272466
2016-06-11 12:50:12 +00:00
Craig Topper 68738332b8 [AVX512] Implement 512-bit and masked shufflelo and shufflehi intrinsics directly with __builtin_shufflevector and __builtin_ia32_select. Also improve the formatting of the AVX2 version.
llvm-svn: 272452
2016-06-11 03:31:13 +00:00
Craig Topper d4273a425e [AVX512] Add _mm512_bsrli_epi128 and _mm512_bslli_epi128 intrinsics.
llvm-svn: 272451
2016-06-11 03:31:07 +00:00
Ekaterina Romanova 71a68c928a Add doxygen comments to mmintrin.h's intrinsics.
The doxygen comments are automatically generated based on Sony's intrinsics docu
ment.

I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream.

llvm-svn: 272350
2016-06-10 00:10:40 +00:00
Justin Lebar 4fb5711751 [CUDA] Implement __shfl* intrinsics in clang headers.
Summary: Clang changes to make use of the LLVM intrinsics added in D21160.

Reviewers: tra

Subscribers: jholewinski, cfe-commits

Differential Revision: http://reviews.llvm.org/D21162

llvm-svn: 272299
2016-06-09 20:04:57 +00:00
Craig Topper 2769bb5753 [X86] Handle AVX2 pslldqi and psrldqi intrinsics shufflevector creation directly in the header file instead of in CGBuiltin.cpp. Simplify the sse2 equivalents as well.
llvm-svn: 272246
2016-06-09 05:15:12 +00:00
Craig Topper 3a0c7260f4 [X86] Add void to the argument list of intrinsics that don't take arguments since empty argument list mean something else in C.
llvm-svn: 272244
2016-06-09 05:14:28 +00:00
Igor Breger aadb876200 [AVX512] Emit select instruction instead of using x86 specific instrinsics.
This will allow us to remove the x86 instrinics from the backend.

Differential Revision: http://reviews.llvm.org/D21060

llvm-svn: 272141
2016-06-08 13:59:20 +00:00
Michael Zuckerman c4ae8537cf [Clang][AVX512][BUILTIN]Adding intrinsics for range_round_{sd|ss}
Differential Revision: http://reviews.llvm.org/D21002

llvm-svn: 272123
2016-06-08 08:19:27 +00:00
Ekaterina Romanova 50e94a3b34 Add doxygen comments to xmmintrin.h's intrinsics.
Only half of the intrinsics in this file is documented here. The patch for the o
ther half will be sent out later.

The doxygen comments are automatically generated based on Sony's intrinsics docu
ment.

I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream.

llvm-svn: 272121
2016-06-08 07:34:31 +00:00
Craig Topper f3efec65bb [AVX512] Reformat macro intrinsics, ensure arguments have proper typecasts, ensure result is typecasted back to the generic types.
llvm-svn: 272119
2016-06-08 06:08:07 +00:00
Craig Topper 605894985f [X86] Put parentheses around macro arguments in intrinsics.
llvm-svn: 272118
2016-06-08 06:08:04 +00:00
Michael Zuckerman 96d0399658 [clang][AVX512][Intrinsics] Adding intrinsics reduce_[round]_{ss|sd} to clang
Differential Revision: http://reviews.llvm.org/D21014

llvm-svn: 272012
2016-06-07 14:00:20 +00:00
Michael Zuckerman 1a7889f203 Fixing problem with rsqrt28_sd
maskz_rsqrt28_sd mapped to mask_rsqrt28_sd and not to the maskz.

llvm-svn: 271836
2016-06-05 15:57:49 +00:00
Michael Zuckerman 95721ac863 [Clang][AVX512]Adding set4 intrinsics
Differential Revision: http://reviews.llvm.org/D20866

llvm-svn: 271835
2016-06-05 15:43:30 +00:00
Michael Zuckerman f36f6eb036 [Clang][AVX512][Intrinsics] Adding two definitions _mm512_setzero and _mm512_setzero_epi32
Differential Revision: http://reviews.llvm.org/D20871

llvm-svn: 271832
2016-06-05 15:12:52 +00:00
Craig Topper 6a77b62640 [X86] Use unsigned types for vector arithmetic in intrinsics to avoid undefined behavior for signed integer overflow.
This is really only needed for addition, subtraction, and multiplication, but I did the bitwise ops too for overall consistency. Clang currently doesn't set NSW for signed vector operations so the undefined behavior shouldn't happen today.

llvm-svn: 271778
2016-06-04 05:43:41 +00:00
Craig Topper 406d5cdf7c [AVX512] Remove space in -1 constants. NFC
llvm-svn: 271777
2016-06-04 05:43:37 +00:00
Asaf Badouh 89f657611c [X86][AVX512] add intrinsics of Scalar FP to integer
Differential Revision: http://reviews.llvm.org/D20861

llvm-svn: 271499
2016-06-02 08:11:35 +00:00
Michael Zuckerman 9e7d0a98fa [Clang][AVX512][INTRINSICS] adding round cvt and fix regular cvtps_ph
Differential Revision: http://reviews.llvm.org/D20870

llvm-svn: 271498
2016-06-02 07:44:08 +00:00
Simon Pilgrim 00880511b1 [X86][SSE] Replace (V)CVTTPS2DQ and VCVTTPD2DQ truncating (round to zero) f32/f64 to i32 with generic IR (clang)
The 'cvtt' truncation (round to zero) conversions can be safely represented as generic __builtin_convertvector (fptosi) calls instead of x86 intrinsics. We already do this (implicitly) for the scalar equivalents.

Note: I looked at updating _mm_cvttpd_epi32 as well but this still requires a lot more backend work to correctly lower (both for debug and optimized builds).

Differential Revision: http://reviews.llvm.org/D20859

llvm-svn: 271436
2016-06-01 21:46:51 +00:00
Michael Zuckerman 6170c15fc6 [Clang][Intrinsics][avx512] Continue Adding round cvt to clang
And remove trailing spaces in intrinsic f test
Differential Revision: http://reviews.llvm.org/D20810

llvm-svn: 271398
2016-06-01 14:41:41 +00:00
Michael Zuckerman e54093fcc0 Adding front-end support to several intrinsics (bit scanning, conversion and state reading intrinsics)
Adding LLVM front-end support to two intrinsics dealing with bit scan: _bit_scan_forward and _bit_scan_reverse.
 Their functionality is as described in Intel intrinsics guide:
 https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_forward&expand=371,370
 https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_reverse&expand=371,370

 Furthermore, adding clang front-end support to these conversion intrinsics: _mm256_cvtsd_f64, _mm256_cvtsi256_si32 and _mm256_cvtss_f32.

 Finally, adding tests to all of the above, as well as to the state reading intrinsics _rdpmc and _rdtsc.
  Their functionality is also specified in the Intel intrinsics guide.


Commit on behalf of Omer Paparo Bivas

llvm-svn: 271387
2016-06-01 12:21:00 +00:00
Michael Zuckerman e6aa66a53d [Clang][Intrinsics][avx512] Adding round intrinsics fot max/min/sqrt instruction set to clang
Differential Revision: http://reviews.llvm.org/D20812

llvm-svn: 271373
2016-06-01 08:34:03 +00:00
Michael Zuckerman c301c194ec [Clang][Intrinsics][avx512] Adding round roundscale to clang
Differential Revision: http://reviews.llvm.org/D20815

llvm-svn: 271368
2016-06-01 07:35:44 +00:00
Michael Zuckerman 186d86738d [Clang][Intrinsics][avx512] Adding round cvt to clang
Differential Revision: http://reviews.llvm.org/D20790

llvm-svn: 271265
2016-05-31 11:27:34 +00:00
Craig Topper 74b5948f39 [X86] Use unaligned load intrinsics to implement other intrinsics instead of manually creating the unaligned load.
llvm-svn: 271250
2016-05-31 05:49:13 +00:00
Simon Pilgrim 645e1ad33a [X86][SSE] _mm_store1_ps/_mm_store1_pd should require an aligned pointer
According to the gcc headers, intel intrinsics docs and msdn codegen the _mm_store1_pd (and its _mm_store_pd1 equivalent) should use an aligned pointer - the clang headers are the only implementation I can find that assume non-aligned stores (by storing with _mm_storeu_pd).

Additionally, according to the intel intrinsics docs and msdn codegen the _mm_store1_ps (_mm_store_ps1) requires a similarly aligned pointer.

This patch raises the alignment requirements to match the other implementations by calling _mm_store_ps/_mm_store_pd instead.

I've also added the missing _mm_store_pd1 intrinsic (which maps to _mm_store1_pd like _mm_store_ps1 does to _mm_store1_ps).

As a followup I'll update the llvm fast-isel tests to match this codegen.

Differential Revision: http://reviews.llvm.org/D20617

llvm-svn: 271218
2016-05-30 17:55:25 +00:00
Justin Lebar 720f8da33a [CUDA] Fix order of vectorized ldg intrinsics' elements.
Summary: The order is [x, y, z, w], not [w, x, y, z].

Subscribers: cfe-commits, tra

Differential Revision: http://reviews.llvm.org/D20794

llvm-svn: 271215
2016-05-30 17:12:55 +00:00
Craig Topper 09175dab31 [X86] Replace unaligned store builtins in SSE/AVX intrinsic files with code that will compile to a native unaligned store. Remove the builtins since they are no longer used.
Intrinsics will be removed from llvm in a future commit.

llvm-svn: 271214
2016-05-30 17:10:30 +00:00
Michael Zuckerman 9fcf3552ad [Clang][avx512][builtin] Adding missing intrinsics for cvt
Differential Revision: http://reviews.llvm.org/D20618

llvm-svn: 271205
2016-05-30 13:22:12 +00:00
Yaxun Liu e8f49b9db7 [OpenCL] Add the default header file opencl-c.h for OpenCL C language
OpenCL has large number of "builtin" functions ("builtin" in the sense of OpenCL spec) which are defined in header files. To compile OpenCL kernels using these builtin functions, a header file is needed.

This header file is based on the Khronos implementation (https://github.com/KhronosGroup/SPIR/blob/spirv-1.0/lib/Headers/opencl.h) with heavy refactoring.

Re-commit after fixing failures on ppc64/systemz etc.

Differential Revision: http://reviews.llvm.org/D18369

llvm-svn: 271197
2016-05-30 02:22:28 +00:00
Simon Pilgrim 6d1a0c4c75 [X86][SSE] Make unsigned integer vector types generally available
As discussed on http://reviews.llvm.org/D20684, move the unsigned integer vector types used for zero extension to make them available for general use.

llvm-svn: 271187
2016-05-29 18:49:08 +00:00
Yaxun Liu 898eb39bfc Revert r271136 [OpenCL] Add the default header file opencl-c.h for OpenCL C language due to build failure on ppc64/hexagon/systemz.
llvm-svn: 271144
2016-05-28 19:50:40 +00:00
Yaxun Liu e54d7c44d0 [OpenCL] Add the default header file opencl-c.h for OpenCL C language
OpenCL has large number of "builtin" functions ("builtin" in the sense of OpenCL spec) which are defined in header files. To compile OpenCL kernels using these builtin functions, a header file is needed.

This header file is based on the Khronos implementation (https://github.com/KhronosGroup/SPIR/blob/spirv-1.0/lib/Headers/opencl.h) with heavy refactoring.

Differential Revision: http://reviews.llvm.org/D18369

llvm-svn: 271136
2016-05-28 19:09:01 +00:00
Simon Pilgrim 91b77ceaed [X86][SSE] Replace VPMOVSX and (V)PMOVZX integer extension intrinsics with generic IR (clang)
The VPMOVSX and (V)PMOVZX sign/zero extension intrinsics can be safely represented as generic __builtin_convertvector calls instead of x86 intrinsics.

This patch removes the clang builtins and their use in the sse2/avx headers - a companion patch will remove/auto-upgrade the llvm intrinsics.

Note: We already did this for SSE41 PMOVSX sometime ago.

Differential Revision: http://reviews.llvm.org/D20684

llvm-svn: 271106
2016-05-28 08:12:45 +00:00
Ekaterina Romanova 5a7f09c5af Clean up: remove trailing spaces in x86 intrinsic headers.
Differential Revision: http://reviews.llvm.org/D20614

llvm-svn: 271077
2016-05-28 00:18:59 +00:00
Ahmed Bougacha 5aa0ab3869 [Headers] Remove redundant typedef. NFC.
llvm-svn: 271022
2016-05-27 17:57:23 +00:00
Craig Topper 32578b7dcf [AVX512][Builtin] Fix palignr intrinsic for avx512vlbw. The immediate should not be multiplied by 8.
The 512-bit version was fixed recently but this was missed.

llvm-svn: 270970
2016-05-27 06:59:39 +00:00
David Majnemer b2c5720bfd [Intrin.h] Sort the __read[fg]s intrinsics
No functional change is intended.

llvm-svn: 270952
2016-05-27 02:06:14 +00:00
Michael Zuckerman 22c47e606a Adding missing _mm512_castsi512_si256 intrinsic.
llvm-svn: 270851
2016-05-26 14:32:11 +00:00
Michael Zuckerman eb5f178c4b Fix instrinsics names:
_mm128_cmp_ps_mask-->_mm_cmp_ps_mask
_mm128_mask_cmp_ps_mask-->_mm_mask_cmp_ps_mask
_mm128_cmp_pd_mask-->_mm_cmp_pd_mask
_mm128_mask_cmp_pd_mask-->_mm_mask_cmp_pd_mask

llvm-svn: 270830
2016-05-26 08:10:12 +00:00
Michael Zuckerman 6f08cebf36 [Clang][AVX512][BUILTIN] Adding intrinsics for set1
Differential Revision: http://reviews.llvm.org/D20562

llvm-svn: 270825
2016-05-26 06:54:52 +00:00
Michael Zuckerman efbf3f108e [Clang][AVX512][Builtin] Fix palignr intrinsics header
Differential Revision: http://reviews.llvm.org/D20620

llvm-svn: 270707
2016-05-25 15:05:03 +00:00
Michael Zuckerman d5cc6cd262 [Clang][AVX512][BUILTIN] Add missing intrinsics for cast
Differential Revision: http://reviews.llvm.org/D20523

llvm-svn: 270699
2016-05-25 14:04:21 +00:00
Eric Christopher d83af71b3a Make the altivec intrinsics that require immediate constant propagation
macros rather than functions.

Unfortunately couldn't come up with a simple testcase that didn't need
code generation to verify what was going on.

llvm-svn: 270625
2016-05-24 22:25:06 +00:00
Simon Pilgrim 90770c7c76 [X86][SSE] Replace lossless i32/f32 to f64 conversion intrinsics with generic IR
Both the (V)CVTDQ2PD(Y) (i32 to f64) and (V)CVTPS2PD(Y) (f32 to f64) conversion instructions are lossless and can be safely represented as generic __builtin_convertvector calls instead of x86 intrinsics without affecting final codegen.

This patch removes the clang builtins and their use in the sse2/avx headers - a future patch will deal with removing the llvm intrinsics, but that will require a bit more work.

Differential Revision: http://reviews.llvm.org/D20528

llvm-svn: 270499
2016-05-23 22:13:02 +00:00
Justin Lebar 91f6f07bb8 [CUDA] Add -fcuda-approx-transcendentals flag.
Summary:
This lets us emit e.g. sin.approx.f32.  See
http://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-sin

Reviewers: rnk

Subscribers: tra, cfe-commits

Differential Revision: http://reviews.llvm.org/D20493

llvm-svn: 270484
2016-05-23 20:19:56 +00:00
Michael Zuckerman f86eb71616 [clang][AVX512][Builtin] adding missing intrinsics for vpmultishiftqb{128|256|512} instruction set .
Differential Revision: http://reviews.llvm.org/D20521

llvm-svn: 270441
2016-05-23 15:04:39 +00:00
Michael Zuckerman e6542002fc [Clang][AVX512][BUILTIN]adding missing intrinsics for movdaq instruction set
Differential Revision: http://reviews.llvm.org/D20514

llvm-svn: 270401
2016-05-23 08:01:48 +00:00
Simon Pilgrim 28666ce778 [X86][AVX] Ensure zero-extension of _mm256_extract_epi8 and _mm256_extract_epi16
Ensure _mm256_extract_epi8 and _mm256_extract_epi16 zero extend their i8/i16 result to i32. This matches _mm_extract_epi8 and _mm_extract_epi16.

Fix for PR27594

Differential Revision: http://reviews.llvm.org/D20468

llvm-svn: 270330
2016-05-21 21:14:35 +00:00
Richard Smith b391930bbf Re-alphabetize this file list.
llvm-svn: 270170
2016-05-20 01:07:10 +00:00
Richard Smith f5c3a63c28 Revert incorrect module map changes in r269907 and replace them with the
appropriate changes.

llvm-svn: 270169
2016-05-20 01:06:47 +00:00
Justin Lebar 2e4ecfdebe [CUDA] Implement __ldg using intrinsics.
Summary:
Previously it was implemented as inline asm in the CUDA headers.

This change allows us to use the [addr+imm] addressing mode when
executing ld.global.nc instructions.  This translates into a 1.3x
speedup on some benchmarks that call this instruction from within an
unrolled loop.

Reviewers: tra, rsmith

Subscribers: jhen, cfe-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D19990

llvm-svn: 270150
2016-05-19 22:49:13 +00:00
Michael Zuckerman 178113e8cc [Clang][AVX512][intrinsics] continue completing missing set intrinsics
Differential Revision: http://reviews.llvm.org/D20160

llvm-svn: 270047
2016-05-19 12:07:49 +00:00
Michael Zuckerman 2cacc35343 [Clang][AVX512] completing missing intrinsics [pandnd].
Differential Revision: http://reviews.llvm.org/D20101

llvm-svn: 269939
2016-05-18 15:25:53 +00:00
Ashutosh Nema 51c9dd0081 Add new intrinsic support for MONITORX and MWAITX instructions
Summary:
MONITORX/MWAITX instructions provide similar capability to the MONITOR/MWAIT
pair while adding a timer function, such that another termination of the MWAITX
instruction occurs when the timer expires. The presence of the MONITORX and 
MWAITX instructions is indicated by CPUID 8000_0001, ECX, bit 29.

The MONITORX and MWAITX instructions are intercepted by the same bits that
intercept MONITOR and MWAIT. MONITORX instruction establishes a range to be
monitored. MWAITX instruction causes the processor to stop instruction
execution and enter an implementation-dependent optimized state until
occurrence of a class of events.

Opcode of MONITORX instruction is "0F 01 FA". Opcode of MWAITX instruction is
"0F 01 FB". These opcode information is used in adding tests for the
disassembler.

These instructions are enabled for AMD's bdver4 architecture.

Patch by Ganesh Gopalasubramanian!

Reviewers: echristo, craig.topper

Subscribers: RKSimon, joker.eph, llvm-commits, cfe-commits

Differential Revision: http://reviews.llvm.org/D19796

llvm-svn: 269907
2016-05-18 11:56:23 +00:00
Craig Topper 8c18e1120d [AVX512] Add parentheses around macro arguments in AVX512F intrinsics. Remove leading underscores from macro argument names. Add explicit typecasts to all macro arguments and return values. And finally reformat after all the adjustments.
This is a mostly mechanical change accomplished with a script. I tried to split out any changes to the typecasts that already existed into separate commits.

llvm-svn: 269746
2016-05-17 04:41:50 +00:00
Craig Topper d266188540 [AVX512] Add parentheses around macro arguments in AVX512VL intrinsics. Remove leading underscores from macro argument names. Add explicit typecasts to all macro arguments and return values. And finally reformat after all the adjustments.
This is a mostly mechanical change accomplished with a script. I tried to split out any changes to the typecasts that already existed into separate commits.

llvm-svn: 269745
2016-05-17 04:41:48 +00:00
Craig Topper f2e67a03fe [AVX512] Add parentheses around macro arguments in AVX512VLDQ intrinsics. Remove leading underscores from macro argument names. Add explicit typecasts to all macro arguments and return values. And finally reformat after all the adjustments.
This is a mostly mechanical change accomplished with a script. I tried to split out any changes to the typecasts that already existed into separate commits.

llvm-svn: 269744
2016-05-17 04:41:46 +00:00
Craig Topper 1a15b6aff2 [AVX512] Add parentheses around macro arguments in AVX512VLBW intrinsics. Remove leading underscores from macro argument names. Add explicit typecasts to all macro arguments and return values. And finally reformat after all the adjustments.
This is a mostly mechanical change accomplished with a script. I tried to split out any changes to the typecasts that already existed into separate commits.

llvm-svn: 269743
2016-05-17 04:41:42 +00:00
Craig Topper 8e95bb99fe [AVX512] Add parentheses around macro arguments in AVX512PF intrinsics. Remove leading underscores from macro argument names. Add explicit typecasts to all macro arguments and return values. And finally reformat after all the adjustments.
This is a mostly mechanical change accomplished with a script. I tried to split out any changes to the typecasts that already existed into separate commits.

llvm-svn: 269742
2016-05-17 04:41:40 +00:00
Craig Topper 0bb4664a88 [AVX512] Add parentheses around macro arguments in AVX512ER intrinsics. Remove leading underscores from macro argument names. Add explicit typecasts to all macro arguments and return values. And finally reformat after all the adjustments.
This is a mostly mechanical change accomplished with a script. I tried to split out any changes to the typecasts that already existed into separate commits.

llvm-svn: 269741
2016-05-17 04:41:38 +00:00
Craig Topper 41ad25a0f9 [AVX512] Add parentheses around macro arguments in AVX512DQ intrinsics. Remove leading underscores from macro argument names. Add explicit typecasts to all macro arguments and return values. And finally reformat after all the adjustments.
This is a mostly mechanical change accomplished with a script. I tried to split out any changes to the typecasts that already existed into separate commits.

llvm-svn: 269740
2016-05-17 04:41:36 +00:00
Craig Topper 709235674b [AVX512] Add parentheses around macro arguments in AVX512BW intrinsics. Remove leading underscores from macro argument names. Add explicit typecasts to all macro arguments and return values. And finally reformat after all the adjustments.
This is a mostly mechanical change accomplished with a script. I tried to split out any changes to the typecasts that already existed into separate commits.

llvm-svn: 269739
2016-05-17 04:41:33 +00:00
Craig Topper 58187d33b7 [AVX512] Correct types for scalar double precision FMA intrinsics and single precision getexp intrinsics.
llvm-svn: 269737
2016-05-17 04:41:29 +00:00
Craig Topper cd45b1a7c7 [X86] Add a few missing typecasts to intrinsics. Found by playing with -fno-lax-vector-conversions on the builtin tests.
llvm-svn: 269734
2016-05-17 03:42:31 +00:00
Craig Topper 3007cde8c5 [AVX512] _m512_setzero_qi/hi should return __m512i.
llvm-svn: 269733
2016-05-17 03:42:25 +00:00
Craig Topper f6d024edff [AVX512] Fix odd formatting in intrinsic header.
llvm-svn: 269732
2016-05-17 03:42:15 +00:00
Ekaterina Romanova 1168fdc9df Doxygen comments for avxintrin.h.
Added doxygen comments to avxintrin.h's intrinsics. As of now, only around 50% of the intrinsics in this file are documented here. The patches for the other half will be sent out later.

Updated bmiintrin.h to fix an incorrect section name.
Updated f16cintrin.h to fix incorect parameter names.


The doxygen comments are automatically generated based on Sony's intrinsics document.

I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream.

llvm-svn: 269718
2016-05-16 22:54:45 +00:00
Michael Zuckerman bf05a4589e [Clang][AVX512] completing missing intrinsics for [vpabs] instruction set
Differential Revision: http://reviews.llvm.org/D20069

llvm-svn: 269680
2016-05-16 18:57:24 +00:00
Nico Weber 379a1952b3 [ms] Reintroduce feature guards in intrinsic headers in Microsoft mode
Visual Studio's C++ standard library headers include intrin.h, so the intrinsic
headers get included a lot more often in Microsoft mode than elsewhere. The
AVX512 intrinsics are a lot of code (0.7 MB, causing 30% compile time overhead
for small programs including e.g. <string> and 6% compile time overhead for
larger projects like e.g. v8). Since multiversioning can't be relied on in
Microsoft mode (cl.exe doesn't support it), having faster compiles seems like
the much better tradeoff until we have a better intrinsic story going forward
(which we'll need for e.g. PR19898).

Actually using intrinsics on Windows already requires the right /arch:
settings, so this patch should have no big behavior change.

See also thread "The intrinsics headers (especially avx512) are too big. What
to do about it?" on cfe-dev.

http://reviews.llvm.org/D20291

llvm-svn: 269675
2016-05-16 18:14:07 +00:00
Michael Zuckerman cb85677471 [Clang][AVX512] completing missing intrinsics [vsqrt|vrsqrt|vrcp14 ].
Differential Revision: http://reviews.llvm.org/D20068

llvm-svn: 269649
2016-05-16 11:42:01 +00:00
Craig Topper 1aa231e3aa [X86] Add typecasts to remove most assumptions about what __m128i/__m256i is defined as. Add similar typecasts for the fp types as well.
llvm-svn: 269632
2016-05-16 06:38:42 +00:00
Craig Topper 9c6c85f1ad [AVX512] Add typecasts to some intrinsics to avoid doing operations on the __m512/__m512i/__m512d types.
llvm-svn: 269631
2016-05-16 06:38:36 +00:00
Craig Topper 91f23d900f [X86] Remove bad cast from the 'int' return type of __builtin_ia32_kortestchi to '__mask16' before return in an 'int' intrinsic.
llvm-svn: 269621
2016-05-16 01:09:16 +00:00
Craig Topper 7d00d2031d [AVX512] Fix bad typecasts on return value for 512-bit integer byte/word compare builtins.
llvm-svn: 269620
2016-05-16 00:51:06 +00:00
Craig Topper dca1f230ae [AVX512] Add intrinsics for 512-bit insertf32x8/insertf32x4/inserti32x4.
llvm-svn: 269617
2016-05-15 21:26:20 +00:00
Craig Topper 79d05c9b3d [AVX512] Mark some integer builtin arguments that go to immediates in final instructions as an ICE.
llvm-svn: 269613
2016-05-15 20:10:06 +00:00
Craig Topper 9864c59c89 [AVX512] Move unary negations to the left side of typecasts to specific vector type. The __m128/__m256/__m512 types should be treated more opaquely and not have any operations performed on them.
llvm-svn: 269612
2016-05-15 20:10:03 +00:00
Craig Topper f32e2fbe0e [AVX512] Use the correct mask type in an intrinsic.
llvm-svn: 269611
2016-05-15 20:10:00 +00:00
Craig Topper b81d430d3a [AVX512] Fix an intrinsic that was passing -2 as a mask instead of -1.
llvm-svn: 269610
2016-05-15 20:09:58 +00:00
Craig Topper 4537ea74eb [X86] Change most 'void' pointers in builtin type lists to more correct types. Fix some unaligned load/store intrinsics to use a less aligned type in their pointer casts.
llvm-svn: 269552
2016-05-14 06:03:13 +00:00
Michael Zuckerman 13d3c002df [clang][AVX512] completing missing set intrinsics
Differential Revision: http://reviews.llvm.org/D20099

llvm-svn: 269172
2016-05-11 11:41:29 +00:00
Michael Zuckerman 5e2c6b6200 [clang][AVX512] completing missing intrinsics for [vpermt2d|vptestm] instruction set.
Differential Revision: http://reviews.llvm.org/D20096

llvm-svn: 269170
2016-05-11 11:21:18 +00:00
Michael Zuckerman e9e8e573e3 [Clang][AVX512] completing missing intrinsics [load/store]
Differential Revision: http://reviews.llvm.org/D20063

llvm-svn: 269056
2016-05-10 13:13:54 +00:00
Michael Zuckerman de860e5585 [Clang][AVX512] completing missing intrinsics [vmin/vmax]{sd|sq|uq|ud}.
Differential Revision: http://reviews.llvm.org/D20064

llvm-svn: 269042
2016-05-10 11:34:19 +00:00
Michael Zuckerman 2564d2f5fe [Clang][AVX512] completing missing intrinsics [vextractf].
Differential Revision: http://reviews.llvm.org/D20061

llvm-svn: 269037
2016-05-10 10:14:50 +00:00
Michael Zuckerman 7360d8a9cc [Clang][AVX512] completing missing intrinsics [roundscale, ceil, floor]
Differential Revision: http://reviews.llvm.org/D20070

llvm-svn: 269022
2016-05-10 07:30:58 +00:00
Michael Zuckerman f9be3bb1d5 [clang][AVX512] completing missing intrinsics [vmin/vmax].
Differential Revision: http://reviews.llvm.org/D20062

llvm-svn: 268910
2016-05-09 12:38:49 +00:00
Michael Zuckerman f15447537f [Clang][AVX512] completing missing intrinsics [CVT]
Differential Revision: http://reviews.llvm.org/D20056

llvm-svn: 268903
2016-05-09 10:32:51 +00:00
Michael Zuckerman e6f7389b5a [Clang][Builtin][AVX512] Adding intrinsics fot cvt{u}si2s{d|s} cvt{sd|ss}2{ss|sd} instruction set
Differential Revision: http://reviews.llvm.org/D19765

llvm-svn: 268481
2016-05-04 08:55:11 +00:00
Michael Zuckerman c66770313a [clang][AVX512][BuiltIn] Adding intrinsics for cast{pd|ps|si}128_{pd|ps|si}512 and castsi256_si512 instruction set
Differential Revision: http://reviews.llvm.org/D19858

llvm-svn: 268387
2016-05-03 14:26:52 +00:00
Michael Zuckerman e871785eb6 [Clang][avx512][Builtin] Adding intrinsics for cvtw2mask{128|256|512} instruction set
Differential Revision: http://reviews.llvm.org/D19766

llvm-svn: 268385
2016-05-03 14:12:23 +00:00
Michael Zuckerman 8bfb7776e4 [Clang][AVX512][Builtin] Adding intrinsics for vcvt{ph|ps}2{ps|ph} instruction set
Differential Revision: http://reviews.llvm.org/D19767

llvm-svn: 268376
2016-05-03 12:45:04 +00:00
Michael Zuckerman 138fc5b5a8 [Clang][AVX512][Builtin] Adding intrinsics for vcvttpd2udq instruction set
Differential Revision: http://reviews.llvm.org/D19768

llvm-svn: 268373
2016-05-03 11:05:24 +00:00
Michael Zuckerman 708e759b86 [Clang][AVX512][BUILTIN] Adding intrinsics for compressstore{df|di|sf|si} instruction set.
Differential Revision: http://reviews.llvm.org/D19808

llvm-svn: 268372
2016-05-03 10:42:46 +00:00
Michael Zuckerman 5f0e96e56a [CLANG][AVX512][BUILTIN]movap{d|s}{128|256|512}
Differential Revision: http://reviews.llvm.org/D17818

llvm-svn: 268230
2016-05-02 14:02:01 +00:00
Michael Zuckerman d6e68ce75f [Clang][AVX512][BuiltIn] Adding intrinsics for cvtps2pd instruction set
Differential Revision: http://reviews.llvm.org/D19774

llvm-svn: 268217
2016-05-02 09:42:31 +00:00
Michael Zuckerman 6a0e0871db [Clang][avx512][builtin] Adding intrinsics for vexpand{d|q|ps|pd} instrctuon set
Differential Revision: http://reviews.llvm.org/D19467

llvm-svn: 268214
2016-05-02 08:36:41 +00:00
Michael Zuckerman c62f27e3f4 [Clang][BuiltIn][avx512] Adding intrinsics for vpshufd instruction set
Differential Revision: http://reviews.llvm.org/D19580

llvm-svn: 268213
2016-05-02 07:35:27 +00:00
Michael Zuckerman ac1e519944 [clang][Builtin][AVX512] Adding intrinsics for vmovshdup and vmovsldup instruction set
Differential Revision: http://reviews.llvm.org/D19595

llvm-svn: 268196
2016-05-01 14:43:43 +00:00
Michael Zuckerman 0b9d105a16 [clang][BuiltIn][AVX512]Adding intrinsics for cmp{ss|sd} instruction set.
Differential Revision: http://reviews.llvm.org/D19601

llvm-svn: 268028
2016-04-29 11:01:16 +00:00
Michael Zuckerman 41f5a37707 [Clang][AVX512][Builtin] Adding intrinsics for compress instruction set
Differential Revision: http://reviews.llvm.org/D19599

llvm-svn: 268013
2016-04-29 08:52:02 +00:00
Michael Zuckerman de8d3753d3 [clang][AVX512][Builtin] Adding intrinsics for the SAD instruction set.
Differential Revision: http://reviews.llvm.org/D19591

llvm-svn: 267942
2016-04-28 21:21:08 +00:00
Michael Zuckerman 533e065bdc [Clang][BuiltIn][AVX512] Adding intrinsics fot align{d|q} and palignr instruction set
Differential Revision: http://reviews.llvm.org/D19588

llvm-svn: 267876
2016-04-28 12:47:30 +00:00
Michael Zuckerman 514f05543f [Clang][Builtin][AVX512] Adding intrisnics for the vpconflict{q|d} instruction set
Differential Revision: http://reviews.llvm.org/D19525

llvm-svn: 267728
2016-04-27 15:35:13 +00:00
Michael Zuckerman 8c2900f44d [Clang][BuiltIn][AVX512] Adding intrinsics without mask for VBROADCAST and VPBROADCAST instruction set .
Differential Revision: http://reviews.llvm.org/D19196

llvm-svn: 267696
2016-04-27 11:43:14 +00:00
Michael Zuckerman 7c85a8cb46 [Clang][BuiltIn][AVX512]Adding intrinsics for vmovntdqa vmovntpd vmovntps instruction set
Differential Revision: http://reviews.llvm.org/D19529

llvm-svn: 267690
2016-04-27 10:44:15 +00:00
Ekaterina Romanova a2d72377a1 Updated doxygen comments for intrinsics.
(1) Removed \code.. \endcode tags around the instruction name. This matches the doxygen format for all other intrinsics.
(2) Did a better formatting for the comments (to fit into 80 columns more compactly).

llvm-svn: 267676
2016-04-27 07:14:02 +00:00
Michael Zuckerman fa508e8b6d [Clang][Builtin][AVX512]Adding k-register logic intrinsics KAND, KANDN, KOR, KORTEST, KXNOR, KXOR, KUNPACK instruction set.
Differential Revision: http://reviews.llvm.org/D19466

llvm-svn: 267425
2016-04-25 16:42:29 +00:00
Michael Zuckerman edc82fe3ef [Clang][Builtin][AVX512]Adding intrinsics for vfpclass{sd|ss} vfpclass{pd|ps} instruction set
Differential Revision: http://reviews.llvm.org/D19476

llvm-svn: 267414
2016-04-25 14:48:23 +00:00
Michael Zuckerman fcf32c2f00 [Clang][AVX512][BUILTIN] Adding intrinsics for VSCATTERPF{1|0}{DPS|QPS|DPD|QPD} instruction set
Differential Revision: http://reviews.llvm.org/D19313

llvm-svn: 267398
2016-04-25 13:01:40 +00:00
Michael Zuckerman 8938e836c4 [Clang][AVX512][BuiltIn] Adding support to intrinsics of VPERMD and VPERMW instruction set
Differential Revision: http://reviews.llvm.org/D19195

llvm-svn: 267380
2016-04-25 05:32:35 +00:00
Michael Zuckerman 743d68c3cb [clang][AVX512][Builtin] adding intrinsics for vf{n}madd{ss|sd} and vf{n}sub{ss|sd} instruction set
Differential Revision: http://reviews.llvm.org/D19320

llvm-svn: 267135
2016-04-22 10:56:24 +00:00
Michael Zuckerman a1ceca20b6 [Clang][AVX512][BUILTIN] Adding scalar intrinsics for rsqrt14 ,rcp14, getexp and getmant instruction set
Differential Revision: http://reviews.llvm.org/D19326

llvm-svn: 267129
2016-04-22 10:06:10 +00:00
Artem Belevich c34a519407 [CUDA] removed unneeded __nvvm_reflect_anchor()
Since r265060 LLVM infers correct __nvvm_reflect attributes, so
explicit declaration of __nvvm_reflect() is no longer needed.

Differential Revision: http://reviews.llvm.org/D19074

llvm-svn: 267062
2016-04-21 21:40:27 +00:00
Michael Zuckerman 4fa96af4db [Clang][AVX512][BuiltIn] Adding intrinsics of VGATHER{DPS|DPD} , VPGATHER{QD|QQ|DD|DQ} and VGATHERPF{0|1}{DPS|QPS|DPD|QPD} instruction set .
Differential Revision: http://reviews.llvm.org/D19224

llvm-svn: 266983
2016-04-21 12:47:27 +00:00
Richard Smith e0fa4c83b2 [modules] Make the tweak to avoid circular inclusion of emmintrin.h and
xmmintrin.h a bit more directed. If for whatever reason modules are enabled but
we textually include one of these headers, don't deploy the special case for
modules. To make this work cleanly, extend __building_module to be defined
even when modules is disabled.

llvm-svn: 266945
2016-04-21 01:46:37 +00:00
Michael Zuckerman 6fa512cecf [Clang][Builtin][AVX512] Adding intrinsics for VGETMANT{PD|PS} and VGETEXP{PD|PS} instruction set
Differential Revision: http://reviews.llvm.org/D19197

llvm-svn: 266763
2016-04-19 17:10:29 +00:00
Michael Zuckerman ef2979af50 [Clang][AVX512][BUILTIN] Adding intrinsics support to VEXTRACT{I|F} and VINSERT{I|F} instruction set
Differential Revision: http://reviews.llvm.org/D19097

llvm-svn: 266745
2016-04-19 15:18:23 +00:00
Richard Smith 20d4701b3d [modules] Don't expose *intrin.h headers that cannot be included standalone as
separate modules. These cause build breakage with -fmodules-local-submodule-visibility.

llvm-svn: 266501
2016-04-16 00:46:26 +00:00
Michael Zuckerman 0a3508a8d3 [Clang][AVX512][BUILTIN] Adding support for intrinsics of vpmov{d|q}{b|w|d}{128|256|512} instruction set
Differential Revision: http://reviews.llvm.org/D19055

llvm-svn: 266280
2016-04-14 07:56:51 +00:00
Michael Zuckerman d871531687 [Clang][AVX512][Builtin] Adding intrinsics of vpmovus{d|q}{b|w|d}{128|256|512} instruction set
Differential Revision: http://reviews.llvm.org/D19050

llvm-svn: 266278
2016-04-14 06:48:09 +00:00
Michael Zuckerman e1680617b0 [Clang][AVX512][Builtin] Adding support to intrinsics of pmovs{d|q}{b|w|d}{128|256|512} instruction set
Differential Revision: http://reviews.llvm.org/D19023

llvm-svn: 266202
2016-04-13 15:02:04 +00:00
Michael Zuckerman c2b6128a8f [Clang][AVX512][Builtin] Adding support for VBROADCAST and VPBROADCASTB/W/D/Q instruction set
Differential Revision: http://reviews.llvm.org/D19012

llvm-svn: 266195
2016-04-13 12:58:01 +00:00
Michael Zuckerman 074edd7c1e [Clang][AVX512][Builtin] Adding supporting to intrinsics of cvt{b|d|q}2mask{128|256|512} and cvtmask2{b|d|q}{128|256|512} instruction set.
Differential Revision: http://reviews.llvm.org/D19009

llvm-svn: 266188
2016-04-13 10:49:37 +00:00
Chuang-Yu Cheng 8eac7ae9ad [PPC64][VSX] Add a couple of new data types for vec_vsx_ld and vec_vsx_st intrinsics and fix incorrect testcases with minor refactoring
New added data types:
  vector double vec_vsx_ld (int, const double *);
  vector float vec_vsx_ld (int, const float *);
  vector bool short vec_vsx_ld (int, const vector bool short *);
  vector bool int vec_vsx_ld (int, const vector bool int *);
  vector signed int vec_vsx_ld (int, const signed int *);
  vector unsigned int vec_vsx_ld (int, const unsigned int *);

  void vec_vsx_st (vector double, int, double *);
  void vec_vsx_st (vector float, int, float *);
  void vec_vsx_st (vector bool short, int, vector bool short *);
  void vec_vsx_st (vector bool short, int, signed short *);
  void vec_vsx_st (vector bool short, int, unsigned short *);
  void vec_vsx_st (vector bool int, int, vector bool int *);
  void vec_vsx_st (vector bool int, int, signed int *);
  void vec_vsx_st (vector bool int, int, unsigned int *);

Also fix testcases which use non-vector argument version of vec_vsx_ld or
vec_vsx_st, but pass incorrect parameter.

llvm-svn: 266166
2016-04-13 05:16:31 +00:00
Eric Christopher d5c75eed44 Add a couple of missing vsx load and store intrinsics.
Patch by Jing Yu!

llvm-svn: 266122
2016-04-12 21:08:54 +00:00
Michael Zuckerman 04fb3bc682 [Clang][BuiltIn][avx512] Adding avx512 (shuf,sqrt{ss|sd},rsqrt ) builtin to clang
llvm-svn: 266048
2016-04-12 07:59:39 +00:00
Michael Zuckerman 81f468c859 [Clang][AVX512][BuiltIn] Adding avx512 ( psll{d|q}512,psllv{16si|8di},psra{d|q}512,psrav{16si|8di},pternlog{d|q}{128|256|512} ) builtin to clang
Differential Revision: http://reviews.llvm.org/D18926

llvm-svn: 265964
2016-04-11 17:04:21 +00:00
Michael Zuckerman 6b5f4d8ad1 [CLANG] [AVX512] [BUILTIN] Adding PSRA{Q|D|QI|DI}{128|256|512} builtin
Differential Revision: http://reviews.llvm.org/D17693

llvm-svn: 265952
2016-04-11 15:46:39 +00:00
Michael Zuckerman 1af947a7b3 [Clang][AVX512][BuiltIn] Adding avx512 ( punpck{h|l}{dq|qdq}{128|256|512},rndscale{ss|sd}, {scalef{ss|sd|pd512|ps512} ) builtin to clang
Differential Revision: http://reviews.llvm.org/D18929

llvm-svn: 265935
2016-04-11 12:32:31 +00:00
Michael Zuckerman 07525091e6 [Clang][AVX512][BuiltIn] Adding avx512 ( ptest{n}m{b|w}{128|256|512} ) builtin to clang
Differential Revision: http://reviews.llvm.org/D18924

llvm-svn: 265928
2016-04-11 10:22:07 +00:00
Michael Zuckerman d8d2f62107 [Clang][AVX512][BuiltIn] Adding avx512 ( vperm{i|t}2var, vpermil{var}{ps|pd}{256|512} ) builtin to clang.
Differential Revision: http://reviews.llvm.org/D18933

llvm-svn: 265915
2016-04-11 07:15:34 +00:00
Michael Zuckerman 8d16199b7b [Clang][AVX512][BuiltIn] Adding avx512 ( vcvt ) builtin to clang
Differential Revision: http://reviews.llvm.org/D18932

llvm-svn: 265904
2016-04-10 17:24:03 +00:00
Michael Zuckerman cdd54c83d8 Adding avx512 (unpck{h|l}{pd|ps}, rcp14{pd|ps}{128|256},vplzcnt{d|q} ) builtin to clang
Differential Revision: http://reviews.llvm.org/D18931

llvm-svn: 265896
2016-04-10 12:54:23 +00:00
Michael Zuckerman fa7ccc5bcf [Clang][AVX512][BuiltIn] Adding avx512 ( store ) builtin to clang
Differential Revision: http://reviews.llvm.org/D18925

llvm-svn: 265895
2016-04-10 10:51:04 +00:00
Ekaterina Romanova f2ed62027d Add doxygen comments to emmintrin.h's intrinsics. Only around 25% of the intrinsics in this file are documented now. The patches for the rest of the intrisics in this file will be send out later.
The doxygen comments are automatically generated based on Sony's intrinsics document.

I got an OK from Eric Christopher to commit doxygen comments without prior code review upstream. This patch was internally reviewed by Paul Robinson.

llvm-svn: 265844
2016-04-08 20:45:48 +00:00
Justin Lebar 25c36fd61b [CUDA] Tweak math forward declares so we're compatible with libstdc++4.9.
Summary:
See comments in patch; we were assuming that some stdlib math functions
would be defined in namespace std, when in fact the spec says they
should be defined in the global namespace.  libstdc++4.9 became more
conforming and broke us.

This new implementation seems to cover the known knowns.

Reviewers: rsmith

Subscribers: cfe-commits, tra

Differential Revision: http://reviews.llvm.org/D18882

llvm-svn: 265751
2016-04-07 23:55:53 +00:00
Michael Zuckerman 5ae71243c2 Fixing duplicate declaration "_mm256 _mm_set_epi32" in revision 262177
Differential Revision: http://reviews.llvm.org/D17685

llvm-svn: 265677
2016-04-07 14:44:08 +00:00
Yunzhong Gao c293a2688d Add copyright notice to the modulemap file.
The module.modulemap file in the lib/Headers directory was missing the LLVM
copyright notice. This patch adds the copyright notice just like the rest of
the files in this directory.

Differential Revision: http://reviews.llvm.org/D18709

llvm-svn: 265325
2016-04-04 18:46:09 +00:00
Justin Lebar cb28f15fbc [CUDA] Fix typo in __clang_cuda_runtime_wrapper.h.
We're #including the wrong file!

llvm-svn: 265083
2016-04-01 00:25:42 +00:00
Justin Lebar 0cda764430 [CUDA] Add math forward declares to CUDA header wrapper.
Summary:
This is necessary for a future patch which will make all constexpr
functions implicitly host+device.  cmath may declare constexpr
functions, but these we do *not* want to be host+device.  The forward
declares added in this patch prevent this (because the rule will be,
constexpr functions become implicitly host+device unless they're
preceeded by a decl with __device__).

Reviewers: tra

Subscribers: cfe-commits, rnk, rsmith

Differential Revision: http://reviews.llvm.org/D18539

llvm-svn: 264963
2016-03-30 23:30:14 +00:00
Justin Lebar 50e5f184d8 [CUDA] Add missing #undef __DEVICE__ to CUDA shim header.
llvm-svn: 264742
2016-03-29 16:24:23 +00:00
Michael Zuckerman def78750b7 [CLANG][avx512][BUILTIN] Adding fixupimm{pd|ps|sd|ss}
getexp{sd|ss} getmant{sd|ss} kunpck{di|si} loada{pd|ps} loaddqu{di|hi|qi|si} max{sd|ss} min{sd|ss} kmov16 builtins to clang


Differential Revision: http://reviews.llvm.org/D18215

llvm-svn: 264574
2016-03-28 12:23:09 +00:00
Justin Lebar 334535132f [CUDA] Don't define __NVCC__.
Summary:
We decided this makes life too difficult for code authors.  For example,
people may want to detect NVCC and disable variadic templates, which
NVCC does not support, but which we do.

Since people are going to have to change compiler flags *anyway* in
order to compile with clang, if they really want the old behavior, they
can pass -D__NVCC__.

Tested with tensorflow and thrust, no apparent problems.

Reviewers: tra

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D18417

llvm-svn: 264205
2016-03-23 22:42:27 +00:00
John Thompson debce24c90 D18325: Added mm_malloc module export.
llvm-svn: 264092
2016-03-22 20:57:51 +00:00
Daniel Jasper be50836514 Make functions in altivec.h be __inline__. As they are all also marked
__always_inline__, this has likely been meant from the start.

Review: http://reviews.llvm.org/D18015
llvm-svn: 263302
2016-03-11 22:13:28 +00:00
Ekaterina Romanova 13f189da86 Add doxygen comments to avxintrin.h's intrinsics.
Only around 25% of the intrinsics in this file are documented here. The patches for the other half will be sent out later.

The doxygen comments are automatically generated based on Sony's intrinsics document.

I got an OK from Eric Christopher to commit doxygen comments without prior code review upstream.

llvm-svn: 263175
2016-03-11 00:05:54 +00:00
Ekaterina Romanova e2961f71d2 Add doxygen comments to xmmintrin.h's intrinsics.
Only half of the intrinsics in this file is documented here. The patch for the other half will be sent out later.

The doxygen comments are automatically generated based on Sony's intrinsics document.

I got an OK from Eric Christopher to commit doxygen comments without prior code review upstream.

llvm-svn: 263098
2016-03-10 09:37:04 +00:00
Kit Barton fbab158767 [PPC] FE support for generating VSX [negated] absolute value instructions
Includes new built-in, conversion of built-in to target-independent intrinsic
and update in the header file. Tests are also updated. There is a second part in
the backend for which I will post a separate code-review. BACKEND PART SHOULD BE
COMMITTED FIRST.

Phabricator: http://reviews.llvm.org/D17816
llvm-svn: 263051
2016-03-09 19:28:31 +00:00
Michael Zuckerman 10d6f9ac04 Fixing wrong header title name.
Differential Revision: http://reviews.llvm.org/D17917

llvm-svn: 263007
2016-03-09 11:26:45 +00:00
Ekaterina Romanova c8976d58fe Add doxygen comments to bmiintrin.h's intrinsics.
The doxygen comments are automatically generated based on Sony's intrinsics document.

I got an OK from Eric Christopher to commit doxygen comments without prior code review upstream.

llvm-svn: 262895
2016-03-08 01:36:59 +00:00
Michael Zuckerman e71d59fc4f [CLANG][AVX512][BUILTIN] Add builtin vcomi{ss|sd}
Differential Revision: http://reviews.llvm.org/D17919

llvm-svn: 262847
2016-03-07 19:15:00 +00:00
Michael Zuckerman 9f33848f04 [CLANG][AVX512][BUILTIN] Adding new feature flag headed files and new BUILTIN vpermi2varq{i|t}{128|256|512}{mask|maskz}
Differential Revision: http://reviews.llvm.org/D17917

llvm-svn: 262834
2016-03-07 17:04:11 +00:00
Michael Zuckerman 0190c65571 [CLANG][AVX512][BUILTIN] Adding new feature flag header file and new builtin vpmadd52{h|l}uq{128|256|512}{mask|maskz}
Differential Revision: http://reviews.llvm.org/D17915

llvm-svn: 262820
2016-03-07 09:55:55 +00:00
Michael Zuckerman 912be16a0e [CLANG][AVX512][BUILTIN] Adding vpmultishiftqb{128|256|512}
Differential Revision: http://reviews.llvm.org/D17914

llvm-svn: 262817
2016-03-07 08:29:10 +00:00
Michael Zuckerman 0d67e4b5d6 [CLANG][AVX512][BUILTIN] movddup{128|256|512}
Differential Revision: http://reviews.llvm.org/D17826

llvm-svn: 262617
2016-03-03 13:43:05 +00:00
Michael Zuckerman 1ad03e7f01 [CLANG][AVX512][BUILTIN] movdqu{qi|hi} {128|256|512}
Differential Revision: http://reviews.llvm.org/D17814

llvm-svn: 262609
2016-03-03 11:34:52 +00:00
Michael Zuckerman ffbb67a8e2 [CLANG][AVX512][BUILTIN] movdqa{32|64}{load|store|}{128|256|512}
Differential Revision: http://reviews.llvm.org/D17812

llvm-svn: 262598
2016-03-03 09:26:01 +00:00
Michael Zuckerman abbe34bce6 [Clang][AVX512][BUILTIN] Adding PSRL{W|WI}{128|256|512}
Differential Revision: http://reviews.llvm.org/D17754

llvm-svn: 262593
2016-03-03 08:55:20 +00:00