66f1fbaaad
Fix miscompilation of float vector returns. Compile code to this:
...
_func:
vsldoi v2, v3, v2, 12
vsldoi v2, v2, v2, 4
blr
instead of:
_func:
vsldoi v2, v3, v2, 12
vsldoi v2, v2, v2, 4
*** vor f1, v2, v2
blr
llvm-svn: 29607
2006-08-11 16:47:32 +00:00
bd1c5a8fb8
Match tablegen changes.
...
llvm-svn: 29604
2006-08-11 09:08:15 +00:00
81b645a76b
CALLSEQ_* produces chain even if that's not needed.
...
llvm-svn: 29603
2006-08-11 09:03:33 +00:00
c24a1d3093
Start eliminating temporary vectors used to create DAG nodes. Instead, pass
...
in the start of an array and a count of operands where applicable. In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap. In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.
I updated a lot of code calling getNode that takes a vector, but ran out of
time. The rest of the code should be updated, and these methods should be
removed.
We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.
It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.
llvm-svn: 29566
2006-08-08 02:23:42 +00:00
b9d34bd098
Match tablegen isel changes.
...
llvm-svn: 29549
2006-08-07 22:28:20 +00:00
8298265042
Fix some ppc64 issues with vector code.
...
llvm-svn: 29384
2006-07-28 16:45:47 +00:00
b572401bea
Remove InFlightSet hack. No longer needed.
...
llvm-svn: 29373
2006-07-28 00:47:19 +00:00
78bf1074fc
Resolve BB references with relocation.
...
llvm-svn: 29351
2006-07-27 18:21:10 +00:00
7ec7b467df
synchronizeICache removeed from TargetJITInfo.
...
llvm-svn: 29348
2006-07-27 17:33:48 +00:00
f300896420
Remove NodeDepth
...
llvm-svn: 29338
2006-07-27 06:40:15 +00:00
787565024a
Support jump tables when in PIC relocation model
...
llvm-svn: 29318
2006-07-27 01:13:04 +00:00
9e56e5c003
Rename RelocModel::PIC to PIC_, to avoid conflicts with -DPIC.
...
llvm-svn: 29307
2006-07-26 21:12:04 +00:00
f6acb34d23
- Refactor the code that resolve basic block references to a TargetJITInfo
...
method.
- Added synchronizeICache() to TargetJITInfo. It is called after each block
of code is emitted to flush the icache. This ensures correct execution
on targets that have separate dcache and icache.
- Added PPC / Mac OS X specific code to do icache flushing.
llvm-svn: 29276
2006-07-25 20:40:54 +00:00
4f8eb5ccaf
bswapped load/store instructions are only availble in indexed addressing form.
...
As such, use xoaddr (indexed only), not xaddr for address selection.
This fixes CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll, a crash compiling lencod.
llvm-svn: 29208
2006-07-19 17:15:36 +00:00
b00b6c2e86
Make the implicit def instructions look like other instrs.
...
llvm-svn: 29174
2006-07-18 16:33:26 +00:00
e1758d4cef
Remove what little AIX support we have. It has never been tested and isn't
...
complete.
llvm-svn: 29156
2006-07-15 01:24:23 +00:00
96aecb5d76
Add missing PPC64 extload/truncstores
...
llvm-svn: 29140
2006-07-14 04:42:02 +00:00
950dffaed6
Add a note
...
llvm-svn: 29139
2006-07-14 04:07:29 +00:00
077b86a078
Another fix in the rotate encodings, needed when the first two operands are not
...
the same.
llvm-svn: 29136
2006-07-13 21:52:41 +00:00
b42a945fd2
Print negative immediates as negative values instead of large constants
...
when using the immshifted addressing mode.
llvm-svn: 29130
2006-07-12 23:24:02 +00:00
dd57ac4871
Fix encoding of rotates, such as rldicl
...
llvm-svn: 29128
2006-07-12 22:08:13 +00:00
5b17dee741
Implement PPC64 relocations types
...
llvm-svn: 29125
2006-07-12 21:23:20 +00:00
1ec5e73b32
An overaggressive #ifdef allows a function to fall off the bottom of the
...
function instead of returning a value. This sometimes allowed the ppc32 jit
to be used in 64-bit mode.
llvm-svn: 29123
2006-07-12 20:42:10 +00:00
6e662083d9
The PPC64 JIT needs register numbers to encode instructions.
...
llvm-svn: 29114
2006-07-11 20:53:55 +00:00
c3d341ea98
Ensure that dump calls that are associated with asserts are removed from
...
non-debug build.
llvm-svn: 29105
2006-07-11 17:58:07 +00:00
71227c23b1
In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones.
...
llvm-svn: 29096
2006-07-11 00:48:23 +00:00
a7976d329e
Implement Regression/CodeGen/PowerPC/bswap-load-store.ll by folding bswaps
...
into i16/i32 load/stores.
llvm-svn: 29089
2006-07-10 20:56:58 +00:00
59b6e8a683
Undisable ppc64 jit
...
llvm-svn: 29011
2006-07-06 17:10:42 +00:00
996795b0dd
Use hidden visibility to make symbols in an anonymous namespace get
...
dropped. This shrinks libllvmgcc.dylib another 67K
llvm-svn: 28975
2006-06-28 23:17:24 +00:00
2f8c2d8ef2
shrink libllvmgcc.dylib another 25K
...
llvm-svn: 28971
2006-06-28 22:00:36 +00:00
ca9c488528
Don't match 64-bit bitfield inserts into rlwimi's. todo add rldimi. :)
...
llvm-svn: 28944
2006-06-27 21:08:52 +00:00
f882c54505
Fix ppc64 jump tables
...
llvm-svn: 28941
2006-06-27 20:46:17 +00:00
82ab3e21b1
Print stubs for external globals right.
...
llvm-svn: 28936
2006-06-27 20:20:53 +00:00
8aed3cc46b
Implement 64-bit select, bswap, etc.
...
llvm-svn: 28935
2006-06-27 20:14:52 +00:00
a2af3f47ea
Add a pattern for i64 sra. Print 8-byte units with a space between the .quad
...
and the data
llvm-svn: 28934
2006-06-27 20:07:26 +00:00
db9a95b775
Fix rewriting frame offsets with ixaddr instructions, which implicitly shift
...
the offset two bits to the left.
llvm-svn: 28933
2006-06-27 18:55:49 +00:00
a07410c95b
PPC doesn't have bit converts to/from i64
...
llvm-svn: 28932
2006-06-27 18:40:08 +00:00
3b5873456e
Add 64-bit MTCTR so that indirect calls work.
...
llvm-svn: 28931
2006-06-27 18:36:44 +00:00
e27d51e0d8
Fix an incorrect store pattern. This fixes em3d.
...
llvm-svn: 28930
2006-06-27 18:22:50 +00:00
d48ce27532
Implement 64-bit undef, sub, shl/shr, srem/urem
...
llvm-svn: 28929
2006-06-27 18:18:41 +00:00
cb5a84f446
Use i32 for shift amounts instead of i64. This gets bisort working.
...
llvm-svn: 28927
2006-06-27 17:34:57 +00:00
f7fd88356a
Add zextload from i32 -> i64, with this, perimeter works.
...
llvm-svn: 28926
2006-06-27 17:30:08 +00:00
1df0839067
Print darwin stub stuff correctly in 64-bit mode. With this, treeadd works in
...
ppc64 mode!
llvm-svn: 28923
2006-06-27 01:02:25 +00:00
9a40cca40f
Fix variable shadowing issue
...
llvm-svn: 28922
2006-06-27 00:10:13 +00:00
97b3da1519
Implement a bunch of 64-bit cleanliness work. With this, treeadd builds (but
...
doesn't work right).
llvm-svn: 28921
2006-06-27 00:04:13 +00:00
7ecbd301b1
Rearrange compares, add ADDI8, add sext from 32-to-64 bit register
...
llvm-svn: 28920
2006-06-26 23:53:10 +00:00
ec78cade34
Improve PPC64 calling convention support
...
llvm-svn: 28919
2006-06-26 22:48:35 +00:00
b6a65f4661
Remove two more definitions
...
llvm-svn: 28918
2006-06-26 22:47:37 +00:00
86e6046515
remove two unused instructions.
...
llvm-svn: 28917
2006-06-26 22:44:13 +00:00
a7b2bd5997
Add and sort "sections" in debug lines. This always stepping through
...
code in sections other than ".text", including weak sections like ctors and
dtors.
llvm-svn: 28909
2006-06-23 12:51:53 +00:00
dc38e6f322
Correct returns of 64-bit values, though they seemed to work before...
...
llvm-svn: 28892
2006-06-21 00:34:03 +00:00
1f1b096142
Make these predicates correct in 64-bit mode too.
...
llvm-svn: 28890
2006-06-20 23:21:20 +00:00
52a956da52
Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file
...
llvm-svn: 28889
2006-06-20 23:18:58 +00:00
5705d4d519
remove unused flag
...
llvm-svn: 28888
2006-06-20 23:15:07 +00:00
9d65f3507e
add some logical ops
...
llvm-svn: 28887
2006-06-20 23:11:59 +00:00
7a856a6d88
remove some unused patterns
...
llvm-svn: 28886
2006-06-20 23:11:36 +00:00
d881f8257b
Add some more immediate patterns. This allows us to compile:
...
void test6() {
Y = 0xABCD0123BCDE4567;
}
into:
_test6:
lis r2, -21555
lis r3, ha16(_Y)
ori r2, r2, 291
rldicr r2, r2, 32, 31
oris r2, r2, 48350
ori r2, r2, 17767
std r2, lo16(_Y)(r3)
blr
llvm-svn: 28885
2006-06-20 23:03:01 +00:00
9834ad2fc6
Instead of li/xoris use li/oris. Note that this doesn't work if bit 15 is
...
set, so disable the pattern in that case.
llvm-svn: 28884
2006-06-20 22:38:59 +00:00
7e742e46ac
Add some 64-bit logical ops.
...
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation. For example, we now compile this:
static unsigned long long Y;
void test3() {
Y = 0xF0F00F00;
}
into:
_test3:
li r2, 3840
lis r3, ha16(_Y)
xoris r2, r2, 61680
std r2, lo16(_Y)(r3)
blr
GCC produces:
_test3:
li r0,0
lis r2,ha16(_Y)
ori r0,r0,61680
sldi r0,r0,16
ori r0,r0,3840
std r0,lo16(_Y)(r2)
blr
llvm-svn: 28883
2006-06-20 22:34:10 +00:00
d6e160d14d
64-bit bugfix: 0xFFFF0000 cannot be formed with a single lis.
...
llvm-svn: 28880
2006-06-20 21:39:30 +00:00
2d4e8f7e86
Add some patterns for globals, so we can now compile this:
...
static unsigned long long X, Y;
void test1() {
X = Y;
}
into:
_test1:
lis r2, ha16(_Y)
lis r3, ha16(_X)
ld r2, lo16(_Y)(r2)
std r2, lo16(_X)(r3)
blr
llvm-svn: 28879
2006-06-20 21:23:06 +00:00
868a75bec6
Remove some now-unneeded casts from instruction patterns. With the casts
...
removed, tblgen produces identical output to with them in.
llvm-svn: 28867
2006-06-20 00:39:56 +00:00
94d18df658
Add some patterns for ppc64
...
llvm-svn: 28866
2006-06-20 00:38:36 +00:00
49cadab385
Implement the getPointerRegClass method, which is required for the ptr_rc
...
magic to work.
llvm-svn: 28847
2006-06-17 00:01:04 +00:00
638ee4ee15
Upgrade some load/store instructions to use the proper addressing mode stuff.
...
llvm-svn: 28841
2006-06-16 21:29:41 +00:00
e8fe5e2bf4
In 64-bit mode, addr mode operands use G8RC instead of GPRC.
...
llvm-svn: 28840
2006-06-16 21:29:03 +00:00
a5190ae7a9
fix some assumptions that pointers can only be 32-bits. With this, we can
...
now compile:
static unsigned long X;
void test1() {
X = 0;
}
into:
_test1:
lis r2, ha16(_X)
li r3, 0
stw r3, lo16(_X)(r2)
blr
Totally amazing :)
llvm-svn: 28839
2006-06-16 21:01:35 +00:00
b429983988
Split 64-bit instructions out into a separate .td file
...
llvm-svn: 28838
2006-06-16 20:22:01 +00:00
61d703183e
Force 64-bit register availability in 64-bit mode. For real.
...
llvm-svn: 28837
2006-06-16 20:05:06 +00:00
a7d9db2fa5
Remove the -darwin and -aix llc options, inferring darwinism and aixism from
...
the target triple & subtarget info. woo.
llvm-svn: 28835
2006-06-16 18:50:48 +00:00
f3b5b92e58
Don't pass target name into TargetData anymore, it is never used or needed.
...
Remove explicit casts to std::string now that there is no overload resolution
issues in the TargetData ctors.
llvm-svn: 28830
2006-06-16 18:22:52 +00:00
16682fff2b
Document the subtarget features better, make sure that 64-bit mode, 64-bit
...
support, and 64-bit register use are all consistent with each other.
Add a new "IsPPC" feature, to distinguish ppc32 vs ppc64 targets, use this
to configure TargetData differently. This not makes ppc64 blow up on lots
of stuff :)
llvm-svn: 28825
2006-06-16 17:50:12 +00:00
a35f306740
Rename some subtarget features. A CPU now can *have* 64-bit instructions,
...
can in 32-bit mode we can choose to optionally *use* 64-bit registers.
llvm-svn: 28824
2006-06-16 17:34:12 +00:00
0c4aa14deb
First baby step towards ppc64 support. This adds a new -march=ppc64 backend
...
that is currently just like ppc32 :)
llvm-svn: 28813
2006-06-16 01:37:27 +00:00
19f964e048
1. Support standard dwarf format (was bootstrapping in Apple format.)
...
2. Add vector support.
llvm-svn: 28807
2006-06-15 20:51:43 +00:00
94bb93f8f7
Type of extract_element index operand should be iPTR.
...
llvm-svn: 28797
2006-06-15 08:18:06 +00:00
f67bec0579
Place dwarf headers at earliest possible point. Well behaved when skipping
...
functions.
llvm-svn: 28781
2006-06-14 11:35:03 +00:00
ac59ab515a
Gaar! Don't use r11 for CR save/restore, use R0. R11 can be register
...
allocated, thus live across the save/reload. This fixes
llc-beta /MultiSource/Applications/spiff/spiff
llc-beta /MultiSource/Benchmarks/sim/sim:
llc-beta /MultiSource/Benchmarks/Ptrdist/bc/bc
llc-beta /MultiSource/Benchmarks/McCat/12-IOtest/iotest:
llc-beta /MultiSource/Benchmarks/FreeBench/fourinarow/fourinarow
llc-beta /MultiSource/Benchmarks/Fhourstones-3.1/fhourstones3.1
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawdaudio/rawdaudio
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawcaudio/rawcaudio
llc-beta /MultiSource/Benchmarks/mediabench/g721/g721encode/encode
llc-beta /MultiSource/Benchmarks/mediabench/jpeg/jpeg-6a/cjpeg
and probably others, with -regalloc=local.
llvm-svn: 28761
2006-06-12 23:59:16 +00:00
6b043a24a1
Fix spilling and reloading of CR regs to reload the right values. This fixes
...
Olden/power (and probably others) with -regalloc=local.
llvm-svn: 28760
2006-06-12 21:50:57 +00:00
b055c8737f
Work around a nasty tblgen bug where it doesn't add operands for varargs
...
nodes correctly.
llvm-svn: 28745
2006-06-10 01:15:02 +00:00
006b2c6ab9
Fix a problem exposed by the local allocator. CALL instructions are not marked
...
as using incoming argument registers, so the local allocator would clobber them
between their set and use. To fix this, we give the call instructions a variable
number of uses in the CALL MachineInstr itself, so live variables understands
the live ranges of these register arguments.
llvm-svn: 28744
2006-06-10 01:14:28 +00:00
c8587d4b81
Add PowerPC intrinsics to support dcbz[l]
...
llvm-svn: 28696
2006-06-06 21:29:23 +00:00
4442a70b3a
Silence -pedantic warning
...
llvm-svn: 28633
2006-06-01 17:17:06 +00:00
b9342afa56
Always reserve space for 8 spilled GPRs. GCC apparently assumes that this
...
space will be available, even if the callee isn't varargs.
llvm-svn: 28571
2006-05-30 21:21:04 +00:00
a3add0fea8
Change RET node to include signness information of the return values. i.e.
...
RET chain, value1, sign1, value2, sign2, ...
llvm-svn: 28510
2006-05-26 23:10:12 +00:00
1fbb0d38c7
Fix build failure of povray
...
llvm-svn: 28473
2006-05-25 18:06:16 +00:00
630bbcef8d
Fix Benchmarks/MallocBench/cfrac
...
llvm-svn: 28471
2006-05-25 16:54:16 +00:00
c2cd473d9b
CALL node change (arg / sign pairs instead of just arguments).
...
llvm-svn: 28462
2006-05-25 00:57:32 +00:00
4af59dac0b
Assert if InflightSet is not cleared after instruction selecting a BB.
...
llvm-svn: 28459
2006-05-25 00:24:28 +00:00
1a8e74d113
Clear HandleMap and ReplaceMap after instruction selection. Or it may cause
...
non-deterministic behavior.
llvm-svn: 28454
2006-05-24 20:46:25 +00:00
aa2372562e
Patches to make the LLVM sources more -pedantic clean. Patch provided
...
by Anton Korobeynikov! This is a step towards closing PR786.
llvm-svn: 28447
2006-05-24 17:04:05 +00:00
33165c246c
Fix CodeGen/Generic/vector.ll:test_div with altivec.
...
llvm-svn: 28445
2006-05-24 00:15:25 +00:00
b56d22c2f6
Handle SETO* like we handle SET*, restoring behavior after Evan's setcc
...
change. This fixes PowerPC/fnegsel.ll.
llvm-svn: 28443
2006-05-24 00:06:44 +00:00
80b1b4d41e
Make TargetData strings less redundant.
...
llvm-svn: 28423
2006-05-20 23:28:54 +00:00
88812b5c0a
Make all of the TargetMachine subclasses use the new string TargetData methods.
...
This is part of the on-going work on PR 761.
llvm-svn: 28414
2006-05-20 00:24:56 +00:00
305c49579c
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
...
llvm-svn: 28378
2006-05-18 00:12:58 +00:00
dcec882286
Remove PointerType from class Target
...
llvm-svn: 28368
2006-05-17 21:20:27 +00:00
6353807fdc
Add a note about a note
...
llvm-svn: 28355
2006-05-17 19:02:25 +00:00
eb755fc1b3
Make PPC call lowering more aggressive, making the isel matching code simple
...
enough to be autogenerated.
llvm-svn: 28354
2006-05-17 19:00:46 +00:00
b1e9e37c58
Switch PPC over to a call-selection model where the lowering code creates
...
the copyto/fromregs instead of making the PPCISD::CALL selection code create
them. This vastly simplifies the selection code, and moves the ABI handling
parts into one place.
llvm-svn: 28346
2006-05-17 06:01:33 +00:00
b7552a88d6
3 changes, 2 of which are cleanup one of which changes codegen:
...
1. Rearrange code a bit so that the special case doesn't require indenting lots
of code.
2. Add comments describing PPC calling convention.
3. Only round up to 56-bytes of stack space for an outgoing call if the callee
is varargs. This saves a bit of stack space.
llvm-svn: 28342
2006-05-17 00:15:40 +00:00
f058f5aef1
implement passing/returning vector regs to calls, at least non-varargs calls.
...
llvm-svn: 28341
2006-05-16 23:54:25 +00:00
aa40ec1b32
Instead of implementing LowerCallTo directly, let the default impl produce an
...
ISD::CALL node, then custom lower that. This means that we only have to handle
LEGAL call operands/results, not every possible type. This allows us to
simplify the call code, shrinking it by about 1/3.
llvm-svn: 28339
2006-05-16 22:56:08 +00:00
26e2fcd8b1
Simplify the argument counting logic by only incrementing the index.
...
llvm-svn: 28335
2006-05-16 18:58:15 +00:00
76c47b50e7
Simplify the dead argument handling code.
...
llvm-svn: 28334
2006-05-16 18:54:32 +00:00
318f0d2122
Vector args passed in registers don't reserve stack space.
...
llvm-svn: 28333
2006-05-16 18:51:52 +00:00
4302e8fb67
Switch the PPC backend over to using FORMAL_ARGUMENTS for formal argument
...
handling. This makes the lower argument code significantly simpler (we
only need to handle legal argument types).
Incidentally, this also implements support for vector argument registers,
so long as they are not on the stack.
llvm-svn: 28331
2006-05-16 18:18:50 +00:00
d2ca9abf57
Fit in 80 cols
...
llvm-svn: 28311
2006-05-16 04:20:24 +00:00
04a9e38369
Remove some dead code, identified by coverity.
...
llvm-svn: 28303
2006-05-15 05:48:32 +00:00
ae48a894b1
Remove dead var, fix bad override.
...
llvm-svn: 28264
2006-05-12 21:09:57 +00:00
f76c42776d
remove dead variable.
...
llvm-svn: 28248
2006-05-12 17:33:59 +00:00
a296339c87
Fix PowerPC/2006-05-12-rlwimi-crash.ll
...
Nate, please verify that if InsertMask is 0, rlwimi shouldn't be used.
This fixes the crash and causes no PPC testsuite regressions.
llvm-svn: 28243
2006-05-12 16:29:37 +00:00
8c2c1e90c4
Refactor a bunch of includes so that TargetMachine.h doesn't have to include
...
TargetData.h. This should make recompiles a bit faster with my current
TargetData tinkering.
llvm-svn: 28238
2006-05-12 06:33:49 +00:00
b25cb79604
Fix the PowerPC JIT-only failure on UnitTests/Vector/sumarray-dbl, which is
...
really a bad codegen bug that LLC happens to get lucky with. I must chat with
Nate for the proper fix.
llvm-svn: 28213
2006-05-10 06:38:32 +00:00
2814134a5d
Indent .data/.text in the .s file
...
llvm-svn: 28204
2006-05-09 16:15:00 +00:00
8488ba2e41
Split SwitchSection into SwitchTo{Text|Data}Section methods.
...
llvm-svn: 28184
2006-05-09 04:59:56 +00:00
ce6646c366
Yet more readme updating
...
llvm-svn: 28172
2006-05-08 20:54:02 +00:00
68a45419cc
New note about something bad happening in target independent optimizers
...
llvm-svn: 28170
2006-05-08 20:08:28 +00:00
0eb8f2e496
Proving once again that I am not as smart as the compiler
...
llvm-svn: 28169
2006-05-08 19:09:24 +00:00
9b6d4c2968
Fold more shifts into inserts, and update the README
...
llvm-svn: 28168
2006-05-08 17:38:32 +00:00
dc996b3f6c
Update some stuff now that the new rlwimi code has gone in
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llvm-svn: 28162
2006-05-08 02:52:38 +00:00
1333cead5b
New rlwimi implementation, which is superior to the old one. There are
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still a couple missed optimizations, but we now generate all the possible
rlwimis for multiple inserts into the same bitfield. More regression tests
to come.
llvm-svn: 28156
2006-05-07 00:23:38 +00:00
8b9e11c110
Print a grouping around inline asm blocks so that we can tell when we are
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using them.
llvm-svn: 28134
2006-05-05 21:50:04 +00:00
304bbf3b1d
New note, Nate, please check to see if I'm full of it :)
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llvm-svn: 28118
2006-05-05 05:36:15 +00:00
10b71c0d08
Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.
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llvm-svn: 28104
2006-05-04 18:05:43 +00:00
10d6341618
Move some methods out of MachineInstr into MachineOperand
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llvm-svn: 28102
2006-05-04 17:52:23 +00:00
fef7a2d0f5
There shalt be only one "immediate" operand type!
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llvm-svn: 28099
2006-05-04 17:21:20 +00:00
13d5f3eb05
Revert Nate's CR patch from last night, which caused many regressions (e.g. fhourstones).
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Loading and storing off R0 isn't what we wanted. Also, taking some CR's out of
CRRC seems to cause failures as well. Further investigation is required.
llvm-svn: 28097
2006-05-04 16:56:45 +00:00
940cc978ef
Remove a bunch more SparcV9 specific stuff
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llvm-svn: 28093
2006-05-04 01:15:02 +00:00
9f6639b64d
Remove some more unused stuff from MachineInstr that was leftover from V9.
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llvm-svn: 28091
2006-05-04 00:44:25 +00:00
e3a9c70ba0
Change from using MachineRelocation ctors to using static methods
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in MachineRelocation to create Relocations.
llvm-svn: 28088
2006-05-03 20:30:20 +00:00
1d8ee1fc80
Suck block address tracking out of targets into the JIT Emitter. This
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simplifies the MachineCodeEmitter interface just a little bit and makes
BasicBlocks work like constant pools and jump tables.
llvm-svn: 28082
2006-05-03 17:10:41 +00:00
20a631fde7
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
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This fixes PR 759.
llvm-svn: 28074
2006-05-03 01:29:57 +00:00
d8b192ba3b
Change the BasicBlockAddrs map to be a vector, indexed by MBB number.
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llvm-svn: 28069
2006-05-03 00:32:55 +00:00
b8065a9a3a
Several related changes:
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1. Change several methods in the MachineCodeEmitter class to be pure virtual.
2. Suck emitConstantPool/initJumpTableInfo into startFunction, removing them
from the MachineCodeEmitter interface, and reducing the amount of target-
specific code.
3. Change the JITEmitter so that it allocates constantpools and jump tables
*right* next to the functions that they belong to, instead of in a separate
pool of memory. This makes all memory for a function be contiguous, and
means the JITEmitter only tracks one block of memory now.
llvm-svn: 28065
2006-05-02 23:22:24 +00:00
e1c96369e2
Fix a purely hypothetical problem (for now): emitWord emits in the host
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byte format. This doesn't work when using the code emitter in a cross target
environment. Since the code emitter is only really used by the JIT, this
isn't a current problem, but if we ever start emitting .o files, it would be.
llvm-svn: 28060
2006-05-02 19:14:47 +00:00
c9aa3715e8
Refactor the machine code emitter interface to pull the pointers for the current
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code emission location into the base class, instead of being in the derived classes.
This change means that low-level methods like emitByte/emitWord now are no longer
virtual (yaay for speed), and we now have a framework to support growable code
segments. This implements feature request #1 of PR469.
llvm-svn: 28059
2006-05-02 18:27:26 +00:00
bbcbf48aab
Since we don't handle callee-save CRs right yet, don't allocate them. Also
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don't step on R11 in the middle of a function when saving and restoring CRs
llvm-svn: 28058
2006-05-02 17:37:31 +00:00
287dc5be0d
Hooray, everyone now uses the same printBasicBlockLabel implementation
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llvm-svn: 28056
2006-05-02 17:34:51 +00:00
b9d4f8324d
Extend printBasicBlockLabel a bit so that it can be used to print all
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basic block labels, consolidating the code to do so in one place for each
target.
llvm-svn: 28050
2006-05-02 05:37:32 +00:00
01364fbba8
Update the PPC compilation callback code to not need weird abi-violating
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prologs and epilogs, keep all the asm in one place, and remove use of
compiler builtin functions.
llvm-svn: 28049
2006-05-02 04:50:05 +00:00
84b49d51be
Fix CodeGen/Generic/2006-04-28-Sign-extend-bool.ll
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llvm-svn: 28017
2006-04-28 21:56:10 +00:00
a4c2c4a276
Add a note
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llvm-svn: 27999
2006-04-28 00:04:05 +00:00
318bb96f9e
No functionality changes, but cleaner code with correct comments.
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llvm-svn: 27966
2006-04-25 04:45:59 +00:00
4ca2ea5b43
JumpTable support! What this represents is working asm and jit support for
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x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
llvm-svn: 27947
2006-04-22 18:53:45 +00:00
c8afdfec52
Teach the JIT how to relocate LI, this fixes the JIT on Prolangs-C/TimberWolfMC
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llvm-svn: 27943
2006-04-22 06:17:56 +00:00
57a32f0bc1
Fix the comment
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llvm-svn: 27938
2006-04-21 22:11:27 +00:00
516b393992
Change the PPC JIT to use a Static relocation model
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llvm-svn: 27937
2006-04-21 22:04:15 +00:00
99d3da9d2c
Fix the CodeGen/PowerPC/buildvec_canonicalize.ll regression last night.
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llvm-svn: 27908
2006-04-20 19:01:30 +00:00
0cd0065c58
Make sure that the new instructions selected have the right type. This fixes
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CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll
llvm-svn: 27868
2006-04-20 05:58:10 +00:00
Chris Lattner