Chris Lattner
c9fa36d706
implement preinc support for r+i loads on ppc64
...
llvm-svn: 31654
2006-11-10 23:58:45 +00:00
Evan Cheng
ab51cf2e78
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
...
llvm-svn: 30945
2006-10-13 21:14:26 +00:00
Evan Cheng
e71fe34d75
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
...
llvm-svn: 30844
2006-10-09 20:57:25 +00:00
Chris Lattner
78370606d0
Shift amounts are always 32-bits, even in 64-bit mode. This fixes
...
CodeGen/PowerPC/2006-09-28-shift_64.ll
llvm-svn: 30652
2006-09-28 20:48:45 +00:00
Chris Lattner
b00b6c2e86
Make the implicit def instructions look like other instrs.
...
llvm-svn: 29174
2006-07-18 16:33:26 +00:00
Chris Lattner
96aecb5d76
Add missing PPC64 extload/truncstores
...
llvm-svn: 29140
2006-07-14 04:42:02 +00:00
Chris Lattner
ca9c488528
Don't match 64-bit bitfield inserts into rlwimi's. todo add rldimi. :)
...
llvm-svn: 28944
2006-06-27 21:08:52 +00:00
Chris Lattner
a2af3f47ea
Add a pattern for i64 sra. Print 8-byte units with a space between the .quad
...
and the data
llvm-svn: 28934
2006-06-27 20:07:26 +00:00
Chris Lattner
3b5873456e
Add 64-bit MTCTR so that indirect calls work.
...
llvm-svn: 28931
2006-06-27 18:36:44 +00:00
Chris Lattner
e27d51e0d8
Fix an incorrect store pattern. This fixes em3d.
...
llvm-svn: 28930
2006-06-27 18:22:50 +00:00
Chris Lattner
d48ce27532
Implement 64-bit undef, sub, shl/shr, srem/urem
...
llvm-svn: 28929
2006-06-27 18:18:41 +00:00
Chris Lattner
f7fd88356a
Add zextload from i32 -> i64, with this, perimeter works.
...
llvm-svn: 28926
2006-06-27 17:30:08 +00:00
Chris Lattner
7ecbd301b1
Rearrange compares, add ADDI8, add sext from 32-to-64 bit register
...
llvm-svn: 28920
2006-06-26 23:53:10 +00:00
Chris Lattner
52a956da52
Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file
...
llvm-svn: 28889
2006-06-20 23:18:58 +00:00
Chris Lattner
9d65f3507e
add some logical ops
...
llvm-svn: 28887
2006-06-20 23:11:59 +00:00
Chris Lattner
d881f8257b
Add some more immediate patterns. This allows us to compile:
...
void test6() {
Y = 0xABCD0123BCDE4567;
}
into:
_test6:
lis r2, -21555
lis r3, ha16(_Y)
ori r2, r2, 291
rldicr r2, r2, 32, 31
oris r2, r2, 48350
ori r2, r2, 17767
std r2, lo16(_Y)(r3)
blr
llvm-svn: 28885
2006-06-20 23:03:01 +00:00
Chris Lattner
9834ad2fc6
Instead of li/xoris use li/oris. Note that this doesn't work if bit 15 is
...
set, so disable the pattern in that case.
llvm-svn: 28884
2006-06-20 22:38:59 +00:00
Chris Lattner
7e742e46ac
Add some 64-bit logical ops.
...
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation. For example, we now compile this:
static unsigned long long Y;
void test3() {
Y = 0xF0F00F00;
}
into:
_test3:
li r2, 3840
lis r3, ha16(_Y)
xoris r2, r2, 61680
std r2, lo16(_Y)(r3)
blr
GCC produces:
_test3:
li r0,0
lis r2,ha16(_Y)
ori r0,r0,61680
sldi r0,r0,16
ori r0,r0,3840
std r0,lo16(_Y)(r2)
blr
llvm-svn: 28883
2006-06-20 22:34:10 +00:00
Chris Lattner
2d4e8f7e86
Add some patterns for globals, so we can now compile this:
...
static unsigned long long X, Y;
void test1() {
X = Y;
}
into:
_test1:
lis r2, ha16(_Y)
lis r3, ha16(_X)
ld r2, lo16(_Y)(r2)
std r2, lo16(_X)(r3)
blr
llvm-svn: 28879
2006-06-20 21:23:06 +00:00
Chris Lattner
94d18df658
Add some patterns for ppc64
...
llvm-svn: 28866
2006-06-20 00:38:36 +00:00
Chris Lattner
638ee4ee15
Upgrade some load/store instructions to use the proper addressing mode stuff.
...
llvm-svn: 28841
2006-06-16 21:29:41 +00:00
Chris Lattner
a5190ae7a9
fix some assumptions that pointers can only be 32-bits. With this, we can
...
now compile:
static unsigned long X;
void test1() {
X = 0;
}
into:
_test1:
lis r2, ha16(_X)
li r3, 0
stw r3, lo16(_X)(r2)
blr
Totally amazing :)
llvm-svn: 28839
2006-06-16 21:01:35 +00:00
Chris Lattner
b429983988
Split 64-bit instructions out into a separate .td file
...
llvm-svn: 28838
2006-06-16 20:22:01 +00:00