4 Commits

Author	SHA1	Message	Date
Tim Northover	64ec0ff433	X86: use sub-register sequences for MOV*r0 operations ... Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. llvm-svn: 182928	2013-05-30 13:19:42 +00:00
Preston Gurd	8b7ab4ba2b	This patch adds the X86FixupLEAs pass, which will reduce instruction ... latency for certain models of the Intel Atom family, by converting instructions into their equivalent LEA instructions, when it is both useful and possible to do so. llvm-svn: 180573	2013-04-25 20:29:37 +00:00
Preston Gurd	f2ea70ae4a	Fix remaining lit tests which were failing when run on an Atom ... processor. Patches by Tyler Nowicki, Andy Zhang, and Preston Gurd! llvm-svn: 160520	2012-07-19 18:53:21 +00:00
Dan Gohman	c88fda477a	Fix X86's isLegalAddressingMode to recognize that static addresses ... need not be RIP-relative in small mode. llvm-svn: 111917	2010-08-24 15:55:12 +00:00