f3be7a7ea7
Bug: rcpps can only folds a load if the address is 16-byte aligned. Fixed many 'ps' load folding patterns in X86InstrSSE.td which are missing the proper alignment checks.
...
Also fixed some 80 col. violations.
llvm-svn: 51462
2008-05-23 00:37:07 +00:00
6b4dcc1c14
Put const weak stuff in appropriate section on Darwin.
...
g++.dg/abi/key2.C
llvm-svn: 51458
2008-05-23 00:16:59 +00:00
97b020e61e
X86CodeEmitter should not set PIC style to None at initialization time. This will break codegen if relocation model is changed to PIC_ later.
...
llvm-svn: 51455
2008-05-22 23:55:24 +00:00
53963b775e
Add missing patterns.
...
llvm-svn: 51435
2008-05-22 18:56:56 +00:00
3d1797ccaa
fix an off-by-one error in my previous patch, don't treat the callee as a incoming arg.
...
llvm-svn: 51422
2008-05-22 06:29:38 +00:00
79be90c3c7
Add support for multiple-return values in inline asm. This should
...
get inline asm working as well as it did previously with the CBE
with the new MRV support for inline asm.
llvm-svn: 51420
2008-05-22 06:19:37 +00:00
f945f94397
movsd and movq do not require 16-byte alignment. This fixes vec_set-5.ll on Linux.
...
llvm-svn: 51327
2008-05-20 18:24:47 +00:00
974722b16f
runOnMachineFunction should set IsPIC because relocation model may have been changed.
...
llvm-svn: 51291
2008-05-20 01:56:59 +00:00
5bf742f2aa
Handle quoted names when constructing $stub's,
...
$non_lazy_ptr's and $lazy_ptr's.
llvm-svn: 51277
2008-05-19 21:38:18 +00:00
1bafa6c886
trip count computation deficiency
...
llvm-svn: 51222
2008-05-17 15:37:38 +00:00
2e1d5e487b
Record weak external linkage in a case where we were
...
missing it. gcc.dg/darwin-weakimport-2.c.
Handle common and weak differently for darwin ppc32.
llvm-svn: 51201
2008-05-16 20:09:25 +00:00
e1f6e4b21d
API change for {BinaryOperator|CmpInst|CastInst}::create*() --> Create. Legacy interfaces will be in place for some time. (Merge from use-diet branch.)
...
llvm-svn: 51200
2008-05-16 19:29:10 +00:00
876dd3ca9e
Treat common as distinct from weak global on Darwin x86.
...
llvm-svn: 51172
2008-05-16 00:52:06 +00:00
29e59ad6c9
Fix typos and comments.
...
llvm-svn: 51165
2008-05-15 22:13:02 +00:00
ef377adca0
Make use of vector load and store operations to implement memcpy, memmove, and memset. Currently only X86 target is taking advantage of these.
...
llvm-svn: 51140
2008-05-15 08:39:06 +00:00
ad2b7a7b97
Silence warnings.
...
llvm-svn: 51129
2008-05-14 20:33:21 +00:00
ce4396bc92
Add CommonLinkage; currently tentative definitions
...
are represented as "weak", but there are subtle differences
in some cases on Darwin, so we need both. The intent
is that "common" will behave identically to "weak" unless
somebody changes their target to do something else.
No functional change as yet.
llvm-svn: 51118
2008-05-14 20:12:51 +00:00
7fc6027873
Detabification. Fixed indentation and spacing.
...
Changed cout to DOUT, and TODOs to FIXMEs.
Other changes as per coding conventions.
llvm-svn: 51105
2008-05-14 11:31:39 +00:00
fbdca96469
Fix typo in ParameterAttribute fields usage. Add an include
...
to make the Cpp backend output compilable.
llvm-svn: 51095
2008-05-14 07:52:03 +00:00
1f8c9ef4cc
Fixed the file description header at the top to remove the developer name.
...
llvm-svn: 51094
2008-05-14 06:50:01 +00:00
6f34ed0d36
Doh. Alignment is in bytes, not in bits.
...
llvm-svn: 51092
2008-05-14 02:49:43 +00:00
eabd647cd5
Change target-specific classes to use more precise static types.
...
This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.
llvm-svn: 51091
2008-05-14 01:58:56 +00:00
03ce206143
add a note
...
llvm-svn: 51062
2008-05-13 19:56:20 +00:00
f8ab712fa9
- Fix the pasto in the fix for a previous pasto.
...
- Incorporate Chris' comment suggestion.
llvm-svn: 51061
2008-05-13 18:59:59 +00:00
d17f58ae6e
add a note
...
llvm-svn: 51060
2008-05-13 18:48:54 +00:00
6645714f16
Fix one more encoding bug.
...
llvm-svn: 51057
2008-05-13 17:52:09 +00:00
595e226085
- Don't treat anyext 16-bit load as a 32-bit load if it's volatile.
...
- Correct a pasto.
llvm-svn: 51054
2008-05-13 16:45:56 +00:00
4394c2376c
Adding files for Microchip's PIC16 target.
...
A brief description about PIC16:
===============================
PIC16 is an 8-bit microcontroller with only one 8-bit register which is the
accumulator. All arithmetic/load/store operations are 8-bit only.
The architecture has two address spaces: program and data. The program memory
is divided into 2K pages and the data memory is divided into banks of 128 byte, with only 80 usable bytes, resulting in an non-contiguous data memory.
It supports direct data memory access (by specifying the address as part of the instruction) and indirect data and program memory access (in an unorthodox fashion which utilize a 16 bit pointer register).
Two classes of registers exist: (8-bit class which is only one
accumulator) (16-bit class, which contains one or more 16 bit
pointer(s))
llvm-svn: 51027
2008-05-13 09:02:57 +00:00
1120279ae6
Instead of a vector load, shuffle and then extract an element. Load the element from address with an offset.
...
pshufd $1, (%rdi), %xmm0
movd %xmm0, %eax
=>
movl 4(%rdi), %eax
llvm-svn: 51026
2008-05-13 08:35:03 +00:00
50f7ef30bb
Fix and encoding error in the psrad xmm, imm8 instruction.
...
llvm-svn: 51020
2008-05-13 01:47:52 +00:00
3f40c69083
On x86, it's safe to treat i32 load anyext as a normal i32 load. Ditto for i8 anyext load to i16.
...
llvm-svn: 51019
2008-05-13 00:54:02 +00:00
d78c400b5b
Clean up the use of static and anonymous namespaces. This turned up
...
several things that were neither in an anonymous namespace nor static
but not intended to be global.
llvm-svn: 51017
2008-05-13 00:00:25 +00:00
b87e63a730
Teach Legalize how to scalarize VSETCC
...
Teach X86 a few more vsetcc patterns. Custom lowering for unsupported ones is next.
llvm-svn: 51009
2008-05-12 23:09:43 +00:00
b980f6fb3d
Xform bitconvert(build_pair(load a, load b)) to a single load if the load locations are at the right offset from each other.
...
llvm-svn: 51008
2008-05-12 23:04:07 +00:00
1e11768a4f
Constify the machine instruction passed into the
...
"is{Trivially,Really}ReMaterializable" methods.
llvm-svn: 51001
2008-05-12 20:54:26 +00:00
d875c3e2fd
Initial X86 codegen support for VSETCC.
...
llvm-svn: 51000
2008-05-12 20:34:32 +00:00
0863b19ae6
Fix a copy+paste bug; pseudo-instructions shouldn't have
...
encoding information.
llvm-svn: 50997
2008-05-12 20:22:45 +00:00
2609d5e779
Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it.
...
llvm-svn: 50991
2008-05-12 19:56:52 +00:00
cfcb56091b
Add support for vicmp/vfcmp codegen, more legalize support coming.
...
This is necessary to unbreak the build.
llvm-svn: 50988
2008-05-12 19:40:03 +00:00
906716c40f
Fix a compile error on compilers that still want a return value
...
in a non-void function that calls abort.
llvm-svn: 50969
2008-05-12 16:17:19 +00:00
a38e72d247
Add note
...
llvm-svn: 50959
2008-05-11 14:33:15 +00:00
71b9afb053
When transforming a vector_shuffle to a load, the base address must not be an undef.
...
llvm-svn: 50940
2008-05-10 06:46:49 +00:00
3c0e11af64
For now, abort when an ISD::VAARG is encountered on x86-64, rather
...
than silently generate invalid code.
llvm-gcc does not currently use VAArgInst; it lowers va_arg in the
front-end.
llvm-svn: 50930
2008-05-10 01:26:14 +00:00
da2587cedc
Some clean up.
...
llvm-svn: 50929
2008-05-10 00:59:18 +00:00
bb48d55a88
If movl top bits are undef, let it be selected to movlps, etc.
...
llvm-svn: 50928
2008-05-10 00:58:41 +00:00
867af2678f
Add a pattern to do move the low element of a v4f32 and zero extend the rest.
...
llvm-svn: 50922
2008-05-09 23:37:55 +00:00
961339bbdb
Handle a few more cases of folding load i64 into xmm and zero top bits.
...
Note, some of the code will be moved into target independent part of DAG combiner in a subsequent patch.
llvm-svn: 50918
2008-05-09 21:53:03 +00:00
0360ecbec1
Use movq to move low half of XMM register and zero-extend the rest.
...
llvm-svn: 50874
2008-05-08 22:35:02 +00:00
78af38c392
Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine.
...
llvm-svn: 50838
2008-05-08 00:57:18 +00:00
e2b0bf43a7
Output correct exception handling and frame info
...
on x86-64 linux. This causes no regressions on
32 bit linux and 32 bit ppc. More tests pass
on 64 bit ppc with no regressions. I didn't
turn on eh on 64 bit linux because the intrinsics
needed to compile the eh runtime aren't done
yet. But if you turn it on and link with the
mainline runtime then eh seems to work fine
on x86-64 linux with this patch. Thanks to
Dale for testing. The main point of the patch
is that if you output that some object is
encoded using 4 bytes you had better not output
8 bytes for it: the patch makes everything
consistent.
llvm-svn: 50825
2008-05-07 19:11:09 +00:00
888594bdf4
Match things like 'armv5tejl-unknown-linux-gnu' for PR2290
...
llvm-svn: 50698
2008-05-06 02:29:28 +00:00
6a2da37c0e
Make several variable declarations static.
...
llvm-svn: 50696
2008-05-06 01:53:16 +00:00
6e2bf7c67e
add a micro optzn.
...
llvm-svn: 50681
2008-05-05 23:19:45 +00:00
310a38d51e
Improved generated code for atomic operators
...
llvm-svn: 50677
2008-05-05 22:56:23 +00:00
dbfcce37fe
Code clean up. No functionality change.
...
llvm-svn: 50675
2008-05-05 22:12:23 +00:00
3e58393c3d
Added addition atomic instrinsics and, or, xor, min, and max.
...
llvm-svn: 50663
2008-05-05 19:05:59 +00:00
b42c28c3dc
Fix IsLinux being uninitialized on non-Linux targets.
...
llvm-svn: 50660
2008-05-05 18:43:07 +00:00
4b0386ce62
Fix 80col violation
...
llvm-svn: 50654
2008-05-05 17:08:59 +00:00
6fd71c6512
Use a dedicated IsLinux flag instead of an ELFLinux TargetType.
...
llvm-svn: 50649
2008-05-05 16:11:31 +00:00
bcde172222
Add AsmPrinter support for emitting a directive to declare that
...
the code being generated does not require an executable stack.
Also, add target-specific code to make use of this on Linux
on x86.
llvm-svn: 50634
2008-05-05 00:28:39 +00:00
9205c8562c
Add General Dynamic TLS model for X86-64. Some parts looks really ugly (look for tlsaddr pattern),
...
but should work. Work is in progress, more models will follow
llvm-svn: 50630
2008-05-04 21:36:32 +00:00
d9481366e3
Select vector shift with non-immediate i32 shift amount operand by first moving the operand into the right register.
...
llvm-svn: 50619
2008-05-04 09:15:50 +00:00
cdf22f2953
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code.
...
llvm-svn: 50601
2008-05-03 00:52:09 +00:00
fa8f9f937a
Undo r50574. We are already ensuring the folded load address is 16-byte aligned.
...
llvm-svn: 50578
2008-05-02 17:01:01 +00:00
4f9cd9181e
80 column violation.
...
llvm-svn: 50575
2008-05-02 07:53:32 +00:00
50f82f2c8e
Not safe folding a load + FsXORPSrr into FsXORPSrm. It's loading a FR64 value but the load folding variant expects a 16-byte aligned address.
...
llvm-svn: 50574
2008-05-02 07:50:58 +00:00
be0de34ede
Tail call optimization improvements:
...
Move platform independent code (lowering of possibly overwritten
arguments, check for tail call optimization eligibility) from
target X86ISelectionLowering.cpp to TargetLowering.h and
SelectionDAGISel.cpp.
Initial PowerPC tail call implementation:
Support ppc32 implemented and tested (passes my tests and
test-suite llvm-test).
Support ppc64 implemented and half tested (passes my tests).
On ppc tail call optimization is performed if
caller and callee are fastcc
call is a tail call (in tail call position, call followed by ret)
no variable argument lists or byval arguments
option -tailcallopt is enabled
Supported:
* non pic tail calls on linux/darwin
* module-local tail calls on linux(PIC/GOT)/darwin(PIC)
* inter-module tail calls on darwin(PIC)
If constraints are not met a normal call will be emitted.
A test checking the argument lowering behaviour on x86-64 was added.
llvm-svn: 50477
2008-04-30 09:16:33 +00:00
c3a1910a07
Bug fixes and updates for CellSPU, syncing up with trunk. Most notable
...
fixes are target-specific lowering of frame indices, fix constants generated
for the FSMBI instruction, and fixing SPUTargetLowering::computeMaskedBitsFor-
TargetNode().
llvm-svn: 50462
2008-04-30 00:30:08 +00:00
0acc739817
Don't do stupid things: doInitialization(Module&) is not applicable to ModulePass :)
...
llvm-svn: 50433
2008-04-29 18:16:22 +00:00
da44054867
Fix the SVOffset values for loads and stores produced by
...
memcpy/memset expansion. It was a bug for the SVOffset value
to be used in the actual address calculations.
llvm-svn: 50359
2008-04-28 17:15:20 +00:00
fac70f2f44
Fix FP return for Win64 ABI
...
llvm-svn: 50342
2008-04-28 07:40:07 +00:00
e183b3cd76
Properly lower vararg's FORMAL_ARGUMENTS node on win64
...
llvm-svn: 50325
2008-04-27 23:15:03 +00:00
b5096e9c73
Handle fp80 for win64
...
llvm-svn: 50324
2008-04-27 22:54:09 +00:00
724539c001
A few inline asm cleanups:
...
- Make targetlowering.h fit in 80 cols.
- Make LowerAsmOperandForConstraint const.
- Make lowerXConstraint -> LowerXConstraint
- Make LowerXConstraint return a const char* instead of taking a string byref.
llvm-svn: 50312
2008-04-26 23:02:14 +00:00
b4224cda3b
no need to implement this method and just have it call
...
the default impl.
llvm-svn: 50311
2008-04-26 22:59:59 +00:00
1e78184a99
Extract the lower 64-bit if a MMX value is passed in a XMM register.
...
llvm-svn: 50292
2008-04-25 20:13:28 +00:00
5ba02020e6
Fix illegal MMX_MOVDQ2Qrr pattern. vector_extract result must be a scalar value.
...
llvm-svn: 50291
2008-04-25 20:12:46 +00:00
ccde6dd016
Special handling for MMX values being passed in either GPR64 or lower 64-bits of XMM registers.
...
llvm-svn: 50289
2008-04-25 19:11:04 +00:00
6d653b58f9
Fix MMX_MOVQ2DQrr pattern. It's illegal to do a bitconvert from a smaller type to a larger one.
...
llvm-svn: 50278
2008-04-25 18:19:54 +00:00
33bd24bd92
add a note
...
llvm-svn: 50267
2008-04-25 17:25:00 +00:00
715eaa031c
80 col violation.
...
llvm-svn: 50266
2008-04-25 17:21:40 +00:00
59834d1c7a
Not checking for intrinsics which do not have a chain operand.
...
llvm-svn: 50260
2008-04-25 08:55:28 +00:00
051da5deaa
- Switch from std::set to SmallPtrSet.
...
- Add comments.
llvm-svn: 50259
2008-04-25 08:22:20 +00:00
df38b35a1e
MMX argument passing fixes:
...
On Darwin / Linux x86-32, v8i8, v4i16, v2i32 values are passed in MM[0-2].
On Darwin / Linux x86-32, v1i64 values are passed in memory.
On Darwin x86-64, v8i8, v4i16, v2i32 values are passed in XMM[0-7].
On Darwin x86-64, v1i64 values are passed in 64-bit GPRs.
llvm-svn: 50257
2008-04-25 07:56:45 +00:00
741c7a3b49
Loosen up an assertion to allow intrinsics. I really have no
...
idea what this code (findNonImmUse) does, so I'm only guessing
that this is the right thing. It would be really really nice
if this had comments and perhaps switched to SmallPtrSet
(hint hint) :)
This fixes rdar://5886601, a crash on gcc.target/i386/sse4_1-pblendw.c
llvm-svn: 50252
2008-04-25 05:13:01 +00:00
9165e165dc
Fix bug in x86 memcpy / memset lowering. If there are trailing bytes not handled by rep instructions, a new memcpy / memset is introduced for them. However, since source / destination addresses are already adjusted, their offsets should be zero.
...
llvm-svn: 50239
2008-04-25 00:26:43 +00:00
c107d0020d
Make these variables static.
...
llvm-svn: 50196
2008-04-23 23:15:23 +00:00
1ae135c87b
Drop dead includes
...
llvm-svn: 50192
2008-04-23 22:44:03 +00:00
9dcc3e97a4
Adjust option names for C++ backend
...
llvm-svn: 50190
2008-04-23 22:37:03 +00:00
78695035c4
First step of implementing PR1538: move llvm2cpp logic to new 'target'
...
llvm-svn: 50189
2008-04-23 22:29:24 +00:00
d871fa5cb6
Initial CBE support for multiple return values.
...
llvm-svn: 50187
2008-04-23 21:49:29 +00:00
0d6df367f1
Fix typo
...
llvm-svn: 50169
2008-04-23 18:24:25 +00:00
965babda19
Only allow increase of max alignment value
...
llvm-svn: 50168
2008-04-23 18:23:50 +00:00
c1534dca56
Be over-conservative: scan for all used virtual registers and calculate maximal stack alignment in assumption, that there will be spill of vector register.
...
llvm-svn: 50167
2008-04-23 18:23:30 +00:00
2659011b70
Add X86 Maximal Stack Alignment Calculator Pass before RA
...
llvm-svn: 50166
2008-04-23 18:23:05 +00:00
156550ae79
Do proper book-keeping of offsets and prologue/epilogue code for stack realignment
...
llvm-svn: 50163
2008-04-23 18:21:27 +00:00
89a0a017fb
If stack realignment is used - incoming args will use EBP as base register and locals - ESP
...
llvm-svn: 50162
2008-04-23 18:21:02 +00:00
ba5129073c
Eastimate required stack alignment early, so we can decide, whether we will need frame pointer or not
...
llvm-svn: 50161
2008-04-23 18:20:17 +00:00
c756b460d9
Cleanup
...
llvm-svn: 50159
2008-04-23 18:19:23 +00:00
a8aac3db3f
Simplify
...
llvm-svn: 50158
2008-04-23 18:18:36 +00:00
cb195f511d
Make stack alignment options global for all targets
...
llvm-svn: 50157
2008-04-23 18:18:10 +00:00
9328fbc4c7
Provide option for enabling-disabling stack realignment
...
llvm-svn: 50156
2008-04-23 18:17:11 +00:00
ca150edda6
Disable stack realignment for functions with dynamic-sized alloca's
...
llvm-svn: 50155
2008-04-23 18:16:43 +00:00
a7495260ee
Provide ABI-correct stack alignment
...
llvm-svn: 50154
2008-04-23 18:16:16 +00:00
8843487e16
Provide convenient helpers for some operations
...
llvm-svn: 50153
2008-04-23 18:15:48 +00:00
2ccafa47ac
Whitespace cleanup
...
llvm-svn: 50152
2008-04-23 18:15:11 +00:00
f166d2d0d6
Implement an x86-64 ABI detail of passing structs by hidden first
...
argument. The x86-64 ABI requires the incoming value of %rdi to
be copied to %rax on exit from a function that is returning a
large C struct.
Also, add a README-X86-64 entry detailing the missed optimization
opportunity and proposing an alternative approach.
llvm-svn: 50075
2008-04-21 23:59:07 +00:00
db08f5218e
Fix the encoding of the MMX movd that moves from MMX to 64-bit GPR.
...
llvm-svn: 50053
2008-04-21 19:52:29 +00:00
a89143f1e0
Add an ugly note.
...
llvm-svn: 50029
2008-04-21 04:46:30 +00:00
984e7199cc
Don't forget to update the current operand when getting the size of an instruction.
...
llvm-svn: 50007
2008-04-20 23:36:47 +00:00
470ab00c76
A better fix for my previous patch, MOVZQI2PQIrr just requires SSE2.
...
llvm-svn: 49986
2008-04-20 05:52:46 +00:00
3b18762f40
Switch to using Simplified ConstantFP::get API.
...
llvm-svn: 49977
2008-04-20 00:41:09 +00:00
5102bd9359
64-bit atomic operations.
...
llvm-svn: 49949
2008-04-19 02:30:38 +00:00
5e7ee0a002
Also LXCHG64 -> XCHG64rm.
...
llvm-svn: 49948
2008-04-19 02:05:42 +00:00
51096affb5
PPC32 atomic operations.
...
llvm-svn: 49947
2008-04-19 01:30:48 +00:00
7f4240a47c
xchg which references a memory operand does not need to lock prefix. Atomicity is guaranteed.
...
llvm-svn: 49946
2008-04-19 01:20:30 +00:00
ad4071a9e1
Fix the handling of va_copy on x86-64. As of llvm-gcc r49920
...
llvm-gcc is now lowering va_copy on x86-64, so this completes
the fix for PR2230.
llvm-svn: 49922
2008-04-18 20:55:41 +00:00
00bd8d904a
- Fix atomic operation JIT encoding.
...
- Remove unused instructions.
llvm-svn: 49921
2008-04-18 20:55:36 +00:00
5879213597
Also support Intel asm syntax.
...
llvm-svn: 49878
2008-04-17 23:35:10 +00:00
4704baa555
Fix assembly code for atomic operations.
...
llvm-svn: 49869
2008-04-17 21:26:35 +00:00
147cb764b5
Don't forget about sub-register indices when rematting instructions.
...
llvm-svn: 49830
2008-04-16 23:44:44 +00:00
c1279f5e4b
Unbreak build on x86-64.
...
llvm-svn: 49822
2008-04-16 22:24:33 +00:00
a7557dfe71
Correlate stubs with functions in JIT: when emitting a stub, the JIT tells the memory manager which function
...
the stub will resolve.
llvm-svn: 49814
2008-04-16 20:46:05 +00:00
ae84bbdbed
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
...
llvm-svn: 49809
2008-04-16 20:10:13 +00:00
a15cee1036
Initialize X863DNowLevel.
...
llvm-svn: 49808
2008-04-16 19:03:02 +00:00
a3ee1a38a3
Ongoing work on improving the instruction selection infrastructure:
...
Rename SDOperandImpl back to SDOperand.
Introduce the SDUse class that represents a use of the SDNode referred by
an SDOperand. Now it is more similar to Use/Value classes.
Patch is approved by Dan Gohman.
llvm-svn: 49795
2008-04-16 16:15:27 +00:00
d43d3beeb0
Add support for the form of the SSE41 extractps instruction that
...
puts its result in a 32-bit GPR.
llvm-svn: 49762
2008-04-16 02:32:24 +00:00
8c99ccaf96
Recreate the size SDNode instead of reusing the old one in the x86
...
memcpy lowering code; this ensures that the size node has the desired
result type. This fixes a regression from r49572 with @llvm.memcpy.i64
on x86-32.
llvm-svn: 49761
2008-04-16 01:32:32 +00:00
3dd8ba6235
Remove X86_64SRet; it isn't used anymore.
...
llvm-svn: 49759
2008-04-16 00:24:30 +00:00
01a5d36d9d
Add movd instructions to move from MMX registers
...
to 64-bit GPR registers on x86-64.
llvm-svn: 49757
2008-04-15 23:55:07 +00:00
7000c8f1aa
Change Divided flag to Split, as suggested by Evan
...
llvm-svn: 49715
2008-04-15 08:08:50 +00:00
4fff979a43
Remove unnecessary <sstream> includes.
...
llvm-svn: 49681
2008-04-14 20:40:47 +00:00
2505d86783
Fix const-correctness issues with the SrcValue handling in the
...
memory intrinsic expansion code.
llvm-svn: 49666
2008-04-14 17:55:48 +00:00
876224b1e8
Reverse sense of unwind-tables option. This means
...
stack tracebacks on Darwin x86-64 won't work by default;
nevertheless, everybody but me thinks this is a good idea.
llvm-svn: 49663
2008-04-14 17:54:17 +00:00
dcc2eda5fc
Add a divided flag for the first piece of an argument divided into mulitple parts. Fixes PR1643
...
llvm-svn: 49611
2008-04-13 13:40:22 +00:00
b9f38f38fa
Provide option for stack alignment override
...
llvm-svn: 49593
2008-04-12 22:12:22 +00:00
634fc9a33a
This patch corrects the handling of byval arguments for tailcall
...
optimized x86-64 (and x86) calls so that they work (... at least for
my test cases).
Should fix the following problems:
Problem 1: When i introduced the optimized handling of arguments for
tail called functions (using a sequence of copyto/copyfrom virtual
registers instead of always lowering to top of the stack) i did not
handle byval arguments correctly e.g they did not work at all :).
Problem 2: On x86-64 after the arguments of the tail called function
are moved to their registers (which include ESI/RSI etc), tail call
optimization performs byval lowering which causes xSI,xDI, xCX
registers to be overwritten. This is handled in this patch by moving
the arguments to virtual registers first and after the byval lowering
the arguments are moved from those virtual registers back to
RSI/RDI/RCX.
llvm-svn: 49584
2008-04-12 18:11:06 +00:00
544ab2c50b
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
...
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
llvm-svn: 49572
2008-04-12 04:36:06 +00:00
8c7cf88f7e
Fix a bug that prevented x86-64 from using rep.movsq for
...
8-byte-aligned data.
llvm-svn: 49571
2008-04-12 02:35:39 +00:00
7417348a7e
80 col fix
...
llvm-svn: 49569
2008-04-12 00:47:57 +00:00
aeb23a8a34
add a note, this is actually not too bad to implement.
...
llvm-svn: 49466
2008-04-10 05:54:50 +00:00
c692188075
move the x86-32 part of PR2108 here.
...
llvm-svn: 49465
2008-04-10 05:37:47 +00:00
ad75302497
Fix the x86-64 side of PR2108 by adding a v2f64 version of
...
MOVZQI2PQIrr. This would be better handled as a dag combine
(with the goal of eliminating the bitconvert) but I don't know
how to do that safely. Thoughts welcome.
llvm-svn: 49463
2008-04-10 05:13:43 +00:00
33b3300178
Make isVectorClearMaskLegal's operand list const.
...
llvm-svn: 49446
2008-04-09 20:09:42 +00:00
3d074a3125
Add XMM1 as a second return value register for f32 and f64 on x86-64. This
...
is needed for the x86-64-ABI handling of structs that contain floating-point
members that are returned by value.
llvm-svn: 49441
2008-04-09 17:54:37 +00:00
cbf87313a2
Add DX as a second return value register for i16 on x86.
...
llvm-svn: 49440
2008-04-09 17:53:38 +00:00
4c0c018bc5
Rename -disable-required-unwind-tables to unwind-tables-optional.
...
llvm-svn: 49389
2008-04-08 18:07:49 +00:00
fe767621ca
Handle the situation in 2008-01-25-EmptyFunction.ll
...
correctly when unwind info is being generated.
llvm-svn: 49366
2008-04-08 00:37:56 +00:00
344aec2952
Implement new llc flag -disable-required-unwind-tables.
...
Corresponds to -fno-unwind-tables (usually default in gcc).
llvm-svn: 49361
2008-04-08 00:10:24 +00:00
3bc3ddd638
Rename MemOperand to MachineMemOperand. This was suggested by
...
review feedback from Chris quite a while ago. No functionality
change.
llvm-svn: 49348
2008-04-07 19:35:22 +00:00
51f532f92d
Re-commit of the r48822, where the infinite looping problem discovered
...
by Dan Gohman is fixed.
llvm-svn: 49330
2008-04-07 10:06:32 +00:00
e9ecc68d8f
API changes for class Use size reduction, wave 1.
...
Specifically, introduction of XXX::Create methods
for Users that have a potentially variable number of
Uses.
llvm-svn: 49277
2008-04-06 20:25:17 +00:00
f77b5ef3d0
Favors pshufd over shufps when shuffling elements from one vector. pshufd is faster than shufps.
...
llvm-svn: 49244
2008-04-05 00:30:36 +00:00
b20e659770
strdup needs <cstring>. This fixes a build error with g++-4.3.
...
llvm-svn: 49218
2008-04-04 16:08:00 +00:00
6c66bd368e
Re-enable SSE4.
...
llvm-svn: 49158
2008-04-03 08:53:29 +00:00
6db4b4cc65
Fix x86-64 encoding bug. REX prefix must always follow 0x0F prefix. For example, extractps in 64bit mode: 66 REX 0F 3A 17, not 66 0F 3A REX 17.
...
llvm-svn: 49157
2008-04-03 08:53:17 +00:00
d9129d1de3
Cosmetic
...
llvm-svn: 49156
2008-04-03 07:45:18 +00:00
3063c5546e
Temporarily disabling SSE4 until we fix the encoding issues.
...
llvm-svn: 49129
2008-04-03 04:49:54 +00:00
025cea1126
Backing out 48222 temporarily.
...
llvm-svn: 49124
2008-04-03 03:13:16 +00:00
bd72cea737
Suppress the 128-bit integer typedef on 32-bit targets, because
...
it causes compile errors.
llvm-svn: 49122
2008-04-02 23:52:49 +00:00
39d8b26322
Partial CBackend support for 128-bit integers. This is needed
...
now that llvm-gcc is lowering appropriately-sized struct returns
to i128 on x86-64.
llvm-svn: 49109
2008-04-02 19:40:14 +00:00
8780ecbbac
Cosmetic changes per EH patch review feedback.
...
llvm-svn: 49096
2008-04-02 17:04:45 +00:00
20c9e4cbee
Add new CC lowering rule: provide a list of registers, which can be 'shadowed',
...
when some another register is used for argument passing.
Currently is used on Win64.
llvm-svn: 49079
2008-04-02 05:23:57 +00:00
fd967cf3fa
Recommitting EH patch; this should answer most of the
...
review feedback.
-enable-eh is still accepted but doesn't do anything.
EH intrinsics use Dwarf EH if the target supports that,
and are handled by LowerInvoke otherwise.
The separation of the EH table and frame move data is,
I think, logically figured out, but either one still
causes full EH info to be generated (not sure how to
split the metadata correctly).
MachineModuleInfo::needsFrameInfo is no longer used and
is removed.
llvm-svn: 49064
2008-04-02 00:25:04 +00:00
b86595fb0a
ReMat of load from stub in pic mode extends the life of pic base. Currently spiller doesn't do a good job of estimating the impact. Disable for now.
...
llvm-svn: 49059
2008-04-01 23:26:12 +00:00
19a6dd9f2a
Remove unnecessary and non-deterministic checking code. Re-enable remat of load from gv stub.
...
llvm-svn: 49054
2008-04-01 21:38:20 +00:00
cb9f8f6e4e
Don't use __bzero for memset if the second argument isn't zero.
...
llvm-svn: 49050
2008-04-01 20:56:18 +00:00
980d7200c1
Speculatively micro-optimize memory-zeroing calls on Darwin 10.
...
llvm-svn: 49048
2008-04-01 20:38:36 +00:00
5e4e051c2a
Revert 49006 for the moment.
...
llvm-svn: 49046
2008-04-01 20:00:57 +00:00
306e3dcff4
Disabling remat of load from gv stub (temporarily) again to fix llvmgcc bootstrap miscompare.
...
llvm-svn: 49037
2008-04-01 07:33:13 +00:00
86e476b7cb
Unbreak ARM / Thumb soft FP support.
...
llvm-svn: 49012
2008-04-01 01:50:16 +00:00
efa81a6979
Accept 'y' constraint (MMX) in inline asm.
...
llvm-svn: 49011
2008-04-01 00:57:48 +00:00
7d02cf3c9c
Emit exception handling info for functions which are
...
not marked nounwind, or for all functions when -enable-eh
is set, provided the target supports Dwarf EH.
llvm-gcc generates nounwind in the right places; other FEs
will need to do so also. Given such a FE, -enable-eh should
no longer be needed.
llvm-svn: 49006
2008-03-31 23:40:23 +00:00
e4f77c69ac
It's not safe to fold a load from GV stub or constantpool into a two-address use.
...
llvm-svn: 49002
2008-03-31 23:19:51 +00:00
ed6e34fe41
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
...
llvm-svn: 48995
2008-03-31 20:40:39 +00:00
1973a46cd3
Re-apply 48911.
...
llvm-svn: 48977
2008-03-31 07:54:19 +00:00
9fb8908457
Moved from PR1570.
...
llvm-svn: 48965
2008-03-30 19:07:11 +00:00
0f760dfe09
Fix "Control reaches the end of non-void function" warnings,
...
patch by David Chisnall.
llvm-svn: 48963
2008-03-30 18:22:13 +00:00
fd2eb00cc2
Fix a tokenfactor node to use the load chain rather than the
...
load value. This fixes PR2177.
llvm-svn: 48932
2008-03-28 23:45:16 +00:00
b8654202dd
Backing out 48911 for now. It's breaking stuff.
...
llvm-svn: 48922
2008-03-28 17:49:06 +00:00
81e0c9a32c
New entry.
...
llvm-svn: 48912
2008-03-28 07:07:06 +00:00
9ae4d7b719
Load from stub is already re-materializable.
...
llvm-svn: 48911
2008-03-28 06:49:25 +00:00
308e564693
Code clean up.
...
llvm-svn: 48856
2008-03-27 01:45:11 +00:00
29e62a59f3
Allow certain lea instructions to be rematerialized.
...
llvm-svn: 48855
2008-03-27 01:41:09 +00:00
4fb07c6500
Remove an unused command line option.
...
llvm-svn: 48854
2008-03-27 01:30:24 +00:00
358e04a185
Use a linked data structure for the uses lists of an SDNode, just like
...
LLVM Value/Use does and MachineRegisterInfo/MachineOperand does.
This allows constant time for all uses list maintenance operations.
The idea was suggested by Chris. Reviewed by Evan and Dan.
Patch is tested and approved by Dan.
On normal use-cases compilation speed is not affected. On very big basic
blocks there are compilation speedups in the range of 15-20% or even better.
llvm-svn: 48822
2008-03-26 12:39:26 +00:00
292063603e
Fix some SSE4.1 instruction encoding bugs.
...
llvm-svn: 48815
2008-03-26 08:11:49 +00:00
ad6c23d5e9
Use ## for comment delimiter on darwin x86-32, so
...
llvm's output .s files will go through gcc -std=c99
without triggering preprocesser errors. Approach
suggested by Daveed Vandevoorde.
llvm-svn: 48808
2008-03-25 23:29:30 +00:00
ddc58ff92a
Smaller function alignment when optimizing for size.
...
llvm-svn: 48805
2008-03-25 22:29:46 +00:00
88c44ef91f
Rename option -optimizefor-size to -optimize-size.
...
llvm-svn: 48804
2008-03-25 22:28:39 +00:00
c60c67fc37
Add explicit keywords.
...
llvm-svn: 48801
2008-03-25 22:06:05 +00:00
bdc24adaaf
A quick nm audit turned up several fixed tables and objects that were
...
marked read-write. Use const so that they can be allocated in a
read-only segment.
llvm-svn: 48800
2008-03-25 21:45:14 +00:00
246a52740b
Add optimize-for-size knob.
...
llvm-svn: 48793
2008-03-25 21:02:35 +00:00
883cbfd0ba
Add CMP32mr and friends to the load-unfolding table. Among
...
other things, this allows the scheduler to unfold a load operand
in the 2008-01-08-SchedulerCrash.ll testcase, so it now successfully
clones the comparison to avoid a pushf+popf.
llvm-svn: 48777
2008-03-25 16:53:19 +00:00
50b536eef9
Add \t after .set. Fix by Jay Freeman.
...
llvm-svn: 48753
2008-03-24 23:36:49 +00:00
6306183df3
Use the bit size of the operand instead of the hard-coded 32 to generate the
...
mask.
llvm-svn: 48750
2008-03-24 23:16:37 +00:00
615488ab45
- SSE4.1 extractfps extracts a f32 into a gr32 register. Very useful! Not. Fix the instruction specification and teaches lowering code to use it only when the only use is a store instruction.
...
llvm-svn: 48746
2008-03-24 21:52:23 +00:00
58db865d6e
Remove duplicated entries.
...
llvm-svn: 48714
2008-03-23 22:56:07 +00:00
1fdd5e9133
Minor typo fixes. Also add another FIXME.
...
llvm-svn: 48710
2008-03-23 20:32:06 +00:00
17fb491469
Add license header
...
llvm-svn: 48707
2008-03-23 14:53:18 +00:00
9f0e820fa3
Add Win64 compilation callback. This allows easy examples to be JITed on Win64!
...
llvm-svn: 48706
2008-03-23 14:44:32 +00:00
a347663762
Provide a JIT selector on win64
...
llvm-svn: 48704
2008-03-23 13:43:47 +00:00
7574ead985
Hack out the PIC mode on Win64 targets. This needs to be investigated later.
...
llvm-svn: 48703
2008-03-23 13:41:18 +00:00
4733e72a25
Code cleanup. Provide generic way of selecting JIT pointer bitwidth regardless
...
of compiler used.
llvm-svn: 48702
2008-03-23 13:40:45 +00:00
bd47269f13
Remove old-standing obsolete code.
...
llvm-svn: 48701
2008-03-23 12:32:54 +00:00
cec773d8e7
Honour built-in defines on win64 targets for automatically subtarget recognize.
...
Force stack alignment to 16 bytes on win targets.
llvm-svn: 48695
2008-03-22 21:18:22 +00:00
07a789d2b5
Recognize "windows" in target triple, not only "win32"
...
llvm-svn: 48694
2008-03-22 21:12:53 +00:00
b86e0936f1
Add information about callee-saved registers on Win64
...
llvm-svn: 48692
2008-03-22 21:04:01 +00:00
7f125b2ba5
Add convenient helper for win64 check. Simplify things slightly.
...
llvm-svn: 48691
2008-03-22 20:57:27 +00:00
7b4f4e1a86
Initial support for Win64 calling conventions. Still in early state.
...
llvm-svn: 48690
2008-03-22 20:37:30 +00:00
2fa75184f3
Another comments fixing
...
llvm-svn: 48683
2008-03-22 07:53:40 +00:00
c55b444a8f
Restore this assert now that the livevar bug is fixed.
...
This verifies kill info for "ret" fp operands is right.
llvm-svn: 48656
2008-03-21 20:41:27 +00:00
d97eea372a
Introduce a new node for holding call argument
...
flags. This is needed by the new legalize types
infrastructure which wants to expand the 64 bit
constants previously used to hold the flags on
32 bit machines. There are two functional changes:
(1) in LowerArguments, if a parameter has the zext
attribute set then that is marked in the flags;
before it was being ignored; (2) PPC had some bogus
code for handling two word arguments when using the
ELF 32 ABI, which was hard to convert because of
the bogusness. As suggested by the original author
(Nicolas Geoffray), I've disabled it for the moment.
Tested with "make check" and the Ada ACATS testsuite.
llvm-svn: 48640
2008-03-21 09:14:45 +00:00
68b11e14bc
remove Evan's "ugly hack" that sorta attempted to get
...
x86-64 return conventions correct, but was never enabled.
We can now do the "right thing" with multiple return values.
llvm-svn: 48635
2008-03-21 06:50:21 +00:00
5abbe6cef5
Add support for calls that return two FP values in
...
ST(0)/ST(1).
llvm-svn: 48634
2008-03-21 06:38:26 +00:00
7e59a30e9f
disable a bogus assertion.
...
llvm-svn: 48633
2008-03-21 06:01:05 +00:00
b6f04a3e0a
Enable support for returning two long-double values in ST(0)/ST(1).
...
This allows us to compile fp-stack-2results.ll into:
_test:
fldz
fld1
ret
which returns 1 in ST(0) and 0 in ST(1). This is needed for x86-64
_Complex long double.
llvm-svn: 48632
2008-03-21 05:57:20 +00:00
92b4488202
Undo 48570. Correctly match mmx shift instructions with an immediate operand.
...
llvm-svn: 48627
2008-03-21 00:40:09 +00:00
fd5fe2a83d
add a note.
...
llvm-svn: 48583
2008-03-20 04:46:13 +00:00
7a3e750fd2
Fix this xform: (sra (shl X, m), result_size) -> (sign_extend (trunc (shl X, result_size - n - m)))
...
llvm-svn: 48578
2008-03-20 02:18:41 +00:00
a7cca362af
detabify llvm, patch by Mike Stump!
...
llvm-svn: 48577
2008-03-20 01:22:40 +00:00
bbaf3edace
Add more patterns to match in the integer comparison test harnesses.
...
Fix bugs encountered, mostly due to range matching for immediates;
the CellSPU's 10-bit immediates are sign extended, covering a
larger range of unsigned values.
llvm-svn: 48575
2008-03-20 00:51:36 +00:00
bbba76fc99
Add intrinsics to match mmx shift builtin's with immediate operand.
...
llvm-svn: 48569
2008-03-19 23:38:52 +00:00
718da668ab
PassInfo keep tracks whether a pass is an analysis pass or not.
...
llvm-svn: 48554
2008-03-19 21:56:59 +00:00
b9056838d2
Add support for multiple return values for the PPC target by
...
converting call result lowering to use the CallingConvLowering
infastructure.
llvm-svn: 48552
2008-03-19 21:39:28 +00:00
7da2bceb3b
Don't loose incoming argument registers. Fix documentation style.
...
llvm-svn: 48545
2008-03-19 16:39:45 +00:00
8fe9109469
Fix X86's isTruncateFree to not claim that truncate to i1 is free. This fixes Bill's testcase that failed for r48491.
...
llvm-svn: 48542
2008-03-19 08:30:06 +00:00
2f6ab65d77
On Darwin, GCC issues a ".globl" for something that has a "visibility protected"
...
attribute instead of ".protected".
llvm-svn: 48516
2008-03-18 23:38:12 +00:00
484064370a
Fix a x86-64 isel lowering bug that's been around forever. A x86-64 varargs function implicitly reads X86::AL, don't clobber it!
...
llvm-svn: 48515
2008-03-18 23:36:35 +00:00
cf87e71053
Make Complex long long/double/long double work
...
in ppc64 mode.
llvm-svn: 48459
2008-03-17 17:11:08 +00:00
7d4152bda6
Check in some #ifdef'd out code switching call argument
...
lowering over to SparcCallingConv.td. We can't make the switch
yet because we can't say to pass f64 registers in 2 x i32 registers
with the td file yet.
llvm-svn: 48449
2008-03-17 06:58:37 +00:00
52f16deb65
minor cleanups
...
llvm-svn: 48448
2008-03-17 06:57:02 +00:00
24bc123e80
Unbreak JIT. Ignore TargetInstrInfo::IMPLICIT_DEF.
...
llvm-svn: 48447
2008-03-17 06:56:52 +00:00
4eabbb8f11
remove dead code
...
llvm-svn: 48445
2008-03-17 06:04:10 +00:00
db26db2158
Switch sparc from using LowerCallTo to using LowerOperation(CALL) like
...
other targets. Use autogenerated calling conv to lower result of
calls.
llvm-svn: 48444
2008-03-17 06:01:07 +00:00
49b269d780
Start moving sparc to use SparcCallingConv.td, switching over
...
return lowering first. This fixes a bug where the top and bottom
of i64 values were returned in the wrong registers before.
llvm-svn: 48443
2008-03-17 05:41:48 +00:00
0a1762e374
split sparc lowering out into SparcISelLowering.{cpp|h} to follow
...
best practices.
llvm-svn: 48442
2008-03-17 03:21:36 +00:00
5c5597a572
refactor the LowerOperation code out to individual functions for
...
each lowering, which is 'best practice'.
llvm-svn: 48441
2008-03-17 02:52:07 +00:00
92dcf1e0c2
Next round of PPC32 ABI changes. Allow for gcc
...
behavior where a callee thinks a param will be
present in memory, even though the ABI doc says
it doesn't have to be. Handle complex long long
and complex double (4 and 8 return regs).
llvm-svn: 48439
2008-03-17 02:13:43 +00:00
af8d3c6699
various rotate fun.
...
llvm-svn: 48438
2008-03-17 01:47:51 +00:00
9030ecec88
Add a couple missing SSE4 instructions
...
llvm-svn: 48430
2008-03-16 21:14:46 +00:00
ab4b7d36cd
C and Objective Caml bindings for the TargetData class.
...
llvm-svn: 48422
2008-03-16 20:08:03 +00:00
d3d0ad3f58
Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.
...
llvm-svn: 48412
2008-03-16 03:12:01 +00:00
ec7533b620
Remove isImplicitDef TargetInstrDesc flag.
...
llvm-svn: 48381
2008-03-15 00:19:36 +00:00
0e7b00d79f
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
...
llvm-svn: 48380
2008-03-15 00:03:38 +00:00
0dfd3f33f7
Implement the real calling convention for ppc32 Altivec:
...
vectors go at the end of the memory area, after all
non-vector parameters.
llvm-svn: 48364
2008-03-14 17:41:26 +00:00
5be52a6053
Fix some 80 col violations.
...
llvm-svn: 48361
2008-03-14 07:46:48 +00:00
96bdbd6c5d
Fix a number of encoding bugs. SSE 4.1 instructions MPSADBWrri, PINSRDrr, etc. have 8-bits immediate field (ImmT == Imm8).
...
llvm-svn: 48360
2008-03-14 07:39:27 +00:00
77c8da7f00
Add debugging stuff.
...
llvm-svn: 48359
2008-03-14 07:13:42 +00:00
477d0f5294
Add an issue that is preventing instcombine from doing a simplification.
...
llvm-svn: 48356
2008-03-14 06:00:19 +00:00
eac0c96371
Use SDTNone instead of duplicating it.
...
llvm-svn: 48346
2008-03-13 23:07:40 +00:00
dd55d3f1b2
Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects.
...
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329
2008-03-13 05:47:01 +00:00
6424bd0b11
Do not promote float params to double in varargs
...
calls here. This was done earlier for params in
the varargs part of the params; any float params
that survive to here are in the non-varargs part,
and must not be promoted.
llvm-svn: 48310
2008-03-12 23:40:01 +00:00
8a923e7c28
Reimplement the parameter attributes support, phase #1 . hilights:
...
1. There is now a "PAListPtr" class, which is a smart pointer around
the underlying uniqued parameter attribute list object, and manages
its refcount. It is now impossible to mess up the refcount.
2. PAListPtr is now the main interface to the underlying object, and
the underlying object is now completely opaque.
3. Implementation details like SmallVector and FoldingSet are now no
longer part of the interface.
4. You can create a PAListPtr with an arbitrary sequence of
ParamAttrsWithIndex's, no need to make a SmallVector of a specific
size (you can just use an array or scalar or vector if you wish).
5. All the client code that had to check for a null pointer before
dereferencing the pointer is simplified to just access the
PAListPtr directly.
6. The interfaces for adding attrs to a list and removing them is a
bit simpler.
Phase #2 will rename some stuff (e.g. PAListPtr) and do other less
invasive changes.
llvm-svn: 48289
2008-03-12 17:45:29 +00:00
99ee78ef63
Clean up my own mess.
...
X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases.
llvm-svn: 48279
2008-03-12 07:02:50 +00:00
0d98256c05
One more bit of Altivec parameter passing.
...
llvm-svn: 48269
2008-03-12 00:49:20 +00:00
b28456ef18
Implement Altivec passing to varargs functions on ppc.
...
llvm-svn: 48264
2008-03-12 00:22:17 +00:00
e8fa50f63a
Correctly propagate thread-local flag from aliasee to alias. This fixes PR2137
...
llvm-svn: 48257
2008-03-11 22:38:53 +00:00
24570836b2
Use PassManagerBase instead of FunctionPassManager for functions
...
that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.
llvm-svn: 48256
2008-03-11 22:29:46 +00:00
8abed80a69
Implement basic support for the 'f' register class constraint. This basically
...
works, but probably won't if you mix it with 't' or 'u' yet.
llvm-svn: 48243
2008-03-11 19:50:13 +00:00
7b27ccfd5e
coalesce away 80-bit floating point copies.
...
llvm-svn: 48241
2008-03-11 19:30:09 +00:00
7930d8e775
convert a massive if statement to a switch.
...
llvm-svn: 48240
2008-03-11 19:28:17 +00:00
120ad01fcb
start handling the 'f' x87 constraint.
...
llvm-svn: 48239
2008-03-11 19:06:29 +00:00
342e4104d3
Missed part of recommit.
...
llvm-svn: 48224
2008-03-11 10:27:36 +00:00
aa7c2105de
Recommitting parts of r48130. These do not appear to cause the observed failures.
...
llvm-svn: 48223
2008-03-11 10:09:17 +00:00
d85667b89c
If there are multiple register classes that a register belongs to, return the super-class (e.g. on x86, returns GR32, not GR32_).
...
llvm-svn: 48220
2008-03-11 07:54:14 +00:00
e88a625ecd
When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting.
...
llvm-svn: 48218
2008-03-11 07:19:34 +00:00
5b59e372dc
In 32-bit mode, mark 64-bit GPR's as unallocatable.
...
llvm-svn: 48217
2008-03-11 07:16:00 +00:00
a3860a2422
Fix the build on gcc 4.2.
...
llvm-svn: 48212
2008-03-11 05:56:09 +00:00
1bd44363f2
Change the model for FP Stack return to use fp operands on the
...
RET instruction instead of using FpSET_ST0_32. This also generalizes
the code to handling returning of multiple FP results.
llvm-svn: 48209
2008-03-11 03:23:40 +00:00
d6819da453
Generalize ExpandIntToFP to handle the case where the operand is legal
...
and it's the result that requires expansion. This code is a little confusing
because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type
(the integer type) rather than the result type.
llvm-svn: 48206
2008-03-11 01:59:03 +00:00
a4fa0ad30d
abort with an assert instead of a cerr to get line#
...
llvm-svn: 48199
2008-03-10 23:56:08 +00:00
92275427e5
- Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency.
...
- Add test pattern matching in CellSPU's icmp32.ll test harness
- Fix CellSPU fcmp.ll-generated assert.
llvm-svn: 48197
2008-03-10 23:49:09 +00:00
7362d38391
Don't emit FP_REG_KILL into a block that just returns. Nothing
...
can be live out of the block anyway, so it isn't needed.
llvm-svn: 48192
2008-03-10 23:34:12 +00:00
0fb187f81b
Disable prolog code that aligns the stack when a
...
local object of >16 byte alignment exists. It does not
work and getting it to work is not trivial, as explained
in the comment. This fixes all the remaining ppc32
failures in the struct-layout-1 part of the gcc testsuite.
(gcc does not support this either, and the only way to
get such an object is with __attribute__((aligned)) or
generic vectors; it can't be done in a standard-conforming
program, or with Altivec. So I think disabling it is OK.)
llvm-svn: 48188
2008-03-10 22:59:46 +00:00
c6c48fca74
Change the "enable/disable" mechanism so that we can enable PPC register
...
scavenging for 32-bit and 64-bit separately.
llvm-svn: 48186
2008-03-10 22:49:16 +00:00
4b3a7fa823
Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to
...
copyfromreg/copytoreg instead.
llvm-svn: 48174
2008-03-10 21:08:41 +00:00
ae2c56d93e
Default ISD::PREFETCH to expand.
...
llvm-svn: 48169
2008-03-10 19:38:10 +00:00
d4e1d9eeb2
Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.
...
llvm-svn: 48167
2008-03-10 19:31:26 +00:00
514b3ed536
fix 80 col violations.
...
llvm-svn: 48166
2008-03-10 18:55:53 +00:00
708784ea4f
Stylistic modifications. No functionality changes.
...
llvm-svn: 48158
2008-03-10 17:46:45 +00:00
48e3375544
Integer comparison tests for CellSPU.
...
llvm-svn: 48152
2008-03-10 16:58:52 +00:00
a6729e8666
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
...
return ValueType can depend its operands' ValueType.
This is a cosmetic change, no functionality impacted.
llvm-svn: 48145
2008-03-10 15:42:14 +00:00
b1de7a35f9
Add description of individual bits in CR. This fix PR1765.
...
llvm-svn: 48143
2008-03-10 14:12:10 +00:00
4ba3f0430b
Allow insert_subreg into implicit, target-specific values.
...
Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.
llvm-svn: 48130
2008-03-10 06:12:08 +00:00
4e622ec86d
Increase ISD::ParamFlags to 64 bits. Increase the ByValSize
...
field to 32 bits, thus enabling correct handling of ByVal
structs bigger than 0x1ffff. Abstract interface a bit.
Fixes gcc.c-torture/execute/pr23135.c and
gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing
on ppc32, quietly producing wrong code on x86-32.)
llvm-svn: 48122
2008-03-10 02:17:22 +00:00
aed9406bb7
Darwin PPC64 indirect call target goes in X12, not R12. This fixes these
...
two regression tests:
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll
llvm-svn: 48120
2008-03-09 20:49:33 +00:00
78e817d7fc
cell really does support cross-regclass moves, because R3 is in lots of different regclasses, and the code is not consistent when it comes to value tracking.
...
llvm-svn: 48119
2008-03-09 20:31:11 +00:00
3ba79ed9e8
make sure ar.pfs is in a register class, this fixes test/CodeGen/IA64/ret-0.ll
...
llvm-svn: 48118
2008-03-09 20:12:44 +00:00
86829f0ff7
teach X86InstrInfo::copyRegToReg how to copy into ST(0) from
...
an RFP register class.
Teach ScheduleDAG how to handle CopyToReg with different src/dst
reg classes.
This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.
llvm-svn: 48107
2008-03-09 09:15:31 +00:00
b79bafcec8
add some code to support cross-register class copying from
...
RST -> RFP{32/64/80}. We only handle ST(0) for now.
llvm-svn: 48104
2008-03-09 08:46:19 +00:00
c4c9dde04c
rearrange some code, no functionality change.
...
llvm-svn: 48101
2008-03-09 07:58:04 +00:00
459f518703
claim ST(x) registers are 80 bits, which is true. This doesn't affect
...
codegen yet because these can't be spilled (they don't exist until after RA).
llvm-svn: 48098
2008-03-09 07:49:01 +00:00
4c869594bc
rename FP_SETRESULT -> FP_SET_ST0
...
llvm-svn: 48094
2008-03-09 07:08:44 +00:00
d587e580a6
rename FpGETRESULT32 -> FpGET_ST0_32 etc. Add support for
...
isel'ing value preserving FP roundings from one fp stack reg to another
into a noop, instead of stack traffic.
llvm-svn: 48093
2008-03-09 07:05:32 +00:00
b6387c8a74
Finish implementing a readme entry: when inserting an i64 variable
...
into a vector of zeros or undef, and when the top part is obviously
zero, we can just use movd + shuffle. This allows us to compile
vec_set-B.ll into:
_test3:
movl $1234567, %eax
andl 4(%esp), %eax
movd %eax, %xmm0
ret
instead of:
_test3:
subl $28, %esp
movl $1234567, %eax
andl 32(%esp), %eax
movl %eax, (%esp)
movl $0, 4(%esp)
movq (%esp), %xmm0
addl $28, %esp
ret
llvm-svn: 48090
2008-03-09 05:42:06 +00:00
93930dc28c
add a note
...
llvm-svn: 48064
2008-03-09 01:08:22 +00:00
eef374c197
Implement a readme entry, compiling
...
#include <xmmintrin.h>
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}
into:
movl $1, %eax
movd %eax, %xmm0
ret
instead of a constant pool load.
llvm-svn: 48063
2008-03-09 01:05:04 +00:00
ad58828354
1) Improve comments.
...
2) Don't try to insert an i64 value into the low part of a
vector with movq on an x86-32 target. This allows us to
compile:
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}
into:
_doload64:
movaps LCPI1_0, %xmm0
ret
instead of:
_doload64:
subl $28, %esp
movl $0, 4(%esp)
movl $1, (%esp)
movq (%esp), %xmm0
addl $28, %esp
ret
llvm-svn: 48057
2008-03-08 22:59:52 +00:00
8a6ebd23a8
minor simplifications to this code, don't create a dead
...
SCALAR_TO_VECTOR on paths that end up not using it.
llvm-svn: 48056
2008-03-08 22:48:29 +00:00
35adf46967
This one looks easy, add a note.
...
llvm-svn: 48055
2008-03-08 22:32:39 +00:00
a76e23a935
move these to the appropriate file
...
llvm-svn: 48054
2008-03-08 22:28:45 +00:00
21a8f144a6
More ppc32 byval handling (bug fixes). Things
...
are looking pretty good now.
llvm-svn: 48043
2008-03-08 01:41:42 +00:00
95cf661534
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
...
llvm-svn: 48042
2008-03-08 00:58:38 +00:00
d2ab5fd713
Add support for calls with i128 return values on ppc64.
...
llvm-svn: 48041
2008-03-08 00:19:12 +00:00
968f32ce3d
PPC64 passes arguments of integral type in i64 registers, not i32. Reflect this
...
by promoting smaller integral values (i32 at this point) to i64, then truncating
to get the wanted size.
llvm-svn: 48030
2008-03-07 20:49:02 +00:00
8d2ead2e34
Add support for lowering 128-bit shifts on ppc64.
...
llvm-svn: 48029
2008-03-07 20:36:53 +00:00
bfa252d402
Next bits of PPC byval handling. Basically functional
...
but there are bugs.
llvm-svn: 48028
2008-03-07 20:27:40 +00:00
20b5a2b037
Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl).
...
llvm-svn: 48027
2008-03-07 20:18:24 +00:00
25ff7e217d
Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work
...
with 32 or 64-bit operands/results.
llvm-svn: 48026
2008-03-07 20:13:51 +00:00
d4defb00df
mark frem as expand for all legal fp types on x86, regardless of whether
...
we're using SSE or not. This fixes PR2122.
llvm-svn: 48006
2008-03-07 06:36:32 +00:00
636ab19205
some more spelling changes
...
llvm-svn: 47996
2008-03-06 10:51:21 +00:00
e9b690b7f1
Refine Cell's i64 constant generation code to cover more constants where the
...
upper and lower 32-bits are the same (in addition to 0 and -1 previously.)
llvm-svn: 47985
2008-03-06 04:02:54 +00:00
dcabdb1b38
gcc likes things spelled correctly
...
llvm-svn: 47981
2008-03-05 23:41:37 +00:00
0d235052d1
Next bit of PPC ByVal handling; call-site code seems
...
correct now.
llvm-svn: 47978
2008-03-05 23:31:27 +00:00
42f56b4838
- Fix support for "special" i64 immediates that can be loaded
...
using IL, ILA, et. al. v2i64 and i64 are now supported by
the select bits (SELB) instruction.
- Add missing comparison operations (testcase forthcoming)
- More multiclass refactoring.
llvm-svn: 47973
2008-03-05 23:02:02 +00:00
7c08a01698
evan implemented this.
...
llvm-svn: 47948
2008-03-05 17:11:51 +00:00
3ea44e4ee9
isTwoAddress = 1 -> Constraints.
...
llvm-svn: 47941
2008-03-05 08:19:16 +00:00
6ec7dc6bea
PSLLWri etc. are two-address instructions.
...
llvm-svn: 47940
2008-03-05 08:11:27 +00:00
2acd0c25f6
add a note
...
llvm-svn: 47939
2008-03-05 07:22:39 +00:00
3bd59641ac
Ignore debugging related instructions if they get this far.
...
llvm-svn: 47934
2008-03-05 02:34:36 +00:00
801bfb2cf7
Rather than asserting. Dump out the MI that we are not able to encode and abort.
...
llvm-svn: 47933
2008-03-05 02:08:03 +00:00
0a62cb44ce
Add a target lowering hook to control whether it's worthwhile to compress fp constant.
...
For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive.
llvm-svn: 47931
2008-03-05 01:30:59 +00:00
357061a74d
64bit CAS on 32bit x86.
...
llvm-svn: 47929
2008-03-05 01:15:49 +00:00
6325446666
Refactor code. Remove duplicated functions that basically do the same thing as
...
findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies.
llvm-svn: 47927
2008-03-05 00:59:57 +00:00
3fcd946c26
Removed spurious EnablePPCRS check.
...
llvm-svn: 47918
2008-03-04 23:27:33 +00:00
85d41a1c44
Move PPC lowering functions into PPCTargetLowering
...
class (cosmetic). First piece of byval implementation;
this doesn't work yet. No functional change.
llvm-svn: 47917
2008-03-04 23:17:14 +00:00
1af20ad336
Use a command-line option to turn register scavenging on/off for PPC.
...
llvm-svn: 47915
2008-03-04 23:13:51 +00:00
4fee9f35b5
x86-64 atomics
...
llvm-svn: 47903
2008-03-04 21:13:33 +00:00
59d58ab8c4
80 column violations.
...
llvm-svn: 47878
2008-03-04 03:20:06 +00:00
33ff36321e
Remove -always-fold-and-in-test.
...
llvm-svn: 47871
2008-03-04 00:40:35 +00:00
a986eea82f
Add support for lowering i64 SRA_PARTS and friends on x86-64.
...
llvm-svn: 47865
2008-03-03 22:22:09 +00:00
632ea65072
This is the initial check-in for adding register scavenging to PPC. (Currently,
...
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.
llvm-svn: 47863
2008-03-03 22:19:16 +00:00
9d91785987
s/isReturnStruct()/hasStructRetAttr()/g
...
llvm-svn: 47857
2008-03-03 21:46:28 +00:00
d51372aa96
another random note
...
llvm-svn: 47831
2008-03-02 19:29:42 +00:00
6b0a189225
add a note
...
llvm-svn: 47830
2008-03-02 19:27:34 +00:00
a70df9e2ee
Evan implemented these.
...
llvm-svn: 47828
2008-03-02 18:05:14 +00:00
bd0bb3f07f
Evan implemented this.
...
llvm-svn: 47827
2008-03-02 17:56:29 +00:00
c93b48caeb
add support for lvsl, fixing PR1481
...
llvm-svn: 47825
2008-03-02 08:54:27 +00:00
8fb4c98284
add support for the sse.cmp.* intrinsics, which fixes sse.isamax with the CBE.
...
llvm-svn: 47824
2008-03-02 08:47:13 +00:00
9044719798
refactor intrinsic handling code out into its own method.
...
llvm-svn: 47823
2008-03-02 08:29:41 +00:00
2541f1dac6
fix printing of undef vectors, this fixes "simple" and "build" in UnitTests/Vector.
...
Now they all pass.
llvm-svn: 47820
2008-03-02 08:14:45 +00:00
4c058b39e4
insertelement got the wrong operands.
...
llvm-svn: 47819
2008-03-02 08:10:16 +00:00
051709436e
Several changes:
...
* Simplify handling of byval, making it easier to understand and more
consistent. This fixes PR2065.
* Clean up and simplify handling of GEPs. I can actually understand it now!
* Implement support for GEP'ing into vectors, this fixes
SingleSource/UnitTests/Vector/build2 among others.
llvm-svn: 47818
2008-03-02 08:07:24 +00:00
9140fba6ad
Fix a bug I introduced in constant array and constant vector handling.
...
llvm-svn: 47816
2008-03-02 05:46:57 +00:00
7295bc15a0
implement shufflevector.
...
llvm-svn: 47815
2008-03-02 05:41:07 +00:00
689d830b6d
implement extractelement.
...
llvm-svn: 47812
2008-03-02 03:57:08 +00:00
d9cc003b0d
implement insertelement.
...
llvm-svn: 47811
2008-03-02 03:52:39 +00:00
92d929c21d
respect isSigned for vector types, fixing sdiv of vectors etc.
...
llvm-svn: 47810
2008-03-02 03:41:23 +00:00
fe1083be61
print the attribute in the right place, this fixes function returning vectors.
...
llvm-svn: 47809
2008-03-02 03:39:43 +00:00
d861066d15
vector types are simple types. This fixes div/rem of vectors.
...
llvm-svn: 47807
2008-03-02 03:33:31 +00:00
b104be599a
Print vector types appropriately. This gets basic vector code working
...
(PR1126)
llvm-svn: 47806
2008-03-02 03:29:50 +00:00
c8d974a323
rename PT -> VT for VectorTypes.
...
llvm-svn: 47805
2008-03-02 03:18:46 +00:00
895aef4720
Print i32/i64 integer constants as 1u instead of ((unsigned int)1).
...
Use dyn_cast better.
llvm-svn: 47804
2008-03-02 03:16:38 +00:00
647c6642e7
Move pr717 to here.
...
llvm-svn: 47803
2008-03-02 02:51:40 +00:00
20bcdba9ca
good catch anton
...
llvm-svn: 47800
2008-03-01 23:18:21 +00:00
f5c90ec12c
make CAS work
...
llvm-svn: 47799
2008-03-01 22:27:48 +00:00
d032c33300
all but CAS working on x86
...
llvm-svn: 47798
2008-03-01 21:52:34 +00:00
0070dd1de3
Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode.
...
llvm-svn: 47795
2008-03-01 13:37:02 +00:00
0e8b146152
Use enumeration for preffered EH dwarf encoding reason
...
llvm-svn: 47770
2008-02-29 22:09:08 +00:00
17df4cd397
Use the correct instruction encodings for the 64-bit MMX movd.
...
llvm-svn: 47740
2008-02-29 01:35:12 +00:00
95a7be473c
Added option -align-loops=<true/false> to disable loop aligner pass.
...
llvm-svn: 47736
2008-02-28 23:29:57 +00:00
cbde4c2206
Interface of getByValTypeAlignment differed between
...
generic & x86 versions; change generic to follow x86
and improve comments. Add PPC version (not right
for non-Darwin.)
llvm-svn: 47734
2008-02-28 22:31:51 +00:00
714eeb2d55
Initialize TextAlignFillValue. Fix revision 47703.
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llvm-svn: 47732
2008-02-28 22:14:09 +00:00
9781aee03c
Avoid collisions in value names.
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llvm-svn: 47725
2008-02-28 20:26:04 +00:00
643dce1146
add a note
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llvm-svn: 47720
2008-02-28 17:21:27 +00:00
507713de08
Set to default: x86 no longer fold and into test if it has more than one use.
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llvm-svn: 47711
2008-02-28 07:46:38 +00:00
e2f55f9fc5
Sparc backend doesn't support debug info yet, mark the nodes as expand. This fixes a crash on
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test/DebugInfo/funccall.ll
llvm-svn: 47709
2008-02-28 05:54:25 +00:00
f1444c35e8
Fix CodeGen/Generic/storetrunc-fp.ll on sparc, PR2105
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llvm-svn: 47707
2008-02-28 05:48:04 +00:00
beb6a5ba4f
fix CodeGen/Generic/2008-01-25-dag-combine-mul.ll on sparc, PR2105
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llvm-svn: 47706
2008-02-28 05:44:20 +00:00
765be8874d
target-indep codegen memcpy lowering issue.
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llvm-svn: 47705
2008-02-28 05:34:27 +00:00
83e80cd368
Add a random not very important note
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llvm-svn: 47704
2008-02-28 04:52:59 +00:00
c799065cc3
Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries.
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llvm-svn: 47703
2008-02-28 00:43:03 +00:00
93e8b679a3
A few more small things I've run into.
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llvm-svn: 47702
2008-02-28 00:21:43 +00:00
d73396bef9
EHPreferredDataFormat hook for PPC targets. Looks like Darwin
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uses the same encoding everywhere. Linux FIXME'ed.
llvm-svn: 47701
2008-02-27 23:49:15 +00:00
ae24cca0e4
Preparation step for some cleanup/generalization in EH information emission:
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provide TAI hook for selection of EH data emission format. Currently unused.
llvm-svn: 47699
2008-02-27 23:33:50 +00:00
26854f242e
Don't hard-code the mask size to be 32, which is incorrect on ppc64
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and was causing aborts with the new APInt changes. This may also be
fixing an obscure ppc64 bug.
llvm-svn: 47692
2008-02-27 21:12:32 +00:00
3d17e4c427
This is done.
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llvm-svn: 47688
2008-02-27 20:26:32 +00:00
97925ec704
Final de-tabification.
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llvm-svn: 47663
2008-02-27 06:33:05 +00:00
83263b8cfb
Make X86TargetLowering::LowerSINT_TO_FP return without creating a dead
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stack slot and store if the SINT_TO_FP is actually legal. This allows
us to compile:
double a(double b) {return (unsigned)b;}
to:
_a:
cvttsd2siq %xmm0, %rax
movl %eax, %eax
cvtsi2sdq %rax, %xmm0
ret
instead of:
_a:
subq $8, %rsp
cvttsd2siq %xmm0, %rax
movl %eax, %eax
cvtsi2sdq %rax, %xmm0
addq $8, %rsp
ret
crazy.
llvm-svn: 47660
2008-02-27 05:57:41 +00:00
5fe95a04f5
this code is correct but strange looking ;-)
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llvm-svn: 47659
2008-02-27 05:48:44 +00:00
3c7d3d5700
Compile x86-64-and-mask.ll into:
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_test:
movl %edi, %eax
ret
instead of:
_test:
movl $4294967295, %ecx
movq %rdi, %rax
andq %rcx, %rax
ret
It would be great to write this as a Pat pattern that used subregs
instead of a 'pseudo' instruction, but I don't know how to do that
in td files.
llvm-svn: 47658
2008-02-27 05:47:54 +00:00
6d56368caf
Spiller now remove unused spill slots.
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llvm-svn: 47657
2008-02-27 03:04:06 +00:00
f19609abe8
Convert the last remaining users of the non-APInt form of
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ComputeMaskedBits to use the APInt form, and remove the
non-APInt form.
llvm-svn: 47654
2008-02-27 01:23:58 +00:00
3f86109fd1
add a note
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llvm-svn: 47652
2008-02-27 01:17:20 +00:00
3bfca3e942
Refactor according to Evan's and Anton's suggestions.
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llvm-svn: 47635
2008-02-26 22:21:54 +00:00
d7a258d325
Rename PrintableName to Name.
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llvm-svn: 47629
2008-02-26 21:47:57 +00:00
c24ea4fb41
Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool
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would have been a Godsend here!
llvm-svn: 47625
2008-02-26 21:11:01 +00:00
1f17bf6171
Correct function comments.
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llvm-svn: 47606
2008-02-26 17:50:59 +00:00
80d6b87934
De-tabify
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llvm-svn: 47600
2008-02-26 10:57:23 +00:00
69a10f4112
Add support for intermodule tail calls on x86/32bit with
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GOT-style position independent code. Before only tail calls to
protected/hidden functions within the same module were optimized.
Now all function calls are tail call optimized.
llvm-svn: 47594
2008-02-26 10:21:54 +00:00
b01b99ec78
Change the lowering of arguments for tail call optimized
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calls. Before arguments that could overwrite each other were
explicitly lowered to a stack slot, not giving the register allocator
a chance to optimize. Now a sequence of copyto/copyfrom virtual
registers ensures that arguments are loaded in (virtual) registers
before they are lowered to the stack slot (and might overwrite each
other). Also parameter stack slots are marked mutable for
(potentially) tail calling functions.
llvm-svn: 47593
2008-02-26 09:19:59 +00:00
a790af3a88
Revert the assert for MUL_LOHI with an unused high result; Chris
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pointed out that this isn't correct at -O0.
llvm-svn: 47575
2008-02-25 22:43:48 +00:00
65b404d61c
Revise previous patch per review.
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llvm-svn: 47573
2008-02-25 22:29:22 +00:00
0be2f3b941
Add an assert to verify that we don't see an
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{S,U}MUL_LOHI with an unused high value.
llvm-svn: 47569
2008-02-25 22:15:55 +00:00
2ff975e749
Remove the hack that turned an {S,U}MUL_LOHI with an unused high
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result into a MUL late in the X86 codegen process. ISD::MUL is
once again Legal on X86, so this is no longer needed. And, the
hack was suboptimal; see PR1874 for details.
llvm-svn: 47567
2008-02-25 21:57:04 +00:00
1f372edd97
Convert MaskedValueIsZero and all its users to use APInt. Also add
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a SignBitIsZero function to simplify a common use case.
llvm-svn: 47561
2008-02-25 21:11:39 +00:00
32d84b1772
Expand removal of MMX memory copies to allow 1 level
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of TokenFactor underneath chain (seems to be enough)
llvm-svn: 47554
2008-02-25 19:20:14 +00:00
a7d1ed4c98
Some platforms use the same name for 32-bit and 64-bit registers (like
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%r3 on PPC) in their ASM files. However, it's hard for humans to read
during debugging. Adding a new field to the register data that lets you
specify a different name to be printed than the one that goes into the
ASM file -- %x3 instead of %r3, for instance.
llvm-svn: 47534
2008-02-24 00:56:13 +00:00
7d5eaec6dd
Merge current work back to tree to minimize diffs and drift. Major highlights
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for CellSPU modifications:
- SPUInstrInfo.td refactoring: "multiclass" really is _your_ friend.
- Other improvements based on refactoring effort in SPUISelLowering.cpp,
esp. in SPUISelLowering::PerformDAGCombine(), where zero amount shifts and
rotates are now eliminiated, other scalar-to-vector-to-scalar silliness
is also eliminated.
- 64-bit operations are being implemented, _muldi3.c gcc runtime now
compiles and generates the right code. More work still needs to be done.
llvm-svn: 47532
2008-02-23 18:41:37 +00:00
Evan Cheng