Commit Graph

138625 Commits

Author SHA1 Message Date
Craig Topper bd74f75619 [X86] Really fix the FileCheck line from r282690.
Why does Folded Spill comments print with a different number of # characters on different systems?

llvm-svn: 282693
2016-09-29 06:49:21 +00:00
Craig Topper 1b60e9d7c0 [AVX-512] Fix a check line from r282690.
llvm-svn: 282691
2016-09-29 06:37:21 +00:00
Craig Topper d875d6b9b4 [AVX-512] Support spills of XMM16-31 and YMM16-31 when VLX isn't available.
This adds new pseudo instructions that can be selected during register allocation to represent loads and stores of XMM/YMM registers when AVX512F is available, but VLX isn't. They will be converted to VEX encoded moves if the register turns out to be XMM0-15/YMM0-15. Otherwise either an EVEX VEXTRACT(store) or VBROADCAST(load) will be used.

Fixes one of the cases from PR29112.

llvm-svn: 282690
2016-09-29 06:07:09 +00:00
Craig Topper f91830e6ee [X86] Remove extra FileCheck lines that got left behind in r282688.
llvm-svn: 282689
2016-09-29 06:07:07 +00:00
Craig Topper 7eb0e7ce1f [AVX-512] Replicate pattern from AVX to select VMOVDDUP for (v2f64 (X86VBroadcast f64:)). Add AVX512VL to command line of existing AVX2 test that hits this condition.
llvm-svn: 282688
2016-09-29 05:54:43 +00:00
Craig Topper e7f2611160 [X86] Add EVEX encoded VBROADCASTSS/SD and VPBROADCASTD/Q to execution domain fixing table.
llvm-svn: 282687
2016-09-29 05:54:39 +00:00
Craig Topper cb3ae5a03d [X86] Remove AddedComplexity adjustments that don't seem to be needed.
llvm-svn: 282686
2016-09-29 05:54:34 +00:00
Craig Topper 7da0465062 [X86] Add 512-bit VPBROADCASTB and VPBROADCASTW tests.
llvm-svn: 282685
2016-09-29 05:54:32 +00:00
Craig Topper 816a1d7783 [X86] Add VBROADCASTF128/VBROADCASTI128 to execution domain fixing tables.
llvm-svn: 282684
2016-09-29 05:54:28 +00:00
Justin Bogner 0009fef06c IR: Rename the tablegen'd Attributes file to .gen
All of the other tablegen'd include files are named .gen, so it's best
to be consistent.

llvm-svn: 282680
2016-09-29 03:35:19 +00:00
Peter Collingbourne f75609e015 Add explanatory comment.
llvm-svn: 282678
2016-09-29 03:29:28 +00:00
Eric Christopher 20ac943748 Remove an unnecessary duplicate initialization of TLOF from the Mips
AsmPrinter. This was reinitializing the Mangler after we moved the
Mangler down to TLOF and causing us to have two different unnamed
global values accessed with the same name.

This should fix the problems on the ubsan tests here:
http://lab.llvm.org:8011/builders/clang-cmake-mips/builds/15307

llvm-svn: 282675
2016-09-29 02:03:52 +00:00
Eric Christopher 1c3bb79864 Remove the default constructor and count variable from the Mangler since
we can just use the size of the DenseMap as a unique counter.

llvm-svn: 282674
2016-09-29 02:03:50 +00:00
Eric Christopher b4b75a531e Update comment about initializing TLOF with a pointer at the previous
line or the other commented out place.

llvm-svn: 282673
2016-09-29 02:03:47 +00:00
Eric Christopher 8e94895555 Tidy spelling and grammar.
llvm-svn: 282672
2016-09-29 02:03:44 +00:00
Matthias Braun aae7fe99d0 MachineFunction: Add missing newline in debug print()
Should not be a functional but an aesthetic change.

llvm-svn: 282669
2016-09-29 01:47:42 +00:00
Matt Arsenault e6740754f0 AMDGPU: Partially fix control flow at -O0
Fixes to allow spilling all registers at the end of the block
work with exec modifications. Don't emit s_and_saveexec_b64 for
if lowering, and instead emit copies. Mark control flow mask
instructions as terminators to get correct spill code placement
with fast regalloc, and then have a separate optimization pass
form the saveexec.

This should work if SGPRs are spilled to VGPRs, but
will likely fail in the case that an SGPR spills to memory
and no workitem takes a divergent branch.

llvm-svn: 282667
2016-09-29 01:44:16 +00:00
Matthias Braun ae689e3498 ScheduleDAGInstrs: There is no need to set OrigNode for MI SUnits; NFC
llvm-svn: 282666
2016-09-29 01:32:31 +00:00
Peter Collingbourne 0d5636e517 LTO: Fix use-after-scope error.
llvm-svn: 282665
2016-09-29 01:28:36 +00:00
Lei Liu 361615cfd0 AArch64: Set shift bit of TLSLE HI12 add instruction
Summary: AArch64 LLVM assembler emits add instruction without shift bit to calculate the higher 12-bit address of TLS variables in local exec model.  This generates wrong code sequence to access TLS variables with thread offset larger than 0x1000.

Reviewers: t.p.northover, peter.smith, rovka

Subscribers: salim.nasser, aemerson, llvm-commits, rengolin

Differential Revision: https://reviews.llvm.org/D24702

llvm-svn: 282661
2016-09-29 01:05:48 +00:00
Davide Italiano 0aff59f32d [LTO] Add a FIXME, we shouldn't expose getComdat().
Thanks to Peter for the suggestion.

llvm-svn: 282655
2016-09-29 00:31:45 +00:00
Davide Italiano d9d689ead1 [LTO] Expose getComdatSymbolTable() to linkers.
llvm-svn: 282654
2016-09-29 00:29:33 +00:00
Evgeny Stupachenko dc8a254663 Wisely choose sext or zext when widening IV.
Summary:
The patch fixes regression caused by two earlier patches D18777 and D18867.

Reviewers: reames, sanjoy

Differential Revision: http://reviews.llvm.org/D24280

From: Li Huang
llvm-svn: 282650
2016-09-28 23:39:39 +00:00
Kevin Enderby 76966bf066 Next set of additional error checks for invalid Mach-O files for the
load command that uses the Mach::rpath_command type
but not used in llvm libObject code but used in llvm tool code.

This includes just the LC_RPATH load command.

llvm-svn: 282649
2016-09-28 23:16:01 +00:00
Quentin Colombet 40cbc27ff3 [RegisterBankInfo] Uniquely generate OperandsMapping.
This is a step toward statically allocate InstructionMapping. Like the
previous few commits, the goal is to move toward a TableGen'ed like
structure with no dynamic allocation at all.

This should already improve compile time by getting rid of a bunch of
memmove of SmallVectors.

llvm-svn: 282643
2016-09-28 22:20:49 +00:00
Quentin Colombet 97d2d21d65 [RegisterBankInfo] Rework the APIs of ValueMapping.
This is a preparatory commit for more TableGen-like structure.
NFC

llvm-svn: 282642
2016-09-28 22:20:24 +00:00
Mike Aizatsky 392caa538d [sancov] introducing symbolized coverage files (.symcov)
Summary:
Answering any meaningful questions about .sancov files requires
accessing symbol information from the corresponding binary.

This change introduces a separate intermediate data structure and
format: symbolized coverage. It contains all symbol information that
is required to answer common queries:
- merging
- coverd/uncovered files and functions
- line status.

Also removing the html report functionality from sancov: generated
HTML files are too huge, and a different approach is required.
Maintaining this half-working approach in the C++ is painful.

Differential Revision: https://reviews.llvm.org/D24947

llvm-svn: 282639
2016-09-28 21:39:28 +00:00
Adrian Prantl f8d10ceafe Remove dead code from LiveDebugVariables.cpp (NFC)
LiveDebugVariables doesn't propagate DBG_VALUEs accross basic block
boundaries any more; this functionality was split into LiveDebugValues.
We can thus drop the now dead references to LexicalScopes from LiveDebugVariables.

llvm-svn: 282638
2016-09-28 21:34:23 +00:00
Mike Aizatsky fa57bf1b2a [sancov] a simple .symcov coverage report server
Coverage reports for gigabyte-sized binaries are huge. There's no
practical reason to generate them statically.

Implementing an experiment http coverage report server. The server
loads .symcov file and serves interactive coverage pages.

llvm-svn: 282637
2016-09-28 21:27:58 +00:00
Kevin Enderby 32359dbf6b Next set of additional error checks for invalid Mach-O files for the
other load commands that use the Mach::version_min_command type
but not used in llvm libObject code but used in llvm tool code.

This includes LC_VERSION_MIN_MACOSX, LC_VERSION_MIN_IPHONEOS,
LC_VERSION_MIN_TVOS and LC_VERSION_MIN_WATCHOS load commands.

llvm-svn: 282635
2016-09-28 21:20:45 +00:00
Dehao Chen 5461d8bdb5 Refactor the ProfileSummaryInfo to use doInitialization and doFinalization to handle Module update.
Summary: This refactors the change in r282616

Reviewers: davidxl, eraman, mehdi_amini

Subscribers: mehdi_amini, davide, llvm-commits

Differential Revision: https://reviews.llvm.org/D25041

llvm-svn: 282630
2016-09-28 21:00:58 +00:00
Krzysztof Parzyszek dcb1bcae0b IfConversion: Add implicit uses for redefined regs with live subregisters
Normally, if conversion would add implicit uses for redefined registers,
e.g. R0<def> = add_if ..., R0<imp-use>. However, if only subregisters of
R0 are known to be live but not R0 itself, such implicit uses will not be
added, causing prior definitions of such subregisters and R0 itself to
become dead.

llvm-svn: 282626
2016-09-28 20:07:41 +00:00
Konstantin Zhuravlyov e14df4b236 [AMDGPU] Promote uniform i16 ops to i32 ops for targets that have 16 bit instructions
Differential Revision: https://reviews.llvm.org/D24125

llvm-svn: 282624
2016-09-28 20:05:39 +00:00
Sanjay Patel 3e9e5ccf7c [InstCombine] update to use FileCheck
Also, remove unnecessary function attributes, parameters, and comments.
It looks like at least some of these tests are not minimal though...

llvm-svn: 282620
2016-09-28 19:10:16 +00:00
Dehao Chen 10d0abb515 Fix the bug introduced in r282616.
llvm-svn: 282618
2016-09-28 18:54:36 +00:00
Dehao Chen 80c8ebb4d8 Fix the bug when -compile-twice is specified, the PSI will be invalidated.
Summary:
When using llc with -compile-twice, module is generated twice, but getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI will still get the old PSI with the original (invalidated) Module. This patch checks if the module has changed when calling getPSI, if yes, update the module and invalidate the Summary.
The bug does not show up in the current llc because PSI is not used in CodeGen yet. But with https://reviews.llvm.org/D24989, the bug will be exposed by test/CodeGen/PowerPC/pr26378.ll

Reviewers: eraman, davidxl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D24993

llvm-svn: 282616
2016-09-28 18:41:14 +00:00
Simon Pilgrim fea5c7a051 [X86][AVX] Add test showing that VBROADCAST loads don't correctly respect dependencies
llvm-svn: 282613
2016-09-28 17:59:30 +00:00
Artur Pilipenko b6ce6e5dac Don't look through addrspacecast in GetPointerBaseWithConstantOffset
Pointers in different addrspaces can have different sizes, so it's not valid to look through addrspace cast calculating base and offset for a value.

This is similar to D13008.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D24729

llvm-svn: 282612
2016-09-28 17:57:16 +00:00
Adrian Prantl 7f5866c227 Teach LiveDebugValues about lexical scopes.
This addresses PR26055 LiveDebugValues is very slow.

Contrary to the old LiveDebugVariables pass LiveDebugValues currently
doesn't look at the lexical scopes before inserting a DBG_VALUE
intrinsic. This means that we often propagate DBG_VALUEs much further
down than necessary. This is especially noticeable in large C++
functions with many inlined method calls that all use the same
"this"-pointer.

For example, in the following code it makes no sense to propagate the
inlined variable a from the first inlined call to f() into any of the
subsequent basic blocks, because the variable will always be out of
scope:

void sink(int a);
void __attribute((always_inline)) f(int a) { sink(a); }
void foo(int i) {
   f(i);
   if (i)
     f(i);
   f(i);
}

This patch reuses the LexicalScopes infrastructure we have for
LiveDebugVariables to take this into account.

The effect on compile time and memory consumption is quite noticeable:
I tested a benchmark that is a large C++ source with an enormous
amount of inlined "this"-pointers that would previously eat >24GiB
(most of them for DBG_VALUE intrinsics) and whose compile time was
dominated by LiveDebugValues. With this patch applied the memory
consumption is 1GiB and 1.7% of the time is spent in LiveDebugValues.

https://reviews.llvm.org/D24994
Thanks to Daniel Berlin and Keith Walker for reviewing!

llvm-svn: 282611
2016-09-28 17:51:14 +00:00
Adrian Prantl 16b2ace0ab Rewrite loops to use range-based for. (NFC)
llvm-svn: 282608
2016-09-28 17:31:17 +00:00
Artem Belevich 3e1211581c [NVPTX] Added intrinsics for atom.gen.{sys|cta}.* instructions.
These are only available on sm_60+ GPUs.

Differential Revision: https://reviews.llvm.org/D24943

llvm-svn: 282607
2016-09-28 17:25:38 +00:00
Sanjoy Das f0022125e0 [SCEV] Use a SmallPtrSet as a temporary union predicate; NFC
Summary:
Instead of creating and destroying SCEVUnionPredicate instances (which
internally creates and destroys a DenseMap), use temporary SmallPtrSet
instances of remember the set of predicates that will get reified into a
SCEVUnionPredicate.

Reviewers: silviu.baranga, sbaranga

Subscribers: sanjoy, mcrosier, llvm-commits, mzolotukhin

Differential Revision: https://reviews.llvm.org/D25000

llvm-svn: 282606
2016-09-28 17:14:58 +00:00
Nirav Dave e524f50882 Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled."
This reverts commit r282600 due to test failues with MCJIT

llvm-svn: 282604
2016-09-28 16:37:50 +00:00
Dylan McKay 1f69cdb321 [AVR] Rename the builtin calling convention names
'BUILTIN' is clearer than 'RT' in this context.

llvm-svn: 282602
2016-09-28 16:04:40 +00:00
Marina Yatsina 76bfc6670b [x86] Accept 'retn' as an alias to 'ret[lqw]'\'ret' (At&t\Intel)
Implement 'retn' simply by aliasing it to the relevant 'ret' instruction

Commit on behalf of coby

Differential Revision: https://reviews.llvm.org/D24346

llvm-svn: 282601
2016-09-28 15:52:56 +00:00
Nirav Dave e17e055b75 In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Simplify Consecutive Merge Store Candidate Search

  Now that address aliasing is much less conservative, push through
  simplified store merging search which only checks for parallel stores
  through the chain subgraph. This is cleaner as the separation of
  non-interfering loads/stores from the store-merging logic.

  Whem merging stores, search up the chain through a single load, and
  finds all possible stores by looking down from through a load and a
  TokenFactor to all stores visited. This improves the quality of the
  output SelectionDAG and generally the output CodeGen (with some
  exceptions).

  Additional Minor Changes:

    1. Finishes removing unused AliasLoad code
    2. Unifies the the chain aggregation in the merged stores across
       code paths
    3. Re-add the Store node to the worklist after calling
       SimplifyDemandedBits.
    4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
       arbitrary, but seemed sufficient to not cause regressions in
       tests.

  This finishes the change Matt Arsenault started in r246307 and
  jyknight's original patch.

  Many tests required some changes as memory operations are now
  reorderable. Some tests relying on the order were changed to use
  volatile memory operations

  Noteworthy tests:

    CodeGen/AArch64/argument-blocks.ll -
      It's not entirely clear what the test_varargs_stackalign test is
      supposed to be asserting, but the new code looks right.

    CodeGen/AArch64/arm64-memset-inline.lli -
    CodeGen/AArch64/arm64-stur.ll -
    CodeGen/ARM/memset-inline.ll -
      The backend now generates *worse* code due to store merging
      succeeding, as we do do a 16-byte constant-zero store efficiently.

    CodeGen/AArch64/merge-store.ll -
      Improved, but there still seems to be an extraneous vector insert
      from an element to itself?

    CodeGen/PowerPC/ppc64-align-long-double.ll -
      Worse code emitted in this case, due to the improved store->load
      forwarding.

    CodeGen/X86/dag-merge-fast-accesses.ll -
    CodeGen/X86/MergeConsecutiveStores.ll -
    CodeGen/X86/stores-merging.ll -
    CodeGen/Mips/load-store-left-right.ll -
      Restored correct merging of non-aligned stores

    CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll -
      Improved. Correctly merges buffer_store_dword calls

    CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll -
      Improved. Sidesteps loading a stored value and merges two stores

    CodeGen/X86/pr18023.ll -
      This test has been removed, as it was asserting incorrect
      behavior. Non-volatile stores *CAN* be moved past volatile loads,
      and now are.

    CodeGen/X86/vector-idiv.ll -
    CodeGen/X86/vector-lzcnt-128.ll -
      It's basically impossible to tell what these tests are actually
      testing. But, looks like the code got better due to the memory
      operations being recognized as non-aliasing.

    CodeGen/X86/win32-eh.ll -
      Both loads of the securitycookie are now merged.

    CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll -
      This test appears to work but no longer exhibits the spill
      behavior.

Reviewers: arsenm, hfinkel, tstellarAMD, nhaehnle, jyknight

Subscribers: wdng, nhaehnle, nemanjai, arsenm, weimingz, niravd, RKSimon, aemerson, qcolombet, resistor, tstellarAMD, t.p.northover, spatel

Differential Revision: https://reviews.llvm.org/D14834

llvm-svn: 282600
2016-09-28 15:50:43 +00:00
Dylan McKay 536239f144 [AVR] Import the LLVM namespace inside AVRMCTargetDesc.cpp
llvm-svn: 282598
2016-09-28 15:35:26 +00:00
Dylan McKay e762094864 [AVR] Add AVRMCTargetDesc.cpp
Summary:
This adds the AVRMCTargetDesc file in tree. It allows creation of the
core classes used in the backend.

Reviewers: arsenm, kparzysz

Subscribers: wdng, beanz, mgorny

Differential Revision: https://reviews.llvm.org/D25023

llvm-svn: 282597
2016-09-28 15:31:12 +00:00
Dylan McKay d6e7fc6d9a [AVR] Update the signature of createAVRAsmBackend
It has been recently changed to also take a MCTargetOptions structure.

llvm-svn: 282594
2016-09-28 14:35:07 +00:00
Dylan McKay f010a2b41a [AVR] Enable the assembly parser
We very recently landed the code. This commit enables the parser.

It also adds a missing include to AVRAsmParser.cpp

llvm-svn: 282593
2016-09-28 14:34:42 +00:00