224340cabe
MC/X86: Push immediate operands as immediates not expressions when possible.
...
llvm-svn: 96055
2010-02-13 00:17:21 +00:00
01f88a96c5
Make PassRegistrar thread-safe since it can be modified by code running in
...
separate LLVMContexts.
llvm-svn: 96051
2010-02-13 00:03:17 +00:00
064e926362
Remove special cases for [LM]FENCE, MONITOR and MWAIT from
...
encoder and decoder by using new MRM_ forms.
llvm-svn: 96048
2010-02-12 23:54:57 +00:00
1e827fd8ca
implement the rest of correct x86-64 encoder support for
...
rip-relative addresses, and add a testcase.
llvm-svn: 96040
2010-02-12 23:24:09 +00:00
626b79d6a6
Add the problem I just hacked around in 96015/96020.
...
The solution there produces correct code, but is seriously
deficient in several ways.
llvm-svn: 96039
2010-02-12 23:16:24 +00:00
741580a5bd
give MCCodeEmitters access to the current MCContext.
...
llvm-svn: 96038
2010-02-12 23:12:47 +00:00
2d36eb6e18
Make JIT::runFunction clean up the generated stub function.
...
Patch by Shivram K!
llvm-svn: 96037
2010-02-12 23:05:31 +00:00
4ad96055fb
implement infrastructure to support fixups for rip-rel
...
addressing. This isn't complete because I need an MCContext
to generate new MCExprs.
llvm-svn: 96036
2010-02-12 23:00:36 +00:00
29a9103ee6
Add YIELD, WFE, WFI, and SEV instructions for disassembly only.
...
Plus add two formats: MiscFrm and ThumbMiscFrm. Some of the for disassembly
only instructions are changed from Pseudo Format to MiscFrm Format.
llvm-svn: 96032
2010-02-12 22:53:19 +00:00
d18320361f
pull the rip-relative addressing mode case up early.
...
llvm-svn: 96031
2010-02-12 22:47:55 +00:00
6c1c0141be
fixme resolved!
...
llvm-svn: 96029
2010-02-12 22:39:06 +00:00
0055e75249
start producing reloc_pcrel_4byte/reloc_pcrel_1byte for calls.
...
llvm-svn: 96028
2010-02-12 22:36:47 +00:00
12455ca03d
enhance the immediate field encoding to know whether the immediate
...
is pc relative or not, mark call and branches as pcrel.
llvm-svn: 96026
2010-02-12 22:27:07 +00:00
439bda9d3f
Load / store multiple instructions cannot load / store sp. Sorry, can't come up with a reasonable test case.
...
llvm-svn: 96023
2010-02-12 22:17:21 +00:00
cb39340b81
This should have gone in with 26015, see comments there.
...
llvm-svn: 96020
2010-02-12 22:00:40 +00:00
dc2051c802
Add halfword multiply accumulate long SMLALBB/BT/TB/TT for disassembly only.
...
llvm-svn: 96019
2010-02-12 21:59:23 +00:00
26062150fa
When save/restoring CR at prolog/epilog, in a large
...
stack frame, the prolog/epilog code was using the same
register for the copy of CR and the address of the save slot. Oops.
This is fixed here for Darwin, sort of, by reserving R2 for this case.
A better way would be to do the store before the decrement of SP,
which is safe on Darwin due to the red zone.
SVR4 probably has the same problem, but I don't know how to fix it;
there is no red zone and R2 is already used for something else.
I'm going to leave it to someone interested in that target.
Better still would be to rewrite the CR-saving code completely;
spilling each CR subregister individually is horrible code.
llvm-svn: 96015
2010-02-12 21:35:34 +00:00
392be58cad
Add support for a union type in LLVM IR. Patch by Talin!
...
llvm-svn: 96011
2010-02-12 20:49:41 +00:00
bdf1b9520c
Add SWP (Swap) and SWPB (Swap Byte) for disassembly only.
...
llvm-svn: 96010
2010-02-12 20:48:24 +00:00
545d36019b
Also recognize armv6t2-* and armv5te-* triplets.
...
llvm-svn: 96008
2010-02-12 20:39:35 +00:00
1a8674e60b
Fix a case of mismatched types in an Add that turned up in 447.dealII.
...
llvm-svn: 96007
2010-02-12 20:39:25 +00:00
9aa30fbe02
Add ARM bitcode file magic.
...
llvm-svn: 96006
2010-02-12 20:13:44 +00:00
2b75de97c0
Reapply 95979, a compile-time speedup, now that the bug it exposed is fixed.
...
llvm-svn: 96005
2010-02-12 19:35:25 +00:00
363f847ec6
Fix this code to avoid dereferencing an end() iterator in
...
offset distributions it doesn't expect.
llvm-svn: 96002
2010-02-12 19:20:37 +00:00
cf20cbec49
Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only.
...
llvm-svn: 95999
2010-02-12 18:55:33 +00:00
30d99f4b9b
Rewrite handling of DBG_VALUE; previous algorithm
...
didn't handle
X =
Y<dead> = use X
DBG_VALUE(X)
I was hoping to avoid this approach as it's slower,
but I don't think it can be done.
llvm-svn: 95996
2010-02-12 18:40:17 +00:00
75879be9d8
1. modernize the constantmerge pass, using densemap/smallvector.
...
2. don't bother trying to merge globals in non-default sections,
doing so is quite dubious at best anyway.
3. fix a bug reported by Arnaud de Grandmaison where we'd try to
merge two globals in different address spaces.
llvm-svn: 95995
2010-02-12 18:17:23 +00:00
e0b2c69d3c
Revert "Reverse the order for collecting the parts of an addrec. The order", it
...
is breaking llvm-gcc bootstrap.
llvm-svn: 95988
2010-02-12 17:27:08 +00:00
c3c357006e
Setup correct data layout to match gcc's expectations on mingw32.
...
llvm-svn: 95981
2010-02-12 15:28:56 +00:00
c9276dfe04
Cleanup stdcall / fastcall name mangling.
...
This should fix alot of problems we saw so far, e.g. PRs 5851 & 2936
llvm-svn: 95980
2010-02-12 15:28:40 +00:00
0194f58047
Reverse the order for collecting the parts of an addrec. The order
...
doesn't matter, except that ScalarEvolution tends to need less time
to fold the results this way.
llvm-svn: 95979
2010-02-12 11:08:26 +00:00
45774ce0ad
Reapply the new LoopStrengthReduction code, with compile time and
...
bug fixes, and with improved heuristics for analyzing foreign-loop
addrecs.
This change also flattens IVUsers, eliminating the stride-oriented
groupings, which makes it easier to work with.
llvm-svn: 95975
2010-02-12 10:34:29 +00:00
c7ef4cc9fc
* Updated the cost matrix normalization proceedure to better handle infinite costs.
...
* Enabled R1/R2 application for nodes with infinite spill costs in the Briggs heuristic (made
safe by the changes to the normalization proceedure).
* Removed a redundant header.
llvm-svn: 95973
2010-02-12 09:43:37 +00:00
f7477e599f
add a bunch of mod/rm encoding types for fixed mod/rm bytes.
...
This will work better for the disassembler for modeling things
like lfence/monitor/vmcall etc.
llvm-svn: 95960
2010-02-12 02:06:33 +00:00
44ac89f517
revert r95949, it turns out that adding new prefixes is not a
...
great solution for the disassembler, we'll go with "plan b".
llvm-svn: 95957
2010-02-12 01:55:31 +00:00
905a2d7727
Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2,
...
MRRC, MRRc2. For disassembly only.
llvm-svn: 95955
2010-02-12 01:44:23 +00:00
0827e040e0
Add a new pass on machine instructions to optimize away PHI cycles that
...
reduce down to a single value. InstCombine already does this transformation
but DAG legalization may introduce new opportunities. This has turned out to
be important for ARM where 64-bit values are split up during type legalization:
InstCombine is not able to remove the PHI cycles on the 64-bit values but
the separate 32-bit values can be optimized. I measured the compile time
impact of this (running llc on 176.gcc) and it was not significant.
llvm-svn: 95951
2010-02-12 01:30:21 +00:00
d7e9212e2d
X86: Fix definition for RCL/RCR.*m? operations -- they were getting represented
...
with "tied memory operands", which is wrong.
llvm-svn: 95950
2010-02-12 01:22:03 +00:00
336f9abb45
add another bit of space for new kinds of instruction prefixes.
...
llvm-svn: 95949
2010-02-12 01:15:16 +00:00
c780af6471
Add a missing pattern for movhps so that we get:
...
movq (%ecx,%edx,2), %xmm2
movhps (%ecx,%eax,2), %xmm2
rather than:
movq (%eax, %edx, 2), %xmm2
movq (%eax, %ebx, 2), %xmm3
movlhps %xmm3, %xmm2
Testcase forthcoming.
llvm-svn: 95948
2010-02-12 01:10:45 +00:00
1572e760bc
fix the encodings of monitor and mwait, which were completely
...
busted in both encoders. I'm not bothering to fix it in the
old one at this point.
llvm-svn: 95947
2010-02-12 01:06:22 +00:00
62f50dad8d
improve support for minix, PR6280, patch by
...
Kees van Reeuwijk!
llvm-svn: 95946
2010-02-12 00:37:46 +00:00
be5557e86b
Add a new function attribute, 'alignstack'. It will indicate (when the backends
...
implement support for it) that the stack should be forcibly realigned in the
prologue (and the process reversed in the epilogue).
llvm-svn: 95945
2010-02-12 00:31:15 +00:00
93c92225af
Reapply coalescer fix for better cross-class coalescing.
...
This time with fixed test cases.
llvm-svn: 95938
2010-02-11 23:55:29 +00:00
b1913c4df9
enhance llvm-mc -show-inst to print the enum of an instruction, like so:
...
testb %al, %al ## <MCInst #2412 TEST8rr
## <MCOperand Reg:2>
## <MCOperand Reg:2>>
jne LBB1_7 ## <MCInst #938 JNE_1
## <MCOperand Expr:(LBB1_7)>>
llvm-svn: 95935
2010-02-11 22:57:32 +00:00
524138176d
add a new MCInstPrinter::getOpcodeName interface, when it is
...
implemented, llvm-mc --show-inst now uses it to print the
instruction opcode as well as the number.
llvm-svn: 95929
2010-02-11 22:39:10 +00:00
b8af65ed0b
improve encoding information for branches. We now know they have
...
8 or 32-bit immediates, which allows the new encoder to handle
them.
llvm-svn: 95927
2010-02-11 21:45:31 +00:00
1d34759721
MC: Move assembler-backend's fixup list into the fragment.
...
llvm-svn: 95926
2010-02-11 21:29:46 +00:00
ee82e763e6
MC: Move MCSectionData::Fixup out to MCAsmFixup.
...
llvm-svn: 95925
2010-02-11 21:29:29 +00:00
ddeceae839
make getFixupKindInfo return a const reference, allowing
...
the tables to be const. Teach MCCodeEmitter to handle
the target-indep kinds so that we don't crash on them.
llvm-svn: 95924
2010-02-11 21:27:18 +00:00
0d642824d6
Revert functional change. This broke a bunch of tests.
...
llvm-svn: 95921
2010-02-11 21:19:44 +00:00
2a34015abc
switch to target-indep fixups for 1/2/4/8 byte data.
...
llvm-svn: 95920
2010-02-11 21:17:54 +00:00
c07f1f4f7b
revert 95903.
...
llvm-svn: 95918
2010-02-11 20:58:56 +00:00
28139f0043
It is always good to do a cross-class join when the large register has a tiny interval.
...
Also avoid division by zero.
llvm-svn: 95917
2010-02-11 20:58:45 +00:00
af88c0a84d
Added LDRT/LDRBT/STRT/STRBT for disassembly only.
...
llvm-svn: 95916
2010-02-11 20:31:08 +00:00
1f298326b0
unbreak the build.
...
llvm-svn: 95915
2010-02-11 19:52:11 +00:00
11ddc679ca
Destroy MDNodes while destructing llvm context.
...
llvm-svn: 95903
2010-02-11 19:35:10 +00:00
2b0a7a2592
refactor the conditional jump instructions in the .td file to
...
use a multipattern that generates both the 1-byte and 4-byte
versions from the same defm
llvm-svn: 95901
2010-02-11 19:25:55 +00:00
3964059a16
Forgot to also check in this file for vcvt (floating-point <-> fixed-point, VFP).
...
Sorry!
llvm-svn: 95892
2010-02-11 18:47:03 +00:00
177ced3953
Allow for more than one DBG_VALUE targeting the
...
same dead instruction.
llvm-svn: 95890
2010-02-11 18:23:23 +00:00
12565de705
Don't allow DBG_VALUE to affect codegen.
...
llvm-svn: 95889
2010-02-11 18:22:31 +00:00
2588efd071
Added VCVT (between floating-point and fixed-point, VFP) for disassembly.
...
A8.6.297
llvm-svn: 95885
2010-02-11 18:17:16 +00:00
f40b8e03fb
Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose.
...
llvm-svn: 95884
2010-02-11 18:12:29 +00:00
45396438c3
Use array_pod_sort instead of std::sort for improved code size.
...
Use SmallVector instead of std::vector for better speed when indirectbr has
few successors.
llvm-svn: 95879
2010-02-11 18:06:56 +00:00
cccdc13662
Make sure that ConstantExpr offsets also aren't off of extern
...
symbols.
Thanks to Duncan Sands for the testcase!
llvm-svn: 95877
2010-02-11 17:44:04 +00:00
9c13dfb5dd
Add pseudo instruction TRAP for disassembly, which is encoded according to A5-21
...
as the "Permanently UNDEFINED" instruction.
llvm-svn: 95873
2010-02-11 17:14:31 +00:00
243e1f21db
Use .empty() instead of .size().
...
llvm-svn: 95871
2010-02-11 10:37:57 +00:00
fbf1f02fee
dont' call getX86RegNum on X86::RIP, it doesn't like that. This
...
fixes the remaining x86-64 jit failures afaik.
llvm-svn: 95867
2010-02-11 08:45:56 +00:00
5a4ec879bf
fix a really nasty bug I introduced in r95693: r12 (and r12d,
...
r12b, etc) also encodes to a R/M value of 4, which is just
as illegal as ESP/RSP for the non-sib version an address.
This fixes x86-64 jit miscompilations of a bunch of programs.
llvm-svn: 95866
2010-02-11 08:41:21 +00:00
6bb2463f85
Add and commonize encoder support for all immediates.
...
Stub out some dummy fixups to make things work.
We can now emit fixups like this:
subl $20, %esp ## encoding: [0x83,0xec,A]
## fixup A - offset: 2, value: 20, kind: fixup_1byte_imm
Emitting $20 as a single-byte fixup to be later resolved
by the assembler is ridiculous of course (vs just emitting
the byte) but this is a failure of the matcher, which
should be producing an imm of 20, not an MCExpr of 20.
llvm-svn: 95860
2010-02-11 07:06:31 +00:00
167842f90b
generalize EmitDisplacementField to work with any size
...
and rename it to EmitImmediate.
llvm-svn: 95859
2010-02-11 06:54:23 +00:00
3555993312
eliminate the dead IsPCRel argument.
...
llvm-svn: 95858
2010-02-11 06:51:36 +00:00
5a40e6c95c
eliminate the dead "PCAdj" logic.
...
llvm-svn: 95857
2010-02-11 06:49:52 +00:00
c660b23075
Fix some of the memcheck errors found in the JIT unittests.
...
llvm-svn: 95856
2010-02-11 06:41:30 +00:00
4e8137d678
Rename ValueRequiresCast to ShouldOptimizeCast, to better reflect
...
what it does. Enhance it to return false to optimizing vector
sign extensions from vector comparisions, which is the idiom used
to get a splatted vector for a vector comparison.
Doing this breaks vector-casts.ll, add some compensating
transformations to handle the important case they cover without
depending on this canonicalization.
This fixes rdar://7434900 a serious pessimization of vector compares.
llvm-svn: 95855
2010-02-11 06:26:33 +00:00
c053cbbc4d
Make DSE only scan blocks that are reachable from the entry
...
block. Other blocks may have pointer cycles that will crash
basicaa and other alias analyses. In any case, there is no
point wasting cycles optimizing dead blocks. This fixes
rdar://7635088
llvm-svn: 95852
2010-02-11 05:11:54 +00:00
d924f63692
Make jump threading honor x|undef -> true and x&undef -> false,
...
instead of considering x|undef -> x, which may not be true.
llvm-svn: 95850
2010-02-11 04:40:44 +00:00
531ea566a6
Add ConstantExpr handling to Intrinsic::objectsize lowering.
...
Update testcase accordingly now that we can optimize another
section.
llvm-svn: 95846
2010-02-11 01:48:54 +00:00
7c2005aa6d
Fix to get it to compile.
...
llvm-svn: 95840
2010-02-11 01:15:27 +00:00
6034260c43
Don't print out a default newline when emitting the section offset. There are
...
almost always comments afterwards that need printing.
llvm-svn: 95839
2010-02-11 01:13:02 +00:00
e0913883b7
Make it possible to create multiple JIT instances at the same time, by removing
...
the global TheJIT and TheJITResolver variables. Lazy compilation is supported
by a global map from a stub address to the JITResolver that knows how to
compile it.
Patch by Olivier Meurant!
llvm-svn: 95837
2010-02-11 01:07:39 +00:00
75521cab3e
Reuse operand location when updating PHI instructions.
...
Calling RemoveOperand is very expensive on huge PHI instructions. This makes
early tail duplication run twice as fast on the Firefox JavaScript
interpreter.
llvm-svn: 95832
2010-02-11 00:34:33 +00:00
896428d630
Remove duplicate successors from indirectbr instructions before building the machine CFG.
...
This makes early tail duplication run 60 times faster when compiling the Firefox
JavaScript interpreter, see PR6186.
llvm-svn: 95831
2010-02-11 00:34:18 +00:00
03936a1880
Ignore dbg info intrinsics.
...
llvm-svn: 95828
2010-02-11 00:20:49 +00:00
5b77f0dac1
The previous fix of widening divides that trap was too fragile as it depends on custom
...
lowering and requires that certain types exist in ValueTypes.h. Modified widening to
check if an op can trap and if so, the widening algorithm will apply only the op on
the defined elements. It is safer to do this in widening because the optimizer can't
guarantee removing unused ops in some cases.
llvm-svn: 95823
2010-02-10 23:37:45 +00:00
af3fe99821
Ignore debug info one more place during coalescing.
...
llvm-svn: 95819
2010-02-10 23:04:09 +00:00
0f52d0c074
Delete dead PHI machine instructions. These can be created due to type
...
legalization even when the IR-level optimizer has removed dead phis, such
as when the high half of an i64 value is unused on a 32-bit target.
I had to adjust a few test cases that had dead phis.
This is a partial fix for Radar 7627077.
llvm-svn: 95816
2010-02-10 22:58:57 +00:00
8bba1608bd
Skip debug info in a couple of places.
...
llvm-svn: 95814
2010-02-10 21:47:48 +00:00
7742b6406b
Use an index instead of pointers into the vector. If the vector resizes, then
...
the pointer values could be invalid.
llvm-svn: 95813
2010-02-10 21:41:57 +00:00
1ccda7b7c4
When I rewrote this loop per Chris' preference I
...
changed its behavior. Oops.
llvm-svn: 95811
2010-02-10 21:41:41 +00:00
4d4c6944e9
A few missed optimizations; the last one could have a significant impact on
...
code with lots of bitfields.
llvm-svn: 95809
2010-02-10 21:26:04 +00:00
211746a69a
Strip new llvm.dbg.value intrinsic.
...
llvm-svn: 95807
2010-02-10 21:19:56 +00:00
3e0c9790f2
MC/X86 AsmMatcher: Fix a use after free spotted by d0k, and de-XFAIL
...
x86_32-encoding.s in on expectation of it passing.
llvm-svn: 95806
2010-02-10 21:19:28 +00:00
bd11c41b91
Minor whitespace cleanups.
...
llvm-svn: 95801
2010-02-10 20:42:57 +00:00
c42c5243a1
Use an AssemblyAnnotatorWriter to clean up IVUsers' debug output.
...
The "uses=" comments are just clutter in this context.
llvm-svn: 95799
2010-02-10 20:42:37 +00:00
e34890f921
Add a hook to AssemblyAnnotationWriter to allow custom info comments
...
to be printed, in place of the familiar "uses=" comments.
llvm-svn: 95798
2010-02-10 20:41:46 +00:00
97c5902e78
Fix several comments which had previously been "the the" where a
...
different word was intended.
llvm-svn: 95795
2010-02-10 20:04:19 +00:00
c7e14704d0
Added NOP, DBG, SVC to the instruction table for disassembly purpose.
...
llvm-svn: 95784
2010-02-10 18:02:25 +00:00
4a618827de
Fix "the the" and similar typos.
...
llvm-svn: 95781
2010-02-10 16:03:48 +00:00
de03bd0ab4
emit some simple (and probably incorrect) fixups for symbolic
...
displacement values.
llvm-svn: 95773
2010-02-10 06:52:12 +00:00
f58d0074d7
keep track of what the current byte being emitted is
...
throughout the X86 encoder.
llvm-svn: 95771
2010-02-10 06:41:02 +00:00
a725d785a9
simplify displacement handling, emit displacements by-operand
...
even for the immediate case. No functionality change.
llvm-svn: 95770
2010-02-10 06:30:00 +00:00
183a423af9
Canonicalize sizeof and alignof on pointer types to a canonical
...
pointer type.
llvm-svn: 95769
2010-02-10 06:13:07 +00:00
605474463f
MC: Switch MCFixup to just hold an MCExpr pointer instead of index into the
...
MCInst it came from.
llvm-svn: 95767
2010-02-10 04:47:08 +00:00
29b8f554fc
Now that ShrinkDemandedOps() is separated out from DAG combine. It sometimes leave some obvious nops which dag combine used to clean up afterwards e.g. (trunk (ext n)) -> n. Look for them and squash them.
...
llvm-svn: 95757
2010-02-10 02:17:34 +00:00
75c9a4eeae
llvm-mc: Remove --show-fixups and always show as part of --show-encoding.
...
Also, fix a silly memory leak.
llvm-svn: 95752
2010-02-10 01:41:14 +00:00
f8b0e44584
Rewrite loop to suit Chris' preference.
...
llvm-svn: 95749
2010-02-10 01:31:26 +00:00
ea26fa9971
fix a layering violation: VirtRegRewriter.cpp shouldn't use AsmPrinter.h.
...
llvm-svn: 95748
2010-02-10 01:23:18 +00:00
0a75ceee38
Remove duplicated #include.
...
llvm-svn: 95747
2010-02-10 01:22:57 +00:00
3ebd551aac
Emit an error for illegal inline asm constraint (which uses illegal type) rather than asserting.
...
llvm-svn: 95746
2010-02-10 01:21:02 +00:00
c9505b68c8
fix missing #includes.
...
llvm-svn: 95745
2010-02-10 01:17:36 +00:00
69920c5c8a
daniel *really* likes fixups!
...
llvm-svn: 95742
2010-02-10 01:05:28 +00:00
a0cd0e11c9
Improve comments a even more.
...
llvm-svn: 95740
2010-02-10 00:59:47 +00:00
f8f9f55468
Skip DBG_VALUE many places in live intervals and
...
register coalescing. This fixes many crashes and
places where debug info affects codegen (when
dbg.value is lowered to machine instructions, which
it isn't yet in TOT).
llvm-svn: 95739
2010-02-10 00:55:42 +00:00
74e6852510
Move verbose asm instruction comments to using MCStreamer.
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The major win of this is that the code is simpler and they
print on the same line as the instruction again:
movl %eax, 96(%esp) ## 4-byte Spill
movl 96(%esp), %eax ## 4-byte Reload
cmpl 92(%esp), %eax ## 4-byte Folded Reload
jl LBB7_86
llvm-svn: 95738
2010-02-10 00:47:53 +00:00
b188e92ca9
Improve comments a bit more.
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llvm-svn: 95737
2010-02-10 00:45:28 +00:00
222c75bea2
more comment updates
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llvm-svn: 95736
2010-02-10 00:44:23 +00:00
d40d42c9e5
Add isDebug argument to ChangeToRegister; this prevents
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the field from being used uninitialized later in some cases.
llvm-svn: 95735
2010-02-10 00:41:49 +00:00
ff68a42121
print all the newlines at the end of instructions with
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OutStreamer.AddBlankLine instead of textually.
llvm-svn: 95734
2010-02-10 00:36:00 +00:00
08f618cd03
IntegerValType holds a uint32_t, so its constructor should take a uint32_t. This allows it to be properly initialized with bit widths > 65535
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llvm-svn: 95731
2010-02-10 00:14:03 +00:00
3d1f1cccbb
Fix comments to reflect renaming elsewhere.
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llvm-svn: 95730
2010-02-10 00:11:11 +00:00
a7c1d6cfd1
Fix the encoding of the movntdqa X86 instruction. It was missing the 0x66
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prefix which is part of the opcode encoding.
llvm-svn: 95729
2010-02-10 00:10:31 +00:00
482bf69bfe
Add ability for MCInstPrinters to add comments for instructions.
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Enhance the x86 backend to show the hex values of immediates in
comments when they are large. For example:
movl $1072693248, 4(%esp) ## imm = 0x3FF00000
llvm-svn: 95728
2010-02-10 00:10:18 +00:00
509be1fe5e
TableGen fragment refactoring.
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Move some utility TableGen defs, classes, etc. into a common file so
they may be used my multiple pattern files. We will use this for
the AVX specification to help with the transition from the current
SSE specification.
llvm-svn: 95727
2010-02-09 23:52:19 +00:00
1215c774f2
Add VBIF/VBIT for disassembly only.
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A8.6.279
llvm-svn: 95713
2010-02-09 23:05:23 +00:00
893047d43e
Only dump output in debug mode.
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llvm-svn: 95711
2010-02-09 23:03:05 +00:00
9a0a46163d
llvm-mc: Add --show-fixups option, for displaying the instruction fixup information in the asm comments.
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llvm-svn: 95710
2010-02-09 23:00:14 +00:00
0e42dc0dac
MC/X86: Add a dummy implementation of MCFixup generation for hacky X86 MCCodeEmitter.
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llvm-svn: 95709
2010-02-09 23:00:03 +00:00
b311a6b3ae
MC: First cut at MCFixup, for getting fixup/relocation information out of an MCCodeEmitter.
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llvm-svn: 95708
2010-02-09 22:59:55 +00:00
bf02536262
Improve comments in the LSDA somewhat. They can be improved much more.
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llvm-svn: 95707
2010-02-09 22:49:16 +00:00
b618f66c5f
Added VMRS/VMSR for disassembly only.
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A8.6.335 & A8.6.336
llvm-svn: 95703
2010-02-09 22:35:38 +00:00
8aef06f8eb
port encoder enhancements over to the new encoder.
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llvm-svn: 95699
2010-02-09 21:57:34 +00:00
0c3b66cd87
fix X86 encoder to output [disp] only addresses with no SIB byte
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in X86-32 mode. This is still required in x86-64 mode to avoid
forming [disp+rip] encoding. Rewrite the SIB byte decision logic
to be actually understandable.
llvm-svn: 95693
2010-02-09 21:47:19 +00:00
7b7028fd24
Move Intrinsic::objectsize lowering back to InstCombineCalls and
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enable constant 0 offset lowering.
llvm-svn: 95691
2010-02-09 21:24:27 +00:00
45d89644ae
revert r95689: getX86RegNum(BaseReg) != N86::ESP is
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a confusing idiom to check for ESP or RSP.
llvm-svn: 95690
2010-02-09 21:21:26 +00:00
e464a4d815
simplify.
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llvm-svn: 95689
2010-02-09 21:00:12 +00:00
b06015aa69
move target-independent opcodes out of TargetInstrInfo
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into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
llvm-svn: 95687
2010-02-09 19:54:29 +00:00
f7279bd10f
Radar 7417921
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tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.
llvm-svn: 95686
2010-02-09 19:51:37 +00:00
ad1aa86276
Pull these back out, they're a little too aggressive and time
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consuming for a simple optimization.
llvm-svn: 95671
2010-02-09 17:29:18 +00:00
64e0ae8dd4
Added vcvtb/vcvtt (between half-precision and single-precision, VFP).
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For disassembly only.
A8.6.300
llvm-svn: 95669
2010-02-09 17:21:56 +00:00
d19418d112
Remember to update live-in lists when coalescing physregs.
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Patch by M Wahab!
llvm-svn: 95668
2010-02-09 17:20:11 +00:00
f5f335da37
move PR3462 to here.
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llvm-svn: 95650
2010-02-09 05:55:14 +00:00
cf11e602a2
add a note from PR6194
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llvm-svn: 95649
2010-02-09 05:45:29 +00:00
c3adf44885
Skip DEBUG_VALUE in some places where it was affecting codegen.
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llvm-svn: 95647
2010-02-09 02:01:46 +00:00
ce25dd74c0
Add declaration attribute to a variable DIE, if there is a separate DIE for the definition.
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llvm-svn: 95646
2010-02-09 01:58:33 +00:00
f4c8d3cea9
simplify this code, duh.
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llvm-svn: 95643
2010-02-09 01:14:06 +00:00
9b6a1789e5
fix PR6193, only considering sign extensions *from i1* for this
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xform.
llvm-svn: 95642
2010-02-09 01:12:41 +00:00
be2f0b2b7b
Add file in here too.
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llvm-svn: 95641
2010-02-09 01:11:03 +00:00
89261502cb
make -show-inst be formatted a bit nicer. Before:
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movl $3735928559, a ## inst: <MCInst 1273 <MCOperand Reg:0> <MCOperand Imm:1> <MCOperand Reg:0> <MCOperand Expr:(a)> <MCOperand Reg:0> <MCOperand Expr:(3735928559)>>
after:
movl $3735928559, a ## <MCInst #1273
## <MCOperand Reg:0>
## <MCOperand Imm:1>
## <MCOperand Reg:0>
## <MCOperand Expr:(a)>
## <MCOperand Reg:0>
## <MCOperand Expr:(3735928559)>>
llvm-svn: 95637
2010-02-09 00:54:51 +00:00
48121948dc
Fixed a bug in the PBQP allocator's findCoalesces method.
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Previously spill registers, whose def indexes are not defined, would sometimes be improperly marked as coalescable with conflicting registers. The new findCoalesces routine conservatively assumes that any register with at least one undefined def is not coalescable with any register it interferes with.
llvm-svn: 95636
2010-02-09 00:50:27 +00:00
Daniel Dunbar