Commit Graph

5886 Commits

Author SHA1 Message Date
James Molloy b47489d4ef Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends.
Fixes PR11877

llvm-svn: 149180
2012-01-28 15:58:32 +00:00
Jim Grosbach 20275a8577 Better user diagnostics for more ARM MachO relocation errors.
llvm-svn: 149102
2012-01-27 00:37:12 +00:00
Jim Grosbach 5e5eabb5ab Keep source information, if available, around for ARM Fixups.
Adjust an example MachObjectWriter diagnostic to use the information
to issue a better message.

Before:
LLVM ERROR: unknown ARM fixup kind!

After:
x.s:6:5: error: unsupported relocation on symbol
    beq bar
    ^

rdar://9800182

llvm-svn: 149093
2012-01-26 23:20:15 +00:00
Jim Grosbach c8f2b7877b Tidy up. Fix mismatched return types for error handling.
llvm-svn: 149062
2012-01-26 15:56:45 +00:00
James Molloy 6685c08e5f Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors.
This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.

llvm-svn: 149057
2012-01-26 09:25:43 +00:00
Anton Korobeynikov 7722a2d4e3 Properly emit ctors / dtors with priorities into desired sections
and let linker handle the rest.

This finally fixes PR5329

llvm-svn: 148990
2012-01-25 22:24:19 +00:00
Jim Grosbach 82f76d1275 ARM assemly parsing and validation of IT instruction.
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."

PR11853

llvm-svn: 148969
2012-01-25 19:52:01 +00:00
Jim Grosbach 086cbfac7d NEON VLD4(all lanes) assembly parsing and encoding.
llvm-svn: 148884
2012-01-25 00:01:08 +00:00
Jim Grosbach ccb6d55dae Tidy up. Rename VLD4DUP patterns for consistency.
llvm-svn: 148883
2012-01-24 23:47:07 +00:00
Jim Grosbach b78403ce48 NEON VLD3(all lanes) assembly parsing and encoding.
llvm-svn: 148882
2012-01-24 23:47:04 +00:00
Jim Grosbach 8e2722cdb0 NEON VST4(one lane) assembly parsing and encoding.
llvm-svn: 148836
2012-01-24 18:53:13 +00:00
Owen Anderson d845d9d9e9 Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.
llvm-svn: 148833
2012-01-24 18:37:29 +00:00
Jim Grosbach 14952a0e32 NEON VLD4(one lane) assembly parsing and encoding.
llvm-svn: 148832
2012-01-24 18:37:25 +00:00
Jim Grosbach 3cfef8d467 NEON Two-operand assembly aliases for VSRA.
llvm-svn: 148821
2012-01-24 17:55:36 +00:00
Jim Grosbach 7ae12cc546 NEON Two-operand assembly aliases for VSLI.
llvm-svn: 148819
2012-01-24 17:49:15 +00:00
Jim Grosbach 7b6f0f67aa NEON Two-operand assembly aliases for VSRI.
llvm-svn: 148818
2012-01-24 17:46:58 +00:00
Jim Grosbach 681db34eae NEON add correct predicates for some asm aliases.
llvm-svn: 148815
2012-01-24 17:23:29 +00:00
Anton Korobeynikov 3cad0c21ed Use correct register class for am2offset register operands.
This pacifies machine verifier

llvm-svn: 148782
2012-01-24 04:58:56 +00:00
Jim Grosbach da70eac268 NEON VST4(multiple 4 element structures) assembly parsing.
llvm-svn: 148764
2012-01-24 00:58:13 +00:00
Jim Grosbach ed561fc850 NEON VLD4(multiple 4 element structures) assembly parsing.
llvm-svn: 148762
2012-01-24 00:43:17 +00:00
Jim Grosbach 1e946a4f91 Tidy up. Remove some vertical space for readability.
llvm-svn: 148761
2012-01-24 00:43:12 +00:00
Chandler Carruth ed975232bc Revert r148686 (and r148694, a fix to it) due to a serious layering
violation -- MC cannot depend on CodeGen.

Specifically, the MCTargetDesc component of each target is actually
a subcomponent of the MC library. As such, it cannot depend on the
target-independent code generator, because MC itself cannot depend on
the target-independent code generator. This change moved a flag from the
ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in
ARMException.cpp, leaving behind an 'extern' to refer back to it. That
layering order isn't viable givin the constraints outlined above.
Commandline flags are designed to be static specifically to avoid these
types of bugs.

Fixing this is likely going to require some non-trivial refactoring.

llvm-svn: 148759
2012-01-24 00:30:17 +00:00
Jim Grosbach 17bacab475 Fix typo.
llvm-svn: 148757
2012-01-24 00:12:39 +00:00
Jim Grosbach d3d36d9315 NEON VST3(single element from one lane) assembly parsing.
llvm-svn: 148755
2012-01-24 00:07:41 +00:00
Jim Grosbach 1a74724fc9 NEON VST3(multiple 3-element structures) assembly parsing.
llvm-svn: 148748
2012-01-23 23:45:44 +00:00
Jim Grosbach ac2af3ffab NEON VLD3(multiple 3-element structures) assembly parsing.
llvm-svn: 148745
2012-01-23 23:20:46 +00:00
Anton Korobeynikov 820417af07 Add missed mayStore flag to STREXD / t2STREXD
llvm-svn: 148742
2012-01-23 22:57:52 +00:00
Jim Grosbach a8b444b08b NEON VLD3 lane-indexed assembly parsing and encoding.
llvm-svn: 148734
2012-01-23 21:53:26 +00:00
Jim Grosbach d28ef9ac46 Simplify some NEON assembly pseudo definitions.
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.

llvm-svn: 148718
2012-01-23 19:39:08 +00:00
NAKAMURA Takumi 28ea8f523b ARMAsmPrinter.cpp: Try to fix up r148686. EnableARMEHABI was also here.
llvm-svn: 148694
2012-01-23 09:14:42 +00:00
Evgeniy Stepanov 482cdc4ebd An option to selectively enable parts of ARM EHABI support.
This change adds an new value to the --arm-enable-ehabi option that
disables emitting unwinding descriptors. This mode gives a working
backtrace() without the (currently broken) exception support.

llvm-svn: 148686
2012-01-23 07:57:39 +00:00
Anton Korobeynikov 5482b9f535 Add fused multiple+add instructions from VFPv4.
Patch by Ana Pazos!

llvm-svn: 148658
2012-01-22 12:07:33 +00:00
Jim Grosbach 78dcaed8ca Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction.
llvm-svn: 148601
2012-01-21 00:07:56 +00:00
David Blaikie 46a9f016c5 More dead code removal (using -Wunreachable-code)
llvm-svn: 148578
2012-01-20 21:51:11 +00:00
Bob Wilson 6c7aaec077 ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651>
We have patterns for vector sext and zext operations but were missing
anyext.  Without those patterns, codegen will fail when the selection DAG
has any_extend nodes.

llvm-svn: 148568
2012-01-20 20:59:56 +00:00
Jim Grosbach 90f5780fc1 VST2 four-register w/ update pseudos for fixed/register update.
rdar://10724489

llvm-svn: 148560
2012-01-20 19:16:00 +00:00
Jim Grosbach a9d36fbca7 NEON use vmov.i32 to splat some f32 values into vectors.
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.

rdar://10616677

llvm-svn: 148556
2012-01-20 18:09:51 +00:00
Benjamin Kramer 116e99a469 Silence warnings about mixing enums.
llvm-svn: 148495
2012-01-19 21:11:13 +00:00
Evgeniy Stepanov 4c7eb477b5 Emit ARM EHABI unwinding instructions for 3 more Thumb instructions.
llvm-svn: 148473
2012-01-19 12:53:06 +00:00
Jim Grosbach 235c8d2d94 ARM assembly diagnostic caret in better position for FPImm.
llvm-svn: 148459
2012-01-19 02:47:30 +00:00
Jim Grosbach 44e5c39c29 Thumb2 relaxation for tADR to t2ADR.
llvm-svn: 148456
2012-01-19 02:09:38 +00:00
Jim Grosbach b008df40d3 Add comment and fix range check in condition.
llvm-svn: 148455
2012-01-19 01:50:30 +00:00
Evan Cheng 2879467d4e - Slight change to finalizeBundle() interface. LastMI is not exclusive (pointing
to instruction right after the last instruction in the bundle.
- Add a finalizeBundle() variant that doesn't specify LastMI. Instead, the code
  will find the last instruction in the bundle by following the 'InsideBundle'
  marker. This is useful in case bundles are formed early (i.e. during MI
  scheduling) but finalized later (i.e. after register allocator has finished
  rewriting virtual registers with physical registers).

llvm-svn: 148444
2012-01-19 00:46:06 +00:00
Evan Cheng 1eb2bb2295 Rename Finalizebundle to finalizeBundle to conform to coding guideline.
llvm-svn: 148440
2012-01-19 00:06:10 +00:00
Jakob Stoklund Olesen f1fb1d2375 Ignore register mask operands when lowering instructions to MC.
This is similar to implicit register operands.  MC doesn't understand
register liveness and call clobbers.

llvm-svn: 148437
2012-01-18 23:52:19 +00:00
Jim Grosbach 94298a906a Thumb2 alternate syntax for LDR(literal) and friends.
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".

rdar://10250964

llvm-svn: 148432
2012-01-18 22:46:46 +00:00
Jim Grosbach cbd3f27354 Replace FIXME with explanatory comment.
llvm-svn: 148427
2012-01-18 22:04:42 +00:00
Jim Grosbach cb80eb2e75 Thumb2 relaxation for LDR(literal).
If the fixup is out of range for the Thumb1 instruction, relax it
to the Thumb2 encoding instead.

rdar://10711829

llvm-svn: 148424
2012-01-18 21:54:16 +00:00
Jim Grosbach 9ab3d8be4e Rename pattern for clarity.
llvm-svn: 148422
2012-01-18 21:54:09 +00:00
Jim Grosbach aba3de99c0 Tidy up. MCAsmBackend naming conventions.
llvm-svn: 148400
2012-01-18 18:52:16 +00:00