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103 Commits

Author SHA1 Message Date
Craig Topper a422b09ae3 Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions. 
llvm-svn: 192567
 2013-10-14 04:55:01 +00:00
Craig Topper 88adf2a49c Remove more filters from the disassembler. Mark some AVX512 instructions as CodeGenOnly. 
llvm-svn: 192525
 2013-10-12 05:41:08 +00:00
Craig Topper aab53e7785 Mark some more instructions as CodeGenOnly. Remove filters from the disassembler. 
llvm-svn: 192522
 2013-10-12 04:46:18 +00:00
Craig Topper 81034928c6 Remove another unnecessary filter from the disassembler. 
llvm-svn: 192425
 2013-10-11 06:59:57 +00:00
Craig Topper e1ceeb40c1 Fix so CRC32r64r8 isn't accidentally filtered from the disassembler tables. 
llvm-svn: 192339
 2013-10-10 04:26:52 +00:00
Craig Topper 2d0d180ab4 More x86 disassembler filtering cleanup. 
llvm-svn: 192279
 2013-10-09 06:12:53 +00:00
Craig Topper 043d749ba3 Remove some old filters from the x86 disassembler table builder. 
llvm-svn: 192275
 2013-10-09 05:02:29 +00:00
Craig Topper a984729f8a Remove unneeded MMX instruction definition by moving pattern to an equivalent instruction definition and removing the filtering from the disassembler table building. 
llvm-svn: 192175
 2013-10-08 06:30:39 +00:00
Craig Topper 72c8cd7bc3 Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. 
llvm-svn: 192171
 2013-10-08 05:53:50 +00:00
Craig Topper 07ad1b23bb Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead. 
llvm-svn: 192090
 2013-10-07 07:19:47 +00:00
Craig Topper 2658d89728 Add disassembler support for long encodings for INC/DEC in 32-bit mode. 
llvm-svn: 192086
 2013-10-07 04:28:06 +00:00
Craig Topper 9e3e38ae3f Add XOP disassembler support. Fixes PR13933. 
llvm-svn: 191874
 2013-10-03 05:17:48 +00:00
Elena Demikhovsky c35219e3ee AVX-512: Added masked SHIFT commands, more encoding tests 
llvm-svn: 189005
 2013-08-22 12:18:28 +00:00
Craig Topper 9469e906a5 Remove use of sprintf added to X86 disassembler tablegen code. Send message with instruction name to errs() instead and use a generic message for the llvm_unreachable. Consistent with other places in this file. 
llvm-svn: 187333
 2013-07-28 21:28:02 +00:00
Elena Demikhovsky baf51e3e61 fixed compilation issue 
llvm-svn: 187325
 2013-07-28 08:45:12 +00:00
Elena Demikhovsky 003e7d73b9 Added encoding prefixes for KNL instructions (EVEX). 
Added 512-bit operands printing.
Added instruction formats for KNL instructions.

llvm-svn: 187324
 2013-07-28 08:28:38 +00:00
Stefanus Du Toit 8811ad4f81 Add support for encoding the HLE XACQUIRE and XRELEASE prefixes. 
For decoding, keep the current behavior of always decoding these as their REP
versions. In the future, this could be improved to recognize the cases where
these behave as XACQUIRE and XRELEASE and decode them as such.

llvm-svn: 184207
 2013-06-18 17:08:10 +00:00
Michael Liao 95d9440348 Add CLAC/STAC instruction encoding/decoding support 
As these two instructions in AVX extension are privileged instructions for
special purpose, it's only expected to be used in inlined assembly.

llvm-svn: 179266
 2013-04-11 04:52:28 +00:00
Dave Zarzycki 656e8515fc x86 -- add the XTEST instruction 
llvm-svn: 177888
 2013-03-25 18:59:43 +00:00
Kevin Enderby f15856ebb4 Fixes disassembler crashes on 2013 Haswell RTM instructions. 
rdar://13318048

llvm-svn: 176828
 2013-03-11 21:17:13 +00:00
Kay Tiong Khoo ab588efe42 Added 0x0D to 2-byte opcode extension table for prefetch* variants 
Fixed decode of existing 3dNow prefetchw instruction
Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs

llvm-svn: 174920
 2013-02-12 00:19:12 +00:00
Chandler Carruth 91d19d8e93 Sort the #include lines for utils/... 
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.

llvm-svn: 169251
 2012-12-04 10:37:14 +00:00
Michael Liao 73cffddb95 Add support of RTM from TSX extension 
- Add RTM code generation support throught 3 X86 intrinsics:
  xbegin()/xend() to start/end a transaction region, and xabort() to abort a
  tranaction region

llvm-svn: 167573
 2012-11-08 07:28:54 +00:00
Craig Topper 3f23c1a8b9 Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. 
llvm-svn: 164204
 2012-09-19 06:37:45 +00:00
Craig Topper c30fdbc46c Add support for converting llvm.fma to fma4 instructions. 
llvm-svn: 162999
 2012-08-31 15:40:30 +00:00
Craig Topper c6b7ef61f4 Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code. 
llvm-svn: 160951
 2012-07-30 06:48:11 +00:00
Craig Topper 08ead0b14e Remove some unnecessary filter checks. They were already covered by IsCodeGenOnly 
llvm-svn: 160950
 2012-07-30 06:27:19 +00:00
Craig Topper 6f4ad80dc8 Remove check for sub class of X86Inst from filter function since caller guaranteed it. Replace another sub class check with ShouldBeEmitted flag since it was factored in there already. 
llvm-svn: 160949
 2012-07-30 05:39:34 +00:00
Craig Topper b58dc17025 Simplify code that filtered certain instructions in two different ways. No functional change. 
llvm-svn: 160948
 2012-07-30 05:10:05 +00:00
Craig Topper 60a58ac3e2 Remove check for f256mem from has256BitOperands as nothing depended on it and it isn't the only 256-bit memory type anyway. 
llvm-svn: 160946
 2012-07-30 04:53:00 +00:00
Craig Topper ac172e225d Remove trailing whitespace. 
llvm-svn: 160945
 2012-07-30 04:48:12 +00:00
Craig Topper c7690ac7ac Make l/q suffixes on AVX forms of scalar convert instructions consistent with their non-AVX forms. 
llvm-svn: 160775
 2012-07-26 07:48:28 +00:00
Richard Trieu 9208abd7c3 Move around some enum elements so that lastMRM corrects gets assigned 56, which 
is one more that MRM_DF which is 55.  Previously, it held value 45, the same
as MRM_D0.

llvm-svn: 160465
 2012-07-18 23:04:22 +00:00
Craig Topper 01deb5f2df Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. 
llvm-svn: 160420
 2012-07-18 04:11:12 +00:00
Craig Topper f7755df776 Update GATHER instructions to support 2 read-write operands. Patch from myself and Manman Ren. 
llvm-svn: 160110
 2012-07-12 06:52:41 +00:00
Manman Ren a09820414a X86: add GATHER intrinsics (AVX2) in LLVM 
Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256

Modified Disassembler to handle VSIB addressing mode.

llvm-svn: 159221
 2012-06-26 19:47:59 +00:00
Benjamin Kramer ef479ea854 Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. 
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.

llvm-svn: 157634
 2012-05-29 19:05:25 +00:00
Craig Topper 7629d63bc4 Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo. 
llvm-svn: 153935
 2012-04-03 05:20:24 +00:00
Kevin Enderby 014e1cde5f Fix the x86 disassembler to at least print the lock prefix if it is the first 
prefix.  Added a FIXME to remind us this still does not work when it is not the
first prefix.

llvm-svn: 152414
 2012-03-09 17:52:49 +00:00
Craig Topper 6491c8020e X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo. 
llvm-svn: 151510
 2012-02-27 01:54:29 +00:00
Craig Topper 66a3597a4a Add vmfunc instruction to X86 assembler and disassembler. 
llvm-svn: 150899
 2012-02-19 01:39:49 +00:00
Craig Topper ed7aa46366 Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. 
llvm-svn: 150873
 2012-02-18 08:19:49 +00:00
Craig Topper 2ba766ae84 Add disassembler support for VPERMIL2PD and VPERMIL2PS. 
llvm-svn: 147368
 2011-12-30 06:23:39 +00:00
Craig Topper 03a0beda88 Add FMA4 instructions to disassembler. 
llvm-svn: 147367
 2011-12-30 05:20:36 +00:00
Craig Topper 75ffc5fbb5 Remove some unnecessary filtering checks from X86 disassembler table build. 
llvm-svn: 144986
 2011-11-19 05:48:20 +00:00
Craig Topper f01f1b5cb9 More AVX2 instructions and their intrinsics. 
llvm-svn: 143895
 2011-11-06 23:04:08 +00:00
Craig Topper 980d59832a Add X86 RORX instruction 
llvm-svn: 142741
 2011-10-23 07:34:00 +00:00
Craig Topper 96fa597828 Add X86 PEXTR and PDEP instructions. 
llvm-svn: 142141
 2011-10-16 16:50:08 +00:00
Craig Topper aea148c366 Add X86 BZHI instruction as well as BMI2 feature detection. 
llvm-svn: 142122
 2011-10-16 07:55:05 +00:00
Craig Topper 0ae8d4d738 Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. 
llvm-svn: 142117
 2011-10-16 07:05:40 +00:00