3180f9f55f
Attempt to fix linking issues with CMake. Please review other CMake users,
...
especially on other platforms. Is there a better way to fix this.
llvm-svn: 109084
2010-07-22 06:27:45 +00:00
9a77382685
Custom lower the memory barrier instructions and add support
...
for lowering without sse2. Add a couple of new testcases.
Fixes a few libgomp tests and latent bugs. Remove a few todos.
llvm-svn: 109078
2010-07-22 02:48:34 +00:00
a4c435f1fa
80-columns.
...
llvm-svn: 109070
2010-07-22 00:26:08 +00:00
68a069a188
Make fast isel win64-aware w.r.t. call-clobbered regs
...
llvm-svn: 109069
2010-07-22 00:09:39 +00:00
e3acfd4d58
Add more 256-bit forms for a bunch of regular AVX instructions
...
Add 64-bit (GR64) versions of some instructions (which are not
described in their SSE forms, but are described in AVX)
llvm-svn: 109063
2010-07-21 23:53:50 +00:00
350b1a449f
Fixes win64. It was broken by a previous patch where I missed the !isWin64
...
and then forced every register to be a vr128 on win64.
llvm-svn: 109060
2010-07-21 23:19:57 +00:00
5c91a5e747
add some rough support for making mcinst lowering work without an
...
asmprinter or mangler around. This is option #B for killing off
X86InstrInfo::GetInstSizeInBytes. Option #A (killing
"needsexactsize") was sent for consideration to llvmdev.
llvm-svn: 109056
2010-07-21 23:03:35 +00:00
6238c1d102
Add missing AVX convert instructions. Those instructions are not described in their SSE forms (although they exist), but add the AVX forms anyway, so the assembler can benefit from it
...
llvm-svn: 109039
2010-07-21 21:37:59 +00:00
784e062b2a
Fix a couple issues with Win64 ABI
...
1) all registers were spilled as xmm, regardless of actual size
2) win64 abi doesn't do the varargs-size-in-%al thing
Still to look into:
xmm6-15 are marked as clobbered by call instructions on win64 even though they aren't.
llvm-svn: 109035
2010-07-21 20:49:52 +00:00
19b3830142
Avoid AVX instructions to be selected instead of its SSE form
...
llvm-svn: 109032
2010-07-21 20:38:42 +00:00
d27913e516
Pulling out previous patch, must've run the tests in
...
the wrong directory.
llvm-svn: 109005
2010-07-21 09:23:56 +00:00
b2d1067024
Lower MEMBARRIER on x86 and support processors without SSE2.
...
Fixes a pile of libgomp failures in the llvm-gcc testsuite due
to the libcall not existing.
llvm-svn: 109004
2010-07-21 09:05:23 +00:00
cdbec62510
Add AVX only vzeroall and vzeroupper instructions
...
llvm-svn: 109002
2010-07-21 08:56:24 +00:00
3499934da6
Add new AVX vpermilps, vpermilpd and vperm2f128 instructions
...
llvm-svn: 108984
2010-07-21 03:07:42 +00:00
3ceaf7a0a2
Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to support it
...
llvm-svn: 108983
2010-07-21 02:46:58 +00:00
e706501975
Add new AVX vextractf128 instructions
...
llvm-svn: 108964
2010-07-20 23:19:02 +00:00
41ff5d4d91
make asmprinter optional, even though passing in null will cause things to explode right now.
...
llvm-svn: 108955
2010-07-20 22:45:33 +00:00
b4dc58975b
continue pushing dependencies around.
...
llvm-svn: 108952
2010-07-20 22:35:40 +00:00
2366d95af9
reduce X86MCInstLower dependencies on asmprinter.
...
llvm-svn: 108950
2010-07-20 22:30:53 +00:00
7fbdd7c852
pass around MF, not MMI.
...
llvm-svn: 108949
2010-07-20 22:26:07 +00:00
d3f3a89425
cleanups.
...
llvm-svn: 108947
2010-07-20 22:23:57 +00:00
5ca516b87c
move two asmprinter methods into the asmprinter .cpp file.
...
llvm-svn: 108945
2010-07-20 22:18:19 +00:00
3b505848fd
Add new AVX instruction vinsertf128
...
llvm-svn: 108892
2010-07-20 19:44:51 +00:00
4adaccf0bf
Constify some arguments.
...
llvm-svn: 108812
2010-07-20 06:52:21 +00:00
14c5fd437c
Add AVX vbroadcast new instruction
...
llvm-svn: 108788
2010-07-20 00:11:13 +00:00
0aff8033c6
Update CMake files.
...
llvm-svn: 108787
2010-07-20 00:08:13 +00:00
64fffadad3
fix a layering problem by moving the x86 implementation
...
of AsmPrinter and InstLowering into libx86 and out of the
asmprinter subdirectory. Now X86/AsmPrinter just depends on
MC stuff, not all of codegen and LLVM IR.
llvm-svn: 108782
2010-07-19 23:41:57 +00:00
9de0ca73d4
Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!
...
llvm-svn: 108769
2010-07-19 23:32:44 +00:00
9db7d0addd
X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same
...
instruction, we only want to allow the one for the current subtarget.
- This also fixes suffix matching for jmp instructions, because it eliminates
the ambiguity between 'jmpl' and 'jmpq'.
llvm-svn: 108746
2010-07-19 20:44:16 +00:00
9aefb8ee4c
X86-64: Mark WINCALL and more tail call instructions as code gen only.
...
llvm-svn: 108685
2010-07-19 07:21:07 +00:00
2e9f58517d
X86: Mark some tail call pseduo instruction as code gen only.
...
llvm-svn: 108684
2010-07-19 07:21:04 +00:00
1cd02510d3
X86: Mark In32/64BitMode on LEAVE[64] and SYSEXIT[64].
...
llvm-svn: 108683
2010-07-19 07:21:01 +00:00
b82cd9319b
MC/X86: We now match instructions like "incl %eax" correctly for the arch we are
...
assembling; remove crufty custom cleanup code.
llvm-svn: 108681
2010-07-19 06:14:54 +00:00
150d948d3a
X86: Mark MOV.*_{TC,NOREX} instruction as code gen only, they aren't real.
...
llvm-svn: 108680
2010-07-19 06:14:49 +00:00
961543377d
X86: MOV8o8a, MOV8ao8, etc. are only valid in 32-bit mode.
...
llvm-svn: 108679
2010-07-19 06:14:44 +00:00
eefe8616be
TblGen/AsmMatcher: Add support for honoring instruction Requires<[]> attributes as part of the matcher.
...
- Currently includes a hack to limit ourselves to "In32BitMode" and "In64BitMode", because we don't have the other infrastructure to properly deal with setting SSE, etc. features on X86.
llvm-svn: 108677
2010-07-19 05:44:09 +00:00
419197cc4d
Target: Give the TargetAsmParser access to the TargetMachine.
...
- Unfortunate, but necessary for now to handle subtarget instruction matching. Eventually we should factor out the lower level target machine information so we don't need to do this.
llvm-svn: 108664
2010-07-19 00:33:49 +00:00
5218343970
the stackifier is global!
...
llvm-svn: 108626
2010-07-17 17:42:04 +00:00
8f440bb9b0
doxygenify some comments.
...
llvm-svn: 108625
2010-07-17 17:40:51 +00:00
83f250f005
Remove unnecessary check that was subsumed into canRealignStack.
...
llvm-svn: 108588
2010-07-17 00:33:04 +00:00
c0be37287c
Make comment a bit more clear as well as return statement since
...
needsStackRealignment is currently checking the can conditions as well.
llvm-svn: 108581
2010-07-17 00:25:41 +00:00
8289f78569
Remove the isMoveInstr() hook.
...
llvm-svn: 108567
2010-07-16 22:35:46 +00:00
2c130b8ead
Use MI.isCopy.
...
llvm-svn: 108565
2010-07-16 22:35:34 +00:00
499f797cdd
Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and
...
thus is a much more meaningful name.
llvm-svn: 108563
2010-07-16 22:20:36 +00:00
8d51149102
Keep valgrind quiet.
...
The isLive() method can read uninitialized memory, but it still gives correct
results.
llvm-svn: 108561
2010-07-16 22:00:33 +00:00
da3e05db70
Accept registers with P modifier. PR 5314.
...
llvm-svn: 108545
2010-07-16 18:35:46 +00:00
c30b4ddc58
Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKill
...
pass that inserted it.
It is no longer necessary to limit the live ranges of FP registers to a single
basic block.
llvm-svn: 108536
2010-07-16 17:41:44 +00:00
f0af236874
Search for a free FP register instead of just assuming FP7 is not in use.
...
llvm-svn: 108535
2010-07-16 17:41:40 +00:00
0e5fb020a0
Allow x87 FP registers to be alive globally in a function.
...
FP_REG_KILL instructions are still inserted, but can be disabled by passing
-live-x87 to llc. The X87FPRegKillInserterPass is going to be removed shortly.
CFG edges are partioned into bundles where the x87 stack must be allocated
identically. Code is insertad at the end of each basic block that shuffles the
live FP registers to match the outgoing bundles expectations.
This fix is in preparation for some upcoming register allocator improvements
that may extend the live range of registers beyond a basic block, similar to
LICM. It also provides a nice runtime speedup if you are building with
-mfpmath=387.
llvm-svn: 108529
2010-07-16 16:38:12 +00:00
55f0c6b9fc
Split -enable-finite-only-fp-math to two options:
...
-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.
llvm-svn: 108465
2010-07-15 22:07:12 +00:00
620693806a
fix the encoding of MMX_MOVFR642Qrr, it starts with 0xF2 not 0xF3,
...
this fixes rdar://8192860. Unfortunately it can only be triggered
with llc because llvm-mc matches another (correctly encoded) version
of this, so no testcase.
llvm-svn: 108454
2010-07-15 20:13:34 +00:00
8b1bb8cfbd
Last COPY conversion.
...
llvm-svn: 108387
2010-07-14 23:58:21 +00:00
9b449d5a92
Use TargetOpcode::COPY instead of X86-native register copy instructions when
...
lowering atomics. This will allow those copies to still be coalesced after
TII::isMoveInstr is removed.
llvm-svn: 108385
2010-07-14 23:50:27 +00:00
769aedd523
fix indentation
...
llvm-svn: 108368
2010-07-14 23:04:59 +00:00
92d8998348
Don't pass StringRef by reference.
...
llvm-svn: 108366
2010-07-14 22:38:02 +00:00
254858031a
Merge lib/Target/X86/X86COFF.h into include/llvm/Support/COFF.h,
...
patch by Michael Spencer!
llvm-svn: 108342
2010-07-14 18:14:33 +00:00
a8e8874552
Fix for PR7193 was overly conservative. The only case where sibcall callee
...
address cannot be allocated a register is in 32-bit mode where the first
three arguments are marked inreg. In that case EAX, EDX, and ECX will be
used for argument passing.
This fixes PR7610.
llvm-svn: 108327
2010-07-14 06:44:01 +00:00
1f471435f8
Don't propagate debug locations to instructions for materializing
...
constants, since they may not be emited near the other instructions
which get the same line, and this confuses debug info.
llvm-svn: 108302
2010-07-14 01:07:44 +00:00
6c6c14a55c
Add AVX 256-bit compare instructions and a bunch of testcases
...
llvm-svn: 108286
2010-07-13 22:06:38 +00:00
fd8bfcd6e1
AVX 256-bit conversion instructions
...
Add the x86 VEX_L form to handle special cases where VEX_L must be set.
llvm-svn: 108274
2010-07-13 21:07:28 +00:00
76a6b663a3
Added a check that pusha cannot be encoded in 64-bit mode.
...
llvm-svn: 108265
2010-07-13 20:05:41 +00:00
55595fb291
my work on adding segment registers to LEA missed the
...
disassembler. Remove some code from the disassembler to
compensate, unbreaking disassembly of lea's.
llvm-svn: 108226
2010-07-13 04:23:55 +00:00
dff283e146
Add AVX 256-bit packed logical forms
...
llvm-svn: 108224
2010-07-13 02:38:35 +00:00
36b32aeaa5
Add AVX 256-bit unop arithmetic instructions
...
llvm-svn: 108223
2010-07-13 01:53:31 +00:00
77a3c4462f
Since AVX is a superset of all SSE versions, only use HasAVX for AVX instructions
...
llvm-svn: 108222
2010-07-13 00:38:47 +00:00
03264efe30
Move some SIMD fragment code into X86InstrFragmentsSIMD so that the
...
utility classes can be used from multiple files. This will aid
transitioning to a new refactored x86 SIMD specification.
llvm-svn: 108213
2010-07-12 23:41:28 +00:00
8e67a0482e
Add AVX 256 binary arithmetic instructions
...
llvm-svn: 108207
2010-07-12 23:04:15 +00:00
91806311c9
More refactoring of basic SSE arith instructions. Open room for 256-bit instructions
...
llvm-svn: 108204
2010-07-12 22:41:32 +00:00
51e6d9bbf6
Apply the SSE dependence idiom for SSE unary operations to
...
SD instructions too, in addition to SS instructions. And
add a comment about it.
llvm-svn: 108191
2010-07-12 20:46:04 +00:00
f9bcaad76d
Add AVX 256-bit MOVMSK forms
...
llvm-svn: 108184
2010-07-12 20:06:32 +00:00
425b35681f
Check begin!=end, rather than !begin.
...
llvm-svn: 108167
2010-07-12 18:12:35 +00:00
68d7424a65
Don't fast-isel an x87 comparison opcode, as fast-isel doesn't
...
support branching on x87 comparisons yet. This fixes PR7624.
llvm-svn: 108149
2010-07-12 15:46:30 +00:00
6635f9838e
Convert getLoadStoreRegOpcode to use a switch.
...
llvm-svn: 108123
2010-07-12 03:43:04 +00:00
de7201545e
A basic block that only uses RFP registers still needs the FP_REG_KILL marker.
...
This fixes PR7375.
llvm-svn: 108120
2010-07-12 02:12:47 +00:00
e35d70fafa
Convert the last getPhysicalRegisterRegClass in VirtRegRewriter.cpp to
...
getMinimalPhysRegClass. It was used to produce spills, and it is better to
use the most specific class if possible.
Update getLoadStoreRegOpcode to handle GR32_AD.
llvm-svn: 108115
2010-07-12 00:52:33 +00:00
f6c7d7fb3f
Use target independent COPY instructions for the fake fextend and fround
...
operations in x87 code.
llvm-svn: 108098
2010-07-11 18:19:39 +00:00
98ee37d878
Remove obsolete README_SSE note.
...
We are generating movaps for all XMM register copies, including scalar
floating point values. This is known to be at least as good as movss and movsd
for all known architectures up to and including Nehalem because it avoids a
partial register stall.
The SSEDomainFix pass will switch movaps to movdqa when appropriate (i.e., when
operands come from the integer unit). We don't now that switching movaps to
movapd has any benefit.
The same applies to andps -> pand.
llvm-svn: 108096
2010-07-11 17:13:42 +00:00
4806848799
Avoid SSE instructions in FastIsel when it is not available.
...
llvm-svn: 108091
2010-07-11 16:22:13 +00:00
e46f3eb0c4
X86InstrInfo::copyRegToReg is dead. Long live copyPhysReg!
...
llvm-svn: 108076
2010-07-11 05:44:30 +00:00
8969657f0c
Use COPY in X86FastISel::X86SelectRet.
...
Don't try a cross-class copy. That is very unlikely anywy since return value
registers are usually register class friendly. (%EAX, %XMM0, etc).
llvm-svn: 108074
2010-07-11 05:17:02 +00:00
3bb1267431
Use COPY in FastISel everywhere it is safe and trivial.
...
The remaining copyRegToReg calls actually check the return value (shock!), so we
cannot trivially replace them with COPY instructions.
llvm-svn: 108069
2010-07-11 03:31:00 +00:00
de457896b6
Don't emit st(0)/st(1) copies as FpMOV instructions. Use FpSET_ST? instead.
...
Based on a patch by Rafael Espíndola.
Attempt to make the FpSET_ST1 hack more robust, but we are still relying on
FpSET_ST0 preceeding it. This is only for supporting really weird x87 inline
asm.
We support:
FpSET_ST0
INLINEASM
FpSET_ST0
FpSET_ST1
INLINEASM
with and without kills on the arguments. We don't support:
FpSET_ST1
FpSET_ST0
INLINEASM
nor
FpSET_ST1
INLINEASM
Just Don't Do It!
llvm-svn: 108047
2010-07-10 17:42:34 +00:00
d7b5ce3312
Reapply bottom-up fast-isel, with several fixes for x86-32:
...
- Check getBytesToPopOnReturn().
- Eschew ST0 and ST1 for return values.
- Fix the PIC base register initialization so that it doesn't ever
fail to end up the top of the entry block.
llvm-svn: 108039
2010-07-10 09:00:22 +00:00
be8d9b0bb8
An x86 function returns a floating point value in st(0), and we must make sure
...
it is popped, even if it is ununsed. A CopyFromReg node is too weak to represent
the required sideeffect, so insert an FpGET_ST0 instruction directly instead.
This will matter when CopyFromReg gets lowered to a generic COPY instruction.
llvm-svn: 108037
2010-07-10 04:04:25 +00:00
5e6c2155a3
Declare YMM subregisters in the right way! Thanks Jakob
...
llvm-svn: 108022
2010-07-09 21:46:19 +00:00
2419606bfb
Add AVX 256-bit packed MOVNT variants
...
llvm-svn: 108021
2010-07-09 21:42:42 +00:00
e2614a9979
Remember the *_TC opcodes for load/store
...
llvm-svn: 108020
2010-07-09 21:27:55 +00:00
6bc772eec7
Add AVX 256-bit unpack and interleave
...
llvm-svn: 108017
2010-07-09 21:20:35 +00:00
7a7b55eb67
Automatically fold COPY instructions into stack load/store.
...
llvm-svn: 108012
2010-07-09 20:43:13 +00:00
51702ec46b
Fix a few tests
...
llvm-svn: 108011
2010-07-09 20:43:09 +00:00
792e906bef
Start the support for AVX instructions with 256-bit %ymm registers. A couple of
...
notes:
- The instructions are being added with dummy placeholder patterns using some 256
specifiers, this is not meant to work now, but since there are some multiclasses
generic enough to accept them, when we go for codegen, the stuff will be already
there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
file.
llvm-svn: 107996
2010-07-09 18:27:43 +00:00
6586e9b203
--- Reverse-merging r107947 into '.':
...
U utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U test/CodeGen/X86/fast-isel.ll
U test/CodeGen/X86/fast-isel-loads.ll
U include/llvm/Target/TargetLowering.h
U include/llvm/Support/PassNameParser.h
U include/llvm/CodeGen/FunctionLoweringInfo.h
U include/llvm/CodeGen/CallingConvLower.h
U include/llvm/CodeGen/FastISel.h
U include/llvm/CodeGen/SelectionDAGISel.h
U lib/CodeGen/LLVMTargetMachine.cpp
U lib/CodeGen/CallingConvLower.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U lib/CodeGen/SelectionDAG/FastISel.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U lib/CodeGen/SelectionDAG/TargetLowering.cpp
U lib/Target/XCore/XCoreISelLowering.cpp
U lib/Target/XCore/XCoreISelLowering.h
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86ISelLowering.h
llvm-svn: 107987
2010-07-09 16:37:18 +00:00
992d25da71
Merge VEX enums with other x86 enum forms. Also fix all checks of which VEX
...
fields to use.
llvm-svn: 107952
2010-07-09 01:56:45 +00:00
0a7d155d67
Fix the memoperand offsets in code generated for va_start.
...
llvm-svn: 107948
2010-07-09 01:06:48 +00:00
88c185617c
have the mc lowering process handle a few tail call forms, lowering them to
...
jumps where possible and turning the TAILCALL marker in the instruction
asm string into a proper comment.
This eliminates a FIXME and is on the path to finishing:
rdar://7639610 - eliminate encoding and asm info for TAILJMPd TAILJMPr TAILJMPn, etc.
However, I can't eliminate the encodings for these instructions because the JIT
still exists and has its own copy of the encoder, sigh.
llvm-svn: 107946
2010-07-09 00:49:41 +00:00
0b5aa1cdd3
Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting
...
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.
llvm-svn: 107943
2010-07-09 00:39:23 +00:00
e6cc0d33bb
Factor out x86 segment override prefix encoding, and also use it for VEX
...
llvm-svn: 107942
2010-07-09 00:38:14 +00:00
061d70ad2c
reject pseudo instructions early in the encoder.
...
llvm-svn: 107939
2010-07-09 00:17:50 +00:00
b652c1a145
Remove trailing whitespaces from file
...
llvm-svn: 107937
2010-07-09 00:07:19 +00:00
f469307c77
Change LEA to have 5 operands for its memory operand, just
...
like all other instructions, even though a segment is not
allowed. This resolves a bunch of gross hacks in the
encoder and makes LEA more consistent with the rest of the
instruction set.
No functionality change.
llvm-svn: 107934
2010-07-08 23:46:44 +00:00
ec536276f0
add some long-overdue enums to refer to the parts of the 5-operand
...
X86 memory operand.
llvm-svn: 107925
2010-07-08 22:41:28 +00:00
ec58a43d81
Remember the VR64 register class
...
llvm-svn: 107920
2010-07-08 22:30:35 +00:00
9f034c1e5d
Rework segment prefix emission code to handle segments
...
in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax
This fixes rdar://8127102. I have several cleanup patches coming
next.
llvm-svn: 107917
2010-07-08 22:28:12 +00:00
1dd82c7dc2
introduce a new X86II::getMemoryOperandNo method, which
...
returns the start of the memory operand for an instruction.
Introduce a new "X86AddrSegment" enum to reduce # magic numbers
referring to X86 memory operand layout.
llvm-svn: 107916
2010-07-08 22:27:06 +00:00
63a622b768
Teach the x86 floating point stackifier to handle COPY instructions.
...
This pass runs before COPY instructions are passed to copyPhysReg, so we simply
translate COPY to the proper pseudo instruction. Note that copyPhysReg does not
handle floating point stack copies.
Once COPY is used everywhere, this can be cleaned up a bit, and most of the
pseudo instructions can be removed.
llvm-svn: 107899
2010-07-08 19:46:30 +00:00
930f8082c3
Implement X86InstrInfo::copyPhysReg
...
llvm-svn: 107898
2010-07-08 19:46:25 +00:00
00264624a9
Convert EXTRACT_SUBREG to COPY when emitting machine instrs.
...
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.
Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.
llvm-svn: 107879
2010-07-08 16:40:22 +00:00
a1e883dcf6
Remove references to INSERT_SUBREG after de-SSA.
...
Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of
INSERT_SUBREG.
llvm-svn: 107878
2010-07-08 16:40:15 +00:00
e796253217
A slight reworking of the custom patterns for x86-64 tpoff codegen and
...
correct the testcase for valid assembly.
Needs more tests.
llvm-svn: 107860
2010-07-08 07:36:46 +00:00
e75704369d
Revert 107840 107839 107813 107804 107800 107797 107791.
...
Debug info intrinsics win for now.
llvm-svn: 107850
2010-07-08 01:00:56 +00:00
6213ab789f
fix copies to/from GR8_ABCD_H even more
...
llvm-svn: 107832
2010-07-07 23:04:56 +00:00
05ea2a4791
finish up support for callw: PR7195
...
llvm-svn: 107826
2010-07-07 22:35:13 +00:00
ac5881295c
Implement the major chunk of PR7195: support for 'callw'
...
in the integrated assembler. Still some discussion to be
done.
llvm-svn: 107825
2010-07-07 22:27:31 +00:00
6c61451011
Add more assembly opcodes for SSE compare instructions
...
llvm-svn: 107823
2010-07-07 22:24:03 +00:00
1c349f18f8
Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake.
...
llvm-svn: 107820
2010-07-07 22:15:37 +00:00
32a600b494
Print undefined/unknown debug value as "undef".
...
llvm-svn: 107818
2010-07-07 21:52:21 +00:00
ddaf0099a5
Allow copies between GR8_ABCD_L and GR8_ABCD_H.
...
This fixes PR7540.
llvm-svn: 107809
2010-07-07 20:33:27 +00:00
e7ccc51cc1
Implement bottom-up fast-isel. This has the advantage of not requiring
...
a separate DCE pass over MachineInstrs.
llvm-svn: 107804
2010-07-07 19:20:32 +00:00
2d4d01d0de
Add X86FastISel support for return statements. This entails refactoring
...
a bunch of stuff, to allow the target-independent calling convention
logic to be employed.
llvm-svn: 107800
2010-07-07 18:32:53 +00:00
fd8060335b
Add AVX AES instructions
...
llvm-svn: 107798
2010-07-07 18:24:20 +00:00
ffe64b1ee5
Give FunctionLoweringInfo an MBB member, avoiding the need to pass it
...
around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.
llvm-svn: 107791
2010-07-07 16:47:08 +00:00
87fb4e8fcd
Simplify FastISel's constructor by giving it a FunctionLoweringInfo
...
instance, rather than pointers to all of FunctionLoweringInfo's
members.
This eliminates an NDEBUG ABI sensitivity.
llvm-svn: 107789
2010-07-07 16:29:44 +00:00
fe7532a308
Split the SDValue out of OutputArg so that SelectionDAG-independent
...
code can do calling-convention queries. This obviates OutputArgReg.
llvm-svn: 107786
2010-07-07 15:54:55 +00:00
6d122aef97
Add AVX SSE4.2 instructions
...
llvm-svn: 107752
2010-07-07 03:39:29 +00:00
3df55b2d6f
Use only one multiclass to pinsrq instructions
...
llvm-svn: 107750
2010-07-07 01:43:01 +00:00
fd6c808154
Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes
...
llvm-svn: 107749
2010-07-07 01:33:38 +00:00
8f5472a8e8
Add AVX SSE4.1 insertps, ptest and movntdqa instructions
...
llvm-svn: 107747
2010-07-07 01:14:56 +00:00
6430c7350d
Add AVX SSE4.1 extractps and pinsr instructions
...
llvm-svn: 107746
2010-07-07 01:01:13 +00:00
f3116ebe96
Add AVX SSE4.1 Extract Integer instructions
...
llvm-svn: 107740
2010-07-07 00:07:24 +00:00
ce65663330
Accept RIP-relative symbols with 'i' constraint, and
...
print the (%rip) only if the 'a' modifier is present.
PR 7528.
llvm-svn: 107727
2010-07-06 23:27:00 +00:00
1f9ad516c6
Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions
...
llvm-svn: 107723
2010-07-06 23:15:17 +00:00
35702d27c4
Add part of AVX SSE4.1 packed move with sign/zero extend instructions
...
llvm-svn: 107720
2010-07-06 23:01:41 +00:00
13f0260e76
Fix comment from previous patch
...
llvm-svn: 107717
2010-07-06 22:38:32 +00:00
e2bd058d32
Add AVX vblendvpd, vblendvps and vpblendvb instructions
...
Update VEX encoding to support those new instructions
llvm-svn: 107715
2010-07-06 22:36:24 +00:00
ee0cb70381
CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.
...
SelectBasicBlock doesn't needs its BasicBlock argument.
llvm-svn: 107712
2010-07-06 22:19:37 +00:00
a3ca21b228
Propagate debug loc.
...
llvm-svn: 107710
2010-07-06 22:08:15 +00:00
3439629239
Reapply r107655 with fixes; insert the pseudo instruction into
...
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
llvm-svn: 107691
2010-07-06 20:24:04 +00:00
23a7593534
Fix PR7545 crash.
...
llvm-svn: 107678
2010-07-06 18:18:32 +00:00
f4f04107ef
Revert r107655.
...
llvm-svn: 107668
2010-07-06 15:49:48 +00:00
12205645a6
Fix a bunch of custom-inserter functions to handle the case where
...
the pseudo instruction is not at the end of the block.
llvm-svn: 107655
2010-07-06 15:18:19 +00:00
2ad0c779c3
Fix up -fstack-protector on linux to use the segment
...
registers. Split out testcases per architecture and os
now.
Patch from Nelson Elhage.
llvm-svn: 107640
2010-07-06 05:18:56 +00:00
d429846eca
Have the X86 backend use Triple instead of a string and some enums.
...
llvm-svn: 107625
2010-07-05 19:26:33 +00:00
c4a7073db3
more tidying.
...
llvm-svn: 107615
2010-07-05 05:53:14 +00:00
7b909ac785
some notes about suboptimal insertps's
...
llvm-svn: 107613
2010-07-05 05:48:41 +00:00
6d60a14251
rip out even more sporadic v2f32 support.
...
llvm-svn: 107610
2010-07-05 04:38:33 +00:00
feb2467bf4
rip out the various v2f32 "mmx" handling logic, now that
...
v2f32 is illegal on x86.
llvm-svn: 107609
2010-07-05 04:36:27 +00:00
45cc4d74a3
Just rip v2f32 support completely out of the X86 backend. In
...
the example in the testcase, we now generate:
_test1: ## @test1
movss 4(%esp), %xmm0
addss 8(%esp), %xmm0
movl 12(%esp), %eax
movss %xmm0, (%eax)
ret
instead of:
_test1: ## @test1
subl $20, %esp
movl 24(%esp), %eax
movq %mm0, (%esp)
movq %mm0, 8(%esp)
movss (%esp), %xmm0
addss 12(%esp), %xmm0
movss %xmm0, (%eax)
addl $20, %esp
ret
v2f32 support did not work reliably because most of the X86
backend didn't know it was legal. It was apparently only added
to support returning source-level v2f32 values in MMX registers
in x86-32 mode. If ABI compatibility is important on this
GCC-extended-vector type for some reason, then the frontend
should generate IR that returns v2i32 instead of v2f32. However,
we generally don't try very hard to be abi compatible on gcc
extended vectors.
llvm-svn: 107601
2010-07-04 23:07:25 +00:00
681b926d54
fix PR7518 - terrible codegen of <2 x float>, by only marking
...
v2f32 as legal in 32-bit mode. It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.
llvm-svn: 107600
2010-07-04 22:57:10 +00:00
cb948d3329
indentation
...
llvm-svn: 107599
2010-07-04 22:56:10 +00:00
199cacf179
Revert r107583. I no longer think that this is the way to solve the problem.
...
llvm-svn: 107585
2010-07-04 09:16:57 +00:00
701aa053b9
Mark sse_load_f32 and sse_load_f64 as having memory operands
...
(SDNPMemOperand). This way when they're morphed the memory operands will be
copied as well.
llvm-svn: 107583
2010-07-04 08:59:55 +00:00
ca99012ac0
Add AVX SSE4.1 blend, mpsadbw and vdp
...
llvm-svn: 107560
2010-07-03 01:37:03 +00:00
bc75502f09
Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions
...
llvm-svn: 107558
2010-07-03 01:15:47 +00:00
fc9cdc4d61
Add AVX SSE4.1 Horizontal Minimum and Position instruction
...
llvm-svn: 107552
2010-07-03 00:49:21 +00:00
0664a67fe1
Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.
...
llvm-svn: 107550
2010-07-03 00:40:23 +00:00
621c85b038
Add AVX SSE4.1 round instructions
...
llvm-svn: 107549
2010-07-03 00:37:44 +00:00
5b59c1bf1f
Simple refactoring of SSE4.1 instructions, making room for the AVX forms
...
llvm-svn: 107540
2010-07-02 23:27:59 +00:00
c7111fd355
- Add support for the rest of AVX SSE3 instructions
...
- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode
llvm-svn: 107523
2010-07-02 22:06:54 +00:00
0ce84486c3
- Two-address pass should not assume unfolding is always successful.
...
- X86 unfolding should check if the instructions being unfolded has memoperands.
If there is no memoperands, then it must assume conservative alignment. If this
would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand
etc. should not unfold the instruction.
llvm-svn: 107509
2010-07-02 20:36:18 +00:00
4ca8ddaceb
Shrink down SSE3 code by more multiclass refactoring
...
llvm-svn: 107448
2010-07-01 23:10:49 +00:00
0a17241a0d
Shrink down SSE3 code by some multiclass refactoring - 1st part
...
llvm-svn: 107438
2010-07-01 22:33:18 +00:00
5e88700f28
Move SSE3 Move patterns to a more appropriate section
...
Add AVX SSE3 packed horizontal and & sub instructions
llvm-svn: 107405
2010-07-01 17:35:02 +00:00
886ee33a38
Add AVX SSE3 packed addsub instructions
...
llvm-svn: 107404
2010-07-01 17:08:18 +00:00
722f5fc567
Enable on-demand fast-isel.
...
llvm-svn: 107377
2010-07-01 02:58:57 +00:00
207624edb0
Fix X86FastISel's add folding to actually work, and not fall back
...
to SelectionDAG.
llvm-svn: 107376
2010-07-01 02:58:21 +00:00
a7a0c83563
Add AVX SSE3 replicate and convert instructions
...
llvm-svn: 107375
2010-07-01 02:33:39 +00:00
7937d5606d
Teach X86FastISel to fold constant offsets and scaled indices in
...
the same address.
llvm-svn: 107373
2010-07-01 02:27:15 +00:00
05166740eb
- Add AVX SSE2 Move doubleword and quadword instructions.
...
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
in the .td file now have a AVX encoded form already working.
llvm-svn: 107365
2010-07-01 01:20:06 +00:00
d0eacf715f
Move MOVD/MODQ code around, creating sections for each of them
...
llvm-svn: 107308
2010-06-30 18:49:10 +00:00
cbcebe2950
Add AVX SSE2 mask creation and conditional store instructions
...
llvm-svn: 107306
2010-06-30 18:38:10 +00:00
5c768e4915
Fix a bug introduced in r107211 where instructions with memory operands are declared as commutable
...
llvm-svn: 107300
2010-06-30 18:06:01 +00:00
d079c91683
Add AVX SSE2 packed integer extract/insert instructions
...
llvm-svn: 107293
2010-06-30 17:03:03 +00:00
12ca3d9fac
use ArgOperand API
...
llvm-svn: 107280
2010-06-30 13:03:37 +00:00
e82689fea2
Add AVX SSE2 integer unpack instructions
...
llvm-svn: 107246
2010-06-30 04:06:39 +00:00
ec0115c9b7
Add AVX SSE2 packed integer shuffle instructions
...
llvm-svn: 107245
2010-06-30 03:47:56 +00:00
51ceead19c
Small refactoring of SSE2 packed integer shuffle instructions
...
llvm-svn: 107243
2010-06-30 03:29:36 +00:00
be792feb8b
Add AVX SSE2 pack with saturation integer instructions
...
llvm-svn: 107241
2010-06-30 02:30:25 +00:00
2686ea4555
Add AVX SSE2 integer packed compare instructions
...
llvm-svn: 107240
2010-06-30 02:21:09 +00:00
2e2caefff9
- Add AVX form of all SSE2 logical instructions
...
- Add VEX encoding bits to x86 MRM0r-MRM7r
llvm-svn: 107238
2010-06-30 01:58:37 +00:00
3f71ddfaad
Add *several* AVX integer packed binop instructions
...
llvm-svn: 107225
2010-06-29 23:47:49 +00:00
7fee95a38e
Move SSE2 Packed Integer instructions around, and create specific sections for each of them
...
llvm-svn: 107211
2010-06-29 22:12:16 +00:00
ba21eb8054
Add AVX Move Aligned/Unaligned packed integers
...
llvm-svn: 107206
2010-06-29 21:25:12 +00:00
30689a3a7f
Add AVX ld/st XCSR register.
...
Add VEX encoding bits for MRMXm x86 form
llvm-svn: 107204
2010-06-29 20:35:48 +00:00
a4575f5b31
Add AVX non-temporal stores
...
llvm-svn: 107178
2010-06-29 18:22:01 +00:00
049f4ffab1
Move non-temporal movs to their own section
...
llvm-svn: 107168
2010-06-29 17:42:37 +00:00
21a9433e9e
Add sqrt, rsqrt and rcp AVX instructions
...
llvm-svn: 107166
2010-06-29 17:26:30 +00:00
67bfa9d109
Remove pointless and unused variables.
...
llvm-svn: 107130
2010-06-29 12:48:49 +00:00
de736a6494
Refactoring of arithmetic instruction classes with unary operator
...
llvm-svn: 107116
2010-06-29 01:33:09 +00:00
d6a091a4d4
Described the missing AVX forms of SSE2 convert instructions
...
llvm-svn: 107108
2010-06-29 00:36:02 +00:00
0a5bb081cc
Reduce indentation via early exit. NFC.
...
llvm-svn: 107067
2010-06-28 21:08:32 +00:00
83205af3fa
use ArgOperand API
...
llvm-svn: 106944
2010-06-26 11:51:52 +00:00
d7d0d4e882
When creating X86 MUL8 and DIV8 instructions, make sure we don't produce
...
CopyFromReg nodes for aliasing registers (AX and AL). This confuses the fast
register allocator.
Instead of CopyFromReg(AL), use ExtractSubReg(CopyFromReg(AX), sub_8bit).
This fixes PR7312.
llvm-svn: 106934
2010-06-26 00:39:23 +00:00
74d716b9cd
Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions
...
llvm-svn: 106917
2010-06-25 23:47:23 +00:00
83651094ad
Reapply r106896:
...
Add several AVX MOV flavors
Support VEX encoding for MRMDestReg
llvm-svn: 106912
2010-06-25 23:33:42 +00:00
4530fed87e
revert this now, it's using avx instead of sse :)
...
llvm-svn: 106906
2010-06-25 23:04:29 +00:00
a34d9b6d84
Add several AVX MOV flavors
...
Support VEX encoding for MRMDestReg
llvm-svn: 106896
2010-06-25 22:27:51 +00:00
ce97d55ad9
The hasMemory argument is irrelevant to how the argument
...
for an "i" constraint should get lowered; PR 6309. While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.
llvm-svn: 106893
2010-06-25 21:55:36 +00:00
8de1fe3ccf
pcmpeqd and friends are Commutable.
...
llvm-svn: 106886
2010-06-25 21:05:35 +00:00
e41e40f689
- Reapply r106066 now that the bzip2 build regression has been fixed.
...
- 2010-06-25-CoalescerSubRegDefDead.ll is the testcase for r106878.
llvm-svn: 106880
2010-06-25 20:48:10 +00:00
553fafc6ce
Move the last piece of SSE2 convert instructions to the Convert Instructions section
...
llvm-svn: 106877
2010-06-25 20:29:27 +00:00
Chandler Carruth