Commit Graph

123359 Commits

Author SHA1 Message Date
Matt Arsenault 8dbeb9256c TTI: Improve default costs for addrspacecast
For some reason multiple places need to do this, and the variant the
loop unroller and inliner use was not handling it.

Also, introduce a new wrapper to be slightly more precise, since on
AMDGPU some addrspacecasts are free, but not no-ops.

llvm-svn: 362436
2019-06-03 18:41:34 +00:00
Nikita Popov c061b99c5b [ConstantRange] Add sdiv() support
The implementation is conceptually simple: We separate the LHS and
RHS into positive and negative components and then also compute the
positive and negative components of the result, taking into account
that e.g. only pos/pos and neg/neg will give a positive result.

However, there's one significant complication: SignedMin / -1 is UB
for sdiv, and we can't just ignore it, because the APInt result of
SignedMin would break the sign segregation. Instead we drop SignedMin
or -1 from the corresponding ranges, taking into account some edge
cases with wrapped ranges.

Because of the sign segregation, the implementation ends up being
nearly fully precise even for wrapped ranges (the remaining
imprecision is due to ranges that are both signed and unsigned
wrapping and are divided by a trivial divisor like 1). This means
that the testing cannot just check the signed envelope as we
usually do. Instead we collect all possible results in a bitvector
and construct a better sign wrapped range (than the full envelope).

Differential Revision: https://reviews.llvm.org/D61238

llvm-svn: 362430
2019-06-03 18:19:54 +00:00
Andrew Kaylor 4172dbab5d Fix a crash when the default of a switch is removed
This patch fixes a problem that occurs in LowerSwitch when a switch statement has a PHI node as its condition, and the PHI node only has two incoming blocks, and one of those incoming blocks is through an unreachable default in the switch statement. When this condition occurs, LowerSwitch holds a pointer to the condition value, but removes the switch block as a predecessor of the PHI block, causing the PHI node to be replaced. LowerSwitch then tries to use its stale pointer to the original condition value, causing a crash.

Differential Revision: https://reviews.llvm.org/D62560

llvm-svn: 362427
2019-06-03 17:54:15 +00:00
Dmitri Gribenko 26c43d0ef8 Include what you use in Lanai.h
Other files were not relying on these transitive includes, so I'm
submitting this change separately.

llvm-svn: 362423
2019-06-03 17:02:15 +00:00
Dmitri Gribenko b8aeaf882e Include what you use in LanaiAsmPrinter.cpp
llvm-svn: 362422
2019-06-03 17:02:07 +00:00
Dmitri Gribenko dc136847e3 Include what you use in LanaiMemAluCombiner.cpp
llvm-svn: 362421
2019-06-03 17:02:02 +00:00
Dmitri Gribenko f4d22bd0b4 Include what you use in LanaiISelDAGToDAG.cpp
llvm-svn: 362420
2019-06-03 17:01:57 +00:00
Dmitri Gribenko 179154f6b9 Include what you use in LanaiFrameLowering.{cpp,h}
llvm-svn: 362419
2019-06-03 17:01:52 +00:00
Dmitri Gribenko 8e317e29da Include what you use in LanaiRegisterInfo.cpp
llvm-svn: 362416
2019-06-03 16:31:37 +00:00
Philip Reames 9ed1673703 [LoopPred] Convert a second member function to a static helper [NFC]
(And remember to actually mark the first one static.)

llvm-svn: 362415
2019-06-03 16:23:20 +00:00
Dmitri Gribenko 857de979a7 Revert "[llvm-ar] Fix relative thin archive path handling"
This reverts commit r362407.  It broke compilation of
llvm/lib/Object/ArchiveWriter.cpp:

error: type 'llvm::sys::path::const_iterator' does not provide a call
operator

llvm-svn: 362413
2019-06-03 16:21:37 +00:00
Nemanja Ivanovic 009d08f313 [PowerPC] Set PROT_READ flag for MF_EXEC to prevent segfaults on PPC machines
The big endian PPC buildbots are all failing now due to calls to cache
invalidation in unit tests on data that has only the PROT_EXEC flag set.
This has been an issue all along on FreeBSD but it can affect Linux machines
depending on configuration.

This patch mitigates the issue the same way it is mitigated on FreeBSD.

Since this is needed to bring the buildbots back to green, I plan to commit this
and allow for post-commit review, but I thought I would also post it here for
ease of access/readability.

Differential revision: https://reviews.llvm.org/D62741

llvm-svn: 362412
2019-06-03 16:20:59 +00:00
Philip Reames 0912b06f78 [LoopPred] Convert member function to free helper function [NFC]
llvm-svn: 362411
2019-06-03 16:17:14 +00:00
Dmitri Gribenko bedcaea99a Include what you use in LanaiInstrInfo.cpp
llvm-svn: 362408
2019-06-03 15:26:25 +00:00
Owen Reynolds fade9cbed7 [llvm-ar] Fix relative thin archive path handling
This fixes some thin archive relative path issues, paths are shortened where possible and paths are output correctly when using the display table command.

Differential Revision: https://reviews.llvm.org/D59491

llvm-svn: 362407
2019-06-03 15:26:07 +00:00
Dmitri Gribenko b3bd866c7f Include what you use in PPCInstrInfo.h
llvm-svn: 362405
2019-06-03 15:04:05 +00:00
Dmitri Gribenko 2b369f83c5 Include what you use in NVPTX.h
Other files were not relying on these transitive includes, so I'm
submitting this change separately.

llvm-svn: 362403
2019-06-03 14:37:26 +00:00
Dmitri Gribenko 14c69fefe6 Include what you use in NVPTX.h
I also fixed all other files that were including NVPTX.h and were
relying on transitive includes.

llvm-svn: 362402
2019-06-03 14:26:50 +00:00
Dmitry Preobrazhensky 9111f35f02 [AMDGPU][MC] Added support of SCC, VCCZ and EXECZ operands
See bug 39292: https://bugs.llvm.org/show_bug.cgi?id=39292

Reviewers: rampitec, arsenm

Differential Revision: https://reviews.llvm.org/D62660

llvm-svn: 362400
2019-06-03 13:51:24 +00:00
Simon Pilgrim cb7e4e8193 [SelectionDAG] Add [us]itofp(undef) --> 0 constant fold (PR39205)
We were missing this fold in the DAG, which I've copied directly from llvm::ConstantFoldCastInstruction

Differential Revision: https://reviews.llvm.org/D62807

llvm-svn: 362397
2019-06-03 13:02:07 +00:00
Dmitri Gribenko 7a3e4ab286 Include what you use in LanaiInstPrinter.cpp
llvm-svn: 362395
2019-06-03 12:53:05 +00:00
Dmitri Gribenko 2f66316c96 Include what you use in LanaiMCCodeEmitter.cpp
LanaiMCCodeEmitter.cpp was not using any APIs from Lanai.h, and was only
including it for transitive dependencies.  Doing so is problematic from
include-what-you-use perspective, but it is also a layering issue (it
creates a dependency cycle between the primary Lanai target library and
the MCTargetDesc library).

llvm-svn: 362394
2019-06-03 12:42:48 +00:00
Dmitri Gribenko c69ee63cb9 Include what you use in LanaiDisassembler.cpp
llvm-svn: 362392
2019-06-03 12:37:11 +00:00
Nicolai Haehnle edfa756f3f AMDGPU/GFX10: V_CMPX_xxx instructions still have an omod operand
Summary: Change-Id: If6ee98e4a723b643bc37254fc6ef8b3812db16da

Reviewers: rampitec

Subscribers: arsenm, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62720

Change-Id: Id547ef152b2f92b24dc1c0efbf7e4467c4fb4b6e
llvm-svn: 362390
2019-06-03 12:07:41 +00:00
Dmitri Gribenko 8668fc0102 Include what you use in HexagonInstPrinter.cpp
HexagonInstPrinter.cpp was not using any APIs from HexagonAsmPrinter.h.
Doing so is problematic from include-what-you-use perspective, but it is
also a layering issue (it creates a dependency cycle between the primary
Hexagon target library and the MCTargetDesc library).

llvm-svn: 362389
2019-06-03 11:41:22 +00:00
Dmitri Gribenko 61b49ccb77 Include what you use in HexagonAsmPrinter.h
llvm-svn: 362388
2019-06-03 11:41:18 +00:00
Dmitri Gribenko 03d1b33041 Include what you use in HexagonMCInstrInfo.cpp
HexagonMCInstrInfo.cpp was not using any APIs from Hexagon.h.  Doing so
is problematic from include-what-you-use perspective, but it is also a
layering issue (it creates a dependency cycle between the primary
Hexagon target library and the MCTargetDesc library).

llvm-svn: 362387
2019-06-03 11:25:37 +00:00
Dmitri Gribenko 970b9f961f Include what you use in HexagonMCCodeEmitter.cpp
HexagonMCCodeEmitter.cpp was not using any APIs from Hexagon.h.  Doing
so is problematic from include-what-you-use perspective, but it is also
a layering issue (it creates a dependency cycle between the primary
Hexagon target library and the MCTargetDesc library).

llvm-svn: 362386
2019-06-03 11:20:53 +00:00
Dmitri Gribenko ebe360edfa Include what you use in HexagonMCCompound.cpp
HexagonMCCompound.cpp was not using any APIs from Hexagon.h.  Doing so
is problematic from include-what-you-use perspective, but it is also a
layering issue (it creates a dependency cycle between the primary
Hexagon target library and the MCTargetDesc library).

llvm-svn: 362385
2019-06-03 11:20:48 +00:00
Dmitri Gribenko 6e076a081a Include what you use in HexagonShuffler.cpp
HexagonShuffler.cpp was not using any APIs from Hexagon.h, and was only
including it for transitive dependencies.  Doing so is problematic from
include-what-you-use perspective, but it is also a layering issue (it
creates a dependency cycle between the primary Hexagon target library
and the MCTargetDesc library).

llvm-svn: 362384
2019-06-03 11:14:20 +00:00
Dmitri Gribenko 6214b577b7 Include what you use in HexagonMCChecker.cpp
HexagonMCChecker.cpp was not using any APIs from Hexagon.h.  Doing so is
problematic from include-what-you-use perspective, but it is also a
layering issue (it creates a dependency cycle between the primary
Hexagon target library and the MCTargetDesc library).

llvm-svn: 362383
2019-06-03 11:14:15 +00:00
Dmitri Gribenko bf2a356ec0 Include what you use in HexagonMCTargetDesc.cpp
HexagonMCTargetDesc.cpp was not using any APIs from Hexagon.h.  Doing so
is problematic from include-what-you-use perspective, but it is also a
layering issue (it creates a dependency cycle between the primary
Hexagon target library and the MCTargetDesc library).

llvm-svn: 362382
2019-06-03 11:14:10 +00:00
Dmitri Gribenko beb7f48a29 Include what you use in HexagonMCShuffler.cpp
HexagonMCShuffler.cpp was not using any APIs from Hexagon.h.  Doing so
is problematic from include-what-you-use perspective, but it is also a
layering issue (it creates a dependency cycle between the primary
Hexagon target library and the MCTargetDesc library).

llvm-svn: 362381
2019-06-03 11:14:05 +00:00
Simon Tatham dc83a3c449 [ARM] Fix recent breakage of -mfpu=none.
The recent change D60691 introduced a bug in clang when handling
option combinations such as `-mcpu=cortex-m4 -mfpu=none`. Those
options together should select Cortex-M4 but disable all use of
hardware FP, but in fact, now hardware FP instructions can still be
generated in that mode.

The reason is because the handling of FPUVersion::NONE disables all
the same feature names it used to, of which the base one is `vfp2`.
But now there are further features below that, like `vfp2d16fp` and
(following D60694) `fpregs`, which also need to be turned off to
disable hardware FP completely.

Added a tiny test which double-checks that compiling a simple FP
function doesn't access the FP registers.

Reviewers: SjoerdMeijer, dmgreen

Reviewed By: dmgreen

Subscribers: lebedev.ri, javed.absar, kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D62729

llvm-svn: 362380
2019-06-03 11:02:53 +00:00
Dmitri Gribenko 7ebfbebfe1 Include what you use in HexagonELFObjectWriter.cpp
HexagonELFObjectWriter.cpp was not using any APIs from Hexagon.h, and
was only including it for transitive dependencies.  Doing so is
problematic from include-what-you-use perspective, but it is also a
layering issue (it creates a dependency cycle between the primary
Hexagon target library and the MCTargetDesc library).

llvm-svn: 362376
2019-06-03 09:56:40 +00:00
Nikola Prica 2d0106a110 [LiveDebugValues] Close range for previous variable's location when adding newly deduced location
When LiveDebugValues deduces new variable's location from spill, restore or
register copy instruction it should close old variable's location. Otherwise
we can have multiple block output locations for same variable. That could lead
to inserting two DBG_VALUEs for same variable to the beginning of the successor
block which results to ignoring of first DBG_VALUE.

Reviewers: aprantl, jmorse, wolfgangp, dstenb

Reviewed By: aprantl

Subscribers: probinson, asowda, ivanbaev, petarj, djtodoro

Tags: #debug-info

Differential Revision: https://reviews.llvm.org/D62196

llvm-svn: 362373
2019-06-03 09:48:29 +00:00
Dmitri Gribenko 0aa374a306 Include what you use in HexagonAsmBackend.cpp
HexagonAsmBackend.cpp was not using any APIs from Hexagon.h.  Doing so
is problematic from include-what-you-use perspective, but it is also a
layering issue (it creates a dependency cycle between the primary
Hexagon target library and the MCTargetDesc library).

llvm-svn: 362372
2019-06-03 09:43:05 +00:00
Dmitri Gribenko 301f8fd632 Include what you use in HexagonAsmParser.cpp
HexagonAsmParser.cpp was not using any APIs from Hexagon.h.  Doing so is
problematic from include-what-you-use perspective, but it is also a
layering issue (it creates a dependency cycle between the primary
Hexagon target library and the AsmParser library).

llvm-svn: 362370
2019-06-03 09:38:48 +00:00
Dmitri Gribenko c5327ab71d Include what you use in HexagonShuffler.h
HexagonShuffler.h was not using any APIs from Hexagon.h, and was only
including it for transitive dependencies.  Doing so is problematic from
include-what-you-use perspective, but it is also a layering issue (it
creates a dependency cycle between the primary Hexagon target library
and the MCTargetDesc library).

llvm-svn: 362369
2019-06-03 09:33:48 +00:00
Dmitri Gribenko 3c837201e0 Include what you use in BPFMCTargetDesc.cpp
BPFMCTargetDesc.cpp was not using any APIs from BPF.h.  Doing so is
problematic from include-what-you-use perspective, but it is also a
layering issue (it creates a dependency cycle between the primary
BPF target library and the MCTargetDesc library).

llvm-svn: 362368
2019-06-03 09:29:51 +00:00
Diogo N. Sampaio df92f84110 [ARM][FIX] Ran out of registers due tail recursion
Summary:
- pr42062
When compiling for MinSize,
ARMTargetLowering::LowerCall decides to indirect
multiple calls to a same function. However,
it disconsiders the limitation that thumb1
indirect calls require the callee to be in a
register from r0 to r3 (llvm limiation).
If all those registers are used by arguments, the
compiler dies with "error: run out of registers
during register allocation".
This patch tells the function
IsEligibleForTailCallOptimization if we intend to
perform indirect calls, as to avoid tail call
optimization.

Reviewers: dmgreen, efriedma

Reviewed By: efriedma

Subscribers: javed.absar, kristof.beyls, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62683

llvm-svn: 362366
2019-06-03 08:58:05 +00:00
Sam Parker a0bd6f8a1a [AArch64] Check for simple type in FPToUInt
DAGCombiner was hitting a SimpleType assertion when trying to combine
a v3f32 before type legalization.

bugzilla: https://bugs.llvm.org/show_bug.cgi?id=41916

Differential Revision: https://reviews.llvm.org/D62734

llvm-svn: 362365
2019-06-03 08:49:17 +00:00
Jim Lin 20b14dacbb [AVR] Fix incorrect source regclass of LDWRdPtr
Summary:
LDWRdPtr would be expanded to ld+ldd. ldd only accepts the pointer register is Y or Z.
So the register class of pointer of LDWRdPtr should be PTRDISPREGS instead of PTRREGS.

Reviewers: dylanmckay

Reviewed By: dylanmckay

Subscribers: dylanmckay, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62300

llvm-svn: 362351
2019-06-03 02:31:07 +00:00
Florian Hahn e71963c850 Recommit r360171: [DAGCombiner] Avoid creating large tokenfactors in visitTokenFactor.
If we hit the limit, we do expand the outstanding tokenfactors.
Otherwise, we might drop nodes with users in the unexpanded
tokenfactors. This fixes the crashes reported by Jordan Rupprecht.

Reviewers: niravd, spatel, craig.topper, rupprecht

Reviewed By: niravd

Differential Revision: https://reviews.llvm.org/D62633

llvm-svn: 362350
2019-06-03 01:30:19 +00:00
Nico Weber 54362477c7 llvm-undname; Add more test coverage for demangleFunctionClass()
Also add two FC_Far that seem to be missing, by symmetry from
the public and protected cases. (But FC_Far isn't really a thing
anymore, so this doesn't really have an observable effect.)

llvm-svn: 362344
2019-06-02 23:26:57 +00:00
Craig Topper 50b35caf30 [DAGCombiner][X86] Fold away masked store and scatter with all zeroes mask.
Similar to what was done for masked load and gather.

llvm-svn: 362342
2019-06-02 22:52:38 +00:00
Craig Topper 5f79d74946 [X86] Add test cases for masked store and masked scatter with an all zeroes mask. Fix bug in ScalarizeMaskedMemIntrin
Need to cast only to Constant instead of ConstantVector to allow
ConstantAggregateZero.

llvm-svn: 362341
2019-06-02 22:52:34 +00:00
Simon Pilgrim 8a32ca381d [CostModel][X86] Improve masked load/store AVX1/AVX2 costs
A mixture of internal tests and review of the scheduler models indicates we're overestimating the cost of a masked load, which we're estimating at 4x regular memory ops - more realistic values indicates that its closer to 2x. Masked stores costs are a lot more diverse but 8x is roughly in the middle of the range.

e.g. SandyBridge
defm : X86WriteRes<WriteFMaskedLoad, [SBPort23,SBPort05], 8, [1,2], 3>;
defm : X86WriteRes<WriteFMaskedLoadY, [SBPort23,SBPort05], 9, [1,2], 3>;
defm : X86WriteRes<WriteFMaskedStore, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>;
defm : X86WriteRes<WriteFMaskedStoreY, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>;

e.g. Btver2
defm : X86WriteRes<WriteFMaskedLoad, [JLAGU, JFPU01, JFPX], 6, [1, 2, 2], 1>;
defm : X86WriteRes<WriteFMaskedLoadY, [JLAGU, JFPU01, JFPX], 6, [2, 4, 4], 2>;
defm : X86WriteRes<WriteFMaskedStore, [JSAGU, JFPU01, JFPX], 6, [1, 1, 4], 1>;
defm : X86WriteRes<WriteFMaskedStoreY, [JSAGU, JFPU01, JFPX], 6, [2, 2, 4], 2>;

Differential Revision: https://reviews.llvm.org/D61257

llvm-svn: 362338
2019-06-02 20:37:02 +00:00
Craig Topper a7bc31ebc6 [DAGCombiner] Replace masked loads with a zero mask with the passthru value
Similar to what was recently done for gathers in r362015.

llvm-svn: 362337
2019-06-02 18:58:46 +00:00
Simon Pilgrim 59a8db628b [TTI][X86] Cleanup getMaskedMemoryOpCost. NFCI.
Prep work before resurrecting D61257.

llvm-svn: 362335
2019-06-02 18:06:42 +00:00